Post on 24-Dec-2015
transcript
© 2003-2008 ZHAW
Prof. Hans Weibel, Zurich University of Applied Scienceshans.weibel@zhaw.ch
Synchronization over Ethernet
Standard for a Precision Clock Synchronization Protocol according to IEEE 1588
Synchronous Ethernet according to ITU-T G.8261
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 2
Who is ZHAW – Zurich University of Applied Sciences?
The School of Engineering is a department of the Zurich University of Applied Sciences (ZHAW)
ZHAW‘s Institute of Embedded Systems has a strong commitment to industrial communications in general and to Ethernet in particular, e.g.
Real-time Ethernet (Ethernet Powerling, ProfiNet, etc.) Synchronization (IEEE 1588) High-availability Ethernet add-ons (MRP, PRP, etc.)
The related R&D activities and services include Hardware assistance and off-load (IP) Protocol stacks Support Engineering and consultancy
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 3
Preliminary remark
only Ethernet solutions are taken into account in this presentation (according to workshop planning)
this requires some compromises to be accepted
the big advantage to be exploited is that the same infrastructure can be used for both data transmission and synchronization
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 4
The Standard IEEE 1588
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 5
The Standard IEEE 1588 PTP Message Exchange
UDP
IP
MAC
Phy
PTP
UDP
IP
MAC
Phy
Master Clock Slave Clock
Delay and
JitterProtocol
Stack
Delay and JitterNetwork
Delay and JitterProtocolStack
Network
PTP
MII MII
PTP Precision Time Protocol (Application Layer)UDP User Datagram Protocol (Transport Layer)IP Internet Protocol (Network Layer)MAC Media Access ControlPhy Physical Layer
optional
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 6
The Standard IEEE 1588 Determination of Phase Change Rate (Drift) – one step
Sync(t0k)
t0k
t1k
Master Clock
Slave Clock40
42
44
46
48
50
52
54
56
58
60
62
64
40
42
44
46
48
50
52
54
56
58
60
62
38
Sync(t0k+1)
t0k+1
t1k+1
Δ0
Δ1
Δ0 = t0k+1
- t0 k
Δ1 = t1k+1 - t1
k
Drift = Δ 1 - Δ 0
Δ 1
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 7
The Standard IEEE 1588 Determination of Phase Change Rate (Drift) – two step
Follow_up(t0k)
Sync()t0
k
t1k
Master Clock
Slave Clock40
42
44
46
48
50
52
54
56
58
60
62
64
40
42
44
46
48
50
52
54
56
58
60
62
38
Sync()t0
k+1
Follow_up(t0k+1) t1
k+1
Δ0 = t0k+1
- t0 k
Δ1 = t1k+1 - t1
k
Drift = Δ 1 - Δ 0
Δ 1
Δ0
Δ1
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 8
The Standard IEEE 1588 Determination of Delay and Offset
Follow_up(t0)
Sync(t0)t0
Delay_Resp(t3)
t3 = t2-O+D
apparent concurrencyO = Offset = ClocksSlave – ClocksMaster
Delay_Req()
t3
t2B
measured values t0, t1, t2, t3
A = t1-t0 = D+O
B = t3-t2 = D-O
Delay D =
Offset O =
A + B2
A - B2
t1 = t0+D+O
A
O
D = Delay
Master Clock Slave Clock40
42
44
46
48
50
52
54
56
58
60
62
64
40
42
44
46
48
50
52
54
56
58
60
62
38
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 9
The Standard IEEE 1588 Boundary Clock copes with the Network‘s Delay Fluctuations
PTP
UDP
IP
MAC
Phy
PTP
UDP
IP
MAC
Phy
MAC
Phy
MAC
Phy
Switch with Boundary ClockMaster Clock Slave Clock
Switching Function
PTP
UDP
IP
Slave
PTP
UDP
IP
Master
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 10
The Standard IEEE 1588 Topology and „Best Master Clock“
M
M
S
M M
M
S
M M
S
SSSS
Ordinary Clock, Grandmaster: clock selected as „best Master“ (selection basedon comparison of clock descriptors)
Ordinary Clock
Boundary Clock, e.g. Ethernet switch
S: Port in Slave StateM: Port in Master State
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 11
The Standard IEEE 1588 Version 2Transparent Clock
Delay_Resp(t3 , ∑corr) Time Stamping
Master Clock Slave Clock
t t
t0Sync(t0 , corr)
t1
Delay_Req(corr + Δr)t3
t2
Sync(t0 , corr + Δs)
Delay_Req(corr)
Δs
Δr
Transparent Clock
Δ Residence Time
Follow_up(t0)
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 12
The Standard IEEE 1588 Version 2 Transparent Clock – End-to-End Delay Measurement
M
S
S
S
S
SSync Stream e2e Delay Measurement
TC
TC
TC
TC
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 13
The Standard IEEE 1588 Version 2 Transparent Clock – Peer-to-Peer Delay Measurement
M
S
S
S
S
S
TC
TC
TC
TC
Sync Stream p2p Delay Measurement
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 14
The Standard IEEE 1588 Limits
Timestamp quantization effects
Accuracy of Start-of-Frame Detection
Unknown portion of data path asymmetries in cables and transceivers
Jitter in the data path (PHY chips, network elements)
Environmental conditions
Oscillator instabilities
Implementation specific effects (e.g. phase between different asynchronous clock domains of all involved functional building blocks)
Note: Uncertainty due to limited observation capabilities (e.g. the PPS output is subject of quantization effects as well)
Stochastic effects can be filtered out with statistical methods
Systematic errors remain
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 15
The Standard IEEE 1588 Industry Relevance
PTP is or will be applied in application areas such as Test and Measurement (LXI: LAN eXtensions for Instrumentation) Automation and control systems (various flavors of real-time Ethernets) Audio/Video Bridge (AVB according to IEEE 802.1as) Telecommunications
Silicon vendors and IP providers offer Protocol software Hardware assistance IPs PHYs with hardware assistance logic IEEE-1588 enabled microcontrollers Switching cores with IEEE-1588 support
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 16
Synchronous Ethernet
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 17
Synchronous EthernetPhysical Layer Timing in Legacy Ethernet
Ethernet works perfectly well with relatively inaccurate clocks
Each Ethernet link may use its own clock nominal clock rate is the same, but deviations of ± 50 ppm are allowed
(dimensioning such that physical layer buffers do not underflow or overflow)
Details differ according to transmission technology where the two directions of a link use different media (i.e. separate wire pairs
or separate fibers), both directions may have independent clocks GBE over twisted pair uses all wire pairs simultaneously in both directions
signal processing (echo compensation technique) requires same clock on both directions of a link one PHY acts as the master, the other as slave
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 18
Synchronous EthernetTiming of a Fast Ethernet Link (100 Base-TX)
RX_CLK
25 MHz ± 50 ppm
25 MHz ± 50 ppm
TX_CLK
TX_CLK
RX_CLK
PHYMAC PHY MAC
clk
transmission lineis driven by clk
clk recovered fromtransmission line
clk
Symbol
Cable
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 19
Synchronous EthernetPhysical Layer Timing in Legacy Ethernet
E
E
E
E
E
E
X
X
X
X
X
X
X
X
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 20
Synchronous EthernetTiming of a Gigabit Ethernet Link (1000 Base-T)
1000 Base-T transmission is split on 4 wire pairs operation simultaneously in both directions
transmitter and receiver are coupled via a hybrid echo compensation is applied both directions require the same clock
A 1000 Base-T PHY can operate as a master or slave.
Master/slave role selection is part of the auto-negotiation procedure.
A prioritization scheme determines which device will be the master and which will be slave.
The supplement to Std 802.3ab, 1999 Edition defines a resolution function to handle any conflicts:
multiport devices have higher priority to become master than single port devices. if both devices are multiport devices, the one with higher seed bits becomes the
master.
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 21
Synchronous Ethernet1000 Base-T uses 4 pairs simultaneously in both directions
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 22
Synchronous Ethernet1000 Base-T Pysical Layer Signalling with Echo Compensation
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 23
Synchronous EthernetTiming of a Gigabit Ethernet Link (1000Base-T)
RX_CLK
25 MHz ± 50 ppm
25 MHz ± 50 ppm
GTX_CLK
GTX_CLK
RX_CLK
PHYMAC PHY MAC
Master Slave
The Master PHY uses the internal 125 MHz clock generated from CLOCK_IN to transmit data on the 4 wire pairs.
The Slave PHY uses the clock recovered from the opposite PHY as the transmit clock.
x5
CLOCK_IN
Cable
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 24
Synchronous EthernetConcept - 1
Concept has been proposed, elaborated, and standardized by the Telco community in ITU-T by transferring the traditional SDH clock distribution concept to Ethernet networks
The Primary Reference Clock (PRC) frequency is distributed on the physical layer
a receiver can lock to the transmitter‘s frequency a switch selects the best available clock this results in a hierarchical clock distribution tree
OAM messages (Synchronization Status Messages) are used to signal clock quality and sync failure conditions of the upstream switch
to allow selection of the best available timing source (stratum of upstream source)
to avoid timing loops
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 25
Synchronous EthernetConcept - 2
Active layer 2 data forwarding topology (as established by spanning tree protocol) and clock distribution tree are independent (i.e. a blocked port can deliver the clock to its neighboring switch)
Design rules (topology restrictions, priorities for source selection) guarantee clock quality
Clocking of Ethernet devices is changed in a way that is fully conforming with IEEE 802.3 standards
Standard PHY chips can be used as long as a few conditions are met, e.g. PHY provides the recovered receive clock to the external world GBE PHY allows master/slave role to be set by software (no automatic
selection)
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 26
Synchronous EthernetClock Sources for a Synchronous Ethernet Switch
Clock Selection / Regeneration
Oscillator
Ext-In Ext-Out
Port 1 Port 2 Port … Port n
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 27
Synchronous EthernetPhysical Layer Timing in Synchronous Ethernet
E
E
E
E
E
E
X
X
X
X
PRC
X
X
X
X
PRC tracable clock (other links and directions are free running)
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 28
Synchronous EthernetCompared with IEEE 1588
Synchronous Ethernet Clock distribution based on
Ethernet‘s physical layer
Provides frequency only
Performance is independent of data traffic
IEEE 1588 Application layer protocol with
hardware assistance
Provides frequency and time of day
May be susceptible to specific data traffic patterns
Complementary technologies, can be used in combination:
Syncronous Ethernet delivers accurate and stable frequency to all nodes while IEEE 1588 can deliver time of day, where required.
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 29
Synchronous EthernetIndustry Relevance
Telco equipment manufacturers rely on both technologies
Synchronous Ethernet operation will certainly be an important feature in future carrier grade products
Synchronous Ethernet’s role in corporate and industrial communication application is not yet forseeable
Silicon vendors and IP providers offer Synchronous Ethernet compatible PHYs ICs for clock monitoring, selection, and processing
© ZHAW / H. Weibel, 15.2.2008 CERN_Sync_Workshop.ppt / Folie 30
Many thanks for your attention!
hans.weibel@zhaw.ch
Zurich University of Applied Sciences Institute of Embedded Systemshttp://ines.zhaw.ch/ieee1588