Post on 03-Apr-2018
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MicroBlazeSoft-core Processor
Highly Configurable
32-bit Architecture
Master Component for Creating aMicroController
Thirty-two 32-bit general purpose
registers32-bit instruction word with three
operands and two addressing
modes32-bit address busSingle issue pipeline
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DXCL_M
DXCL_S
Data-sideInstruction-side
DOPB
DLMB
IOPB
ILMB
bus interface bus interface
InstructionBuffer
ProgramCounter
Register File32 X 32b
ALU
InstructionDecode
BusIF
BusIF
MFSL 0..7
SFSL 0..7
IXCL_M
IXCL_S
I-Cache
D-Cache
Shift
Barrel Shift
Multiplier
Divider
FPU
SpecialPurposeRegisters
Optional MicroBlaze feature
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Harvard Architecture
Bus Interfaces
Registers
General Purpose
Special Function
ALU
Instruction Processing
R
DXCL_M
DXCL_S
Data-sideInstruction-side
DOPB
DLMB
IOPB
ILMB
bus interface bus interface
InstructionBuffer
ProgramCounter
Register File32 X 32b
ALU
InstructionDecode
BusIF
BusIF
MFSL 0..7
SFSL 0..7
IXCL_M
IXCL_S
I-Cache
D-Cache
Shift
Barrel Shift
Multiplier
Divider
FPU
SpecialPurposeRegisters
Optional MicroBlaze feature
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See Harvard Architecture
http://en.wikipedia.org/wiki/Harvard_architecturehttp://en.wikipedia.org/wiki/Harvard_architecture7/28/2019 02-MB Programming Model
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Microcontroller
Attributes (1/3)
Attribute Option 1 Option 2
Instruction / data
ports Separate (Harvard) Unified (Princeton)
Data memory read/write operations
Only by load/storeinstructions (RISC)
Any instruction canread/write memory
(CISC)
External input/output
Use load/storeinstructions
(memory-mapped)
Special I/Oinstructions
See Harvard Architecture
See RISC and CISCSee Memory Mapped I/O
http://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/Complex_instruction_set_computerhttp://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/Memory-mapped_IOhttp://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/Complex_instruction_set_computerhttp://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/Complex_instruction_set_computerhttp://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/Complex_instruction_set_computerhttp://en.wikipedia.org/wiki/Harvard_architecturehttp://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/Complex_instruction_set_computerhttp://en.wikipedia.org/wiki/Harvard_architecturehttp://en.wikipedia.org/wiki/Memory-mapped_IOhttp://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/Complex_instruction_set_computerhttp://en.wikipedia.org/wiki/Harvard_architecturehttp://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/Harvard_architecturehttp://en.wikipedia.org/wiki/Memory-mapped_IOhttp://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/Harvard_architecturehttp://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/Harvard_architecturehttp://en.wikipedia.org/wiki/Memory-mapped_IOhttp://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/Complex_instruction_set_computerhttp://en.wikipedia.org/wiki/Harvard_architecturehttp://en.wikipedia.org/wiki/Memory-mapped_IOhttp://en.wikipedia.org/wiki/Memory-mapped_IOhttp://en.wikipedia.org/wiki/Complex_instruction_set_computerhttp://en.wikipedia.org/wiki/Complex_instruction_set_computerhttp://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/RISChttp://en.wikipedia.org/wiki/Harvard_architecturehttp://en.wikipedia.org/wiki/Harvard_architecture7/28/2019 02-MB Programming Model
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Microcontroller
Attributes (3/3)
Attribute Option 1 Option 2
Byte order withinwords Big-endian Little-endian
# of instructionoperands
Two operand(rDrD op rS)
Three operand(rDrA op rB)
Addressing modes Few (RISC) Many (CISC)
See Endianness
See Addressing Modes
http://en.wikipedia.org/wiki/Endiannesshttp://www.google.com/ighttp://www.google.com/ighttp://www.google.com/ighttp://www.google.com/ighttp://www.google.com/ighttp://www.google.com/ighttp://www.google.com/ighttp://en.wikipedia.org/wiki/Endiannesshttp://en.wikipedia.org/wiki/Endianness7/28/2019 02-MB Programming Model
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Simplified MicroBlaze
Architecture
Which of the preceding processor
attributes may be inferred from this block
diagram?
DXCL_M
DXCL_S
Data-sideInstruction-side
DOPB
DLMB
IOPB
ILMB
bus interface bus interface
InstructionBuffer
ProgramCounter
Register File32 X 32b
ALU
InstructionDecode
BusIF
BusIF
MFSL 0..7
SFSL 0..7
IXCL_M
IXCL_S
I-Cache
D-Cache
Shift
Barrel Shift
Multiplier
Divider
FPU
SpecialPurposeRegisters
Optional MicroBlaze feature
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Simplified MicroBlaze
Architecture
Harvard Architecture
RISC
Load/Store Architecture 3 or 5 Stage Pipeline (currently 5)
32-bit Datapaths
Byte Addressable
Big Endian
Two Addressing Modes
2 or 3 Operand Instructions ili
_
_
i
DOPB
DLMB
IOPB
ILMB
InstructionBuffer
ProgramCounter
Register File32 X 32b
ALU
Instruction
Decode
BusIF
BusIF
I-Cache
D-Cache
Shift
Barrel Shift
Multiplier
Divider
FPU
SpecialPurposeRegisters
i i l
ANSWERS
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Advanced Processor
Attributes
Superscalar
Speculative, out-of-order execution
Branch prediction Multi-threaded
These techniques improve
performance, but increase powerconsumption
For more info, click on the above links
and/or take an advanced computerarchitecture course
http://en.wikipedia.org/wiki/Multithreadedhttp://en.wikipedia.org/wiki/Multithreadedhttp://en.wikipedia.org/wiki/Branch_predictionhttp://en.wikipedia.org/wiki/Branch_predictionhttp://en.wikipedia.org/wiki/Out-of-order_executionhttp://en.wikipedia.org/wiki/Out-of-order_executionhttp://en.wikipedia.org/wiki/Superscalarhttp://en.wikipedia.org/wiki/Superscalar7/28/2019 02-MB Programming Model
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MicroBlaze Native Data
Types 1/3
32-bit word
(4 bytes)Address: n n+1 n+2 n+3
Alignment: n should be a multiple of 4
Bit labeling: [0...31]
Byte significance: [most,,,least]
Example:0x12345678 0x12 0x34 0x56 0x78
Big-endian
Viewed as a32-bit word at
address n
Viewed as a sequence of 4 bytesstarting at address n
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MicroBlaze Native Data
Types 2/3
16-bit word
(2 bytes)Address: n n+1
Alignment: n should be a multiple of 2
Bit labeling: [0..15]
Byte significance: [most, least]
Example:
0x2468 0x24 0x68Big-endian
Viewed as a16-bit word at
address n
Viewed as a sequenceof 2 bytes starting at
address n
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MicroBlaze Native Data
Types 3/3
8-bit word
(1 byte)Address: n
Alignment: none
Bit significance: most least
Bit labeling: [0 7]
Example:
0x13
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Type A Instructions
Opcode Destination reg Source reg A Source reg B 0 0 0 0 0 0 0 0 0 0 0
Bit: 0 6 11 16 21 31
Example:
Add contents of r24 and r27, and store the sum in register r25
Assembly language:
add r25, r24, r27
Machine code:
0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0
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Does Not Add Up
6-bit opcode => 64 instructions
How are the other 60 instructionsdistinguished?
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Dealing Efficiently with
Constants
-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10
Occurrence
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Questions
1. Why is it important for an embeddedprocessor to deal efficiently with
constants?
2. How should we optimize using 0?
3. Should we make a special case ofn-bitconstants, where n < 32?
4. What if we need a 32-bit constant?