Post on 12-Jan-2016
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Implementation of PaginImplementation of Paging in uCOS-IIg in uCOS-II
2010042220100422
Ke, Dian ChiaKe, Dian Chia
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OutlineOutline
uCOS-II Application ModeluCOS-II Application Model x86 Operating Modex86 Operating Mode x86 Interruptx86 Interrupt Disk I/ODisk I/O Testing ResultTesting Result Q & AQ & A AppendixAppendix
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uCOS-II Application Model (1 / uCOS-II Application Model (1 / 2)2)
OS_STK TaskStk[N_TASKS][STK_SIZE];
…
main(){
…
OSInit();
…
OSTaskCreate(task, (void *)0, &TaskStk[0][STK_SIZE - 1], 0);
OSStart();
}
task(){
…
}
OS_InitTCBList();
OS_MemInit();
…
OS_TCB OSTCBTbl[] in os_core.c
OSTCBStkPtr
OSTCBFreeList
OSTCBPrio
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uCOS-II Application Model (2 / uCOS-II Application Model (2 / 2)2)
… … …
tick tick tick
1 10
TaskStart ready
main starts
main ends
TaskStart starts
tick ISR and rate set
other tasks ready
………..
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x86 Operating Mode (1 / 11)x86 Operating Mode (1 / 11)
real modereal mode All start up in real mode at power-on; 80186 and earlier All start up in real mode at power-on; 80186 and earlier
had only real mode.had only real mode. protected modeprotected mode
The foundation for all subsequent enhancements to the x86 The foundation for all subsequent enhancements to the x86 architecture.architecture.
virtual 8086 modevirtual 8086 mode 80386 and later, virtual real mode, V86-mode or VM86 is 80386 and later, virtual real mode, V86-mode or VM86 is
whereby the CPU (in protected mode) is running an whereby the CPU (in protected mode) is running an “emulated" 16bit “segmented” model (real mode) machine.“emulated" 16bit “segmented” model (real mode) machine.
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x86 Operating Mode (2 / 11)x86 Operating Mode (2 / 11)
unreal modeunreal mode unreal mode, big real mode, huge real mode, or flat real unreal mode, big real mode, huge real mode, or flat real
mode, is a variant of real mode in which one or more data mode, is a variant of real mode in which one or more data segment registers have been loaded with 32-bit addresses segment registers have been loaded with 32-bit addresses and limits.and limits.
system management modesystem management mode First released with 386SL, a mode in which all normal First released with 386SL, a mode in which all normal
execution (including OS) is suspended, and special execution (including OS) is suspended, and special separate software (firmware or hardware-assisted separate software (firmware or hardware-assisted debugger) is executed in high-privilege mode.debugger) is executed in high-privilege mode.
long modelong mode x86-64x86-64
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x86 Operating Mode (3 / 11)x86 Operating Mode (3 / 11)real modereal mode
20 bit segmented memory address space, 20 bit segmented memory address space, 222020 = 1 MB of addressable memory = 1 MB of addressable memory
direct software access to BIOS routines direct software access to BIOS routines and peripheral hardwareand peripheral hardware
no memory protection, multi-tasking or no memory protection, multi-tasking or code privilege levelscode privilege levels
A20 lineA20 line Gate-A20 of IBM Personal Computer ATGate-A20 of IBM Personal Computer AT
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x86 Operating Mode (4 / 11)x86 Operating Mode (4 / 11)real modereal mode
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x86 Operating Mode (5 / 11)x86 Operating Mode (5 / 11)protected modeprotected mode
virtual memory, paging, multi-tasking, …virtual memory, paging, multi-tasking, … first released with 80286first released with 80286
16-bit offset, 64KB segments16-bit offset, 64KB segments 24-bit address bus, 16MB24-bit address bus, 16MB only resetting to enter real modeonly resetting to enter real mode
extended with 80386extended with 80386 32-bit offset, 4GB segments32-bit offset, 4GB segments 32-bit address bus, 4GB32-bit address bus, 4GB security and stabilitysecurity and stability
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x86 Operating Mode (6 / 11)x86 Operating Mode (6 / 11)protected modeprotected mode
enteringentering GDT created with a minimum of three entries: null, code and data segment descriptorGDT created with a minimum of three entries: null, code and data segment descriptor load GDTload GDT disable interruptdisable interrupt 21st address line (A20) enabled21st address line (A20) enabled ; set PE bit; set PE bit
mov eax, cr0mov eax, cr0or eax, 1or eax, 1mov cr0, eaxmov cr0, eax
; far jump (cs = selector of code segment); far jump (cs = selector of code segment)jmp cs:@pmjmp cs:@pm
@pm:@pm:; Now we are in PM.; Now we are in PM.
exitingexiting loading segment registers with real mode values, disabling A20 line, clearing PE bit in thloading segment registers with real mode values, disabling A20 line, clearing PE bit in th
e CR0 registere CR0 register
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x86 Operating Mode (7 / 11)x86 Operating Mode (7 / 11)protected modeprotected mode
privilege levelsprivilege levels
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x86 Operating Mode (8 / 11)x86 Operating Mode (8 / 11)protected modeprotected mode
segment addressingsegment addressing
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x86 Operating Mode (9 / 11)x86 Operating Mode (9 / 11)protected modeprotected mode
segment descriptor entrysegment descriptor entry
G = 0G = 0 G = 1G = 1
limit granularity limit granularity 1 byte1 byte 4KB4KB
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x86 Operating Mode (10 / 11)x86 Operating Mode (10 / 11)unreal modeunreal mode
64 KCS
Too big object
Where to put ?
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x86 Operating Mode (11 / 11)x86 Operating Mode (11 / 11)unreal modeunreal mode
cli ; interrupts offpush ds ; save segment
lgdt [gdtinfo] ; load gdt
mov eax, cr0 ; switch to pmode byor al, 1 ; set pmode bitmov cr0, eax
mov bx, 0x08 ; some descriptormov ds, bx ; cache set
and al, 0xFE ; back to real modemov cr0, eax ; by toggling bit again
pop ds ; get back old segmentsti ; interrupts on
mov bx, 0x0f01 ; attrib/char of smileymov eax, 0x0b8000 ; note 32 bit offsetmov word [ds: eax], bx
cached
8 Bytes
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x86 Interrupt (1 / 4)x86 Interrupt (1 / 4)
ISR stores information about interrupts that are being serviced.
IRR saves information about all interrupt requests to be serviced.
IMR stores the information which interrupt request to be masked.
PR resolves which interrupt request has the highest priority.
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x86 Interrupt (2 / 4)x86 Interrupt (2 / 4)
system timerkeyboard
serial port 2 or 4serial port 1 or 3LPT port 2 or sound cardfloppy disk controller
LPT port 1 or sound card
real-time clock
primary ATA channelsecondary ATA channel
PS/2 connector mouse
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x86 Interrupt (3 / 4)x86 Interrupt (3 / 4)
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x86 Interrupt (4 / 4)x86 Interrupt (4 / 4)
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Disk I/O (1 / 2)Disk I/O (1 / 2)Port Read/Write Misc
----- -------------- -------------------------------------------------
1f0 r/w data register, the bytes are written/read here
1f1 r error register (look these values up yourself)
1f2 r/w sector count, how many sectors to read/write
1f3 r/w sector number, the actual sector wanted
1f4 r/w cylinder low, cylinders is 0-1024
1f5 r/w cylinder high, this makes up the rest of the 1024
1f6 r/w drive/head
bit 7 = 1
bit 6 = 0
bit 5 = 1
bit 4 = 0 drive 0 select
= 1 drive 1 select
bit 3-0 head select bits
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Port Read/Write Misc
----- -------------- -------------------------------------------------
1f7 r status register
bit 7 = 1 controller is executing a command
bit 6 = 1 drive is ready
bit 5 = 1 write fault
bit 4 = 1 seek complete
bit 3 = 1 sector buffer requires servicing
bit 2 = 1 disk data read corrected
bit 1 = 1 index - set to 1 each revolution
bit 0 = 1 previous command ended in an error
1f7 w command register
50h format track
20h read sectors with retry
21h read sectors without retry
22h read long with retry
23h read long without retry
30h write sectors with retry
31h write sectors without retry
32h write long with retry
33h write long without retry
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Testing Result (1 / 3)Testing Result (1 / 3)OS tick rate 100
#tasks 8
OTimeDly 1
attempts range 0x1000
#attempts per tick 5
sw/sec 902
0
20
40
60
80
100
time (second)
page
faul
t rat
io (%
)
RAND FIFO RAND + 2nd chance LRU FIFO + 2nd chance LRU
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Testing Result (2 / 3)Testing Result (2 / 3)
0
20
40
60
80
100
time (second)
page
faul
t rat
io (%
)
RAND FIFO RAND + 2nd chance LRU FIFO + 2nd chance LRU
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Testing Result (3 / 3)Testing Result (3 / 3)
0
20
40
60
80
100
120
time (second)
page
faul
t rat
io (%
)
RAND FIFO RAND + 2nd chance LRU FIFO + 2nd chance LRU
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Q & AQ & A
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AppendixAppendix Linux Booting Involved (1 / 5)Linux Booting Involved (1 / 5)
hardware RESEThardware RESET
BIOS POST…BIOS POST… boot device chosen, copy MBR (512 Bytes, stage 1 boot device chosen, copy MBR (512 Bytes, stage 1
LILO) into memory 0x7c00 (also check LILO) into memory 0x7c00 (also check /arch/i386/boot/bootsect.S)/arch/i386/boot/bootsect.S)
visible selectorvisible selector 0xf0000xf000
hidden base addr.hidden base addr. 0xffff00000xffff0000
0xffff0000 + 0xfff0 = 0xfffffff0 (BIOS, mapped by hardware into RAM)
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AppendixAppendix Linux Booting Involved (2 / 5)Linux Booting Involved (2 / 5)
cs: ip = 0x7c0: 0x0 cs: ip = 0x7c0: 0x0 = 0x7c00= 0x7c00
ss = es = ds = cs, sp ss = es = ds = cs, sp = 0x7c00= 0x7c00
MBR 512 Bytes
First 512 Bytes of kernel
512 Bytes
stage 2 LILO
decompressed kernel
0x7c00
0x900000x90200
0x96a000x969ff
0x96c00
0x98000
0x100000 (1 M)
move
jump
real mode stack
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AppendixAppendix Linux Booting Involved (3 / 5)Linux Booting Involved (3 / 5)
setup() (/arch/i386/boot/setup.S)setup() (/arch/i386/boot/setup.S) reinitialize all hardwarereinitialize all hardware set A20 lineset A20 line switch to protected mode with a temp GDTswitch to protected mode with a temp GDT
cs = 0x9020 cs = 0x9020 cs = a 4G code segment cs = a 4G code segment
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AppendixAppendix Linux Booting Involved (4 / 5)Linux Booting Involved (4 / 5)
startup_32() (start of compressstartup_32() (start of compressed image, /arch/i386/boot/comed image, /arch/i386/boot/compressed/head.S)pressed/head.S) decompress kernel to 0x100000decompress kernel to 0x100000 ljmp $(__BOOT_CS), $0x10000ljmp $(__BOOT_CS), $0x10000
00
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AppendixAppendix Linux Booting Involved (5 / 5)Linux Booting Involved (5 / 5)
startup32() (uncompressed, /astartup32() (uncompressed, /arch/i386/kernel/head.S)rch/i386/kernel/head.S) initialize segment reg.initialize segment reg. fill bss segment of kernel with fill bss segment of kernel with
zeroszeros set page directory into cr3, enaset page directory into cr3, ena
ble pagingble paging lgdt and lidt with the final GDTlgdt and lidt with the final GDT
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AppendixAppendix A Simple Segmentation Sample (1 / 3)A Simple Segmentation Sample (1 / 3)
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AppendixAppendix A Simple Segmentation Sample (2 / 3)A Simple Segmentation Sample (2 / 3)
ecx = original esp + 4
original esp
espebporiginal esporiginal ebp
esp ecx
esp
20j = 0
8
k = &j
12points to
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AppendixAppendix A Simple Segmentation Sample (3 / 3)A Simple Segmentation Sample (3 / 3)
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AppendixAppendixProcess Address Space (1 / 6)Process Address Space (1 / 6)
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AppendixAppendixProcess Address Space (2 / 6)Process Address Space (2 / 6)
pgd_t *
pgd
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AppendixAppendixProcess Address Space (3 / 6)Process Address Space (3 / 6)
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AppendixAppendixProcess Address Space (4 / 6)Process Address Space (4 / 6)
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AppendixAppendixProcess Address Space (5 / 6)Process Address Space (5 / 6)
text0x8048000
0x80bd4820x80be0000x80be484
0x80bec200x80bf000
0x80e3000
0xb8017000
0xb8018000
0xb8019000
0xbf804000
0xbf819000
data
0x80c1000
0xbf8180e0stack
mmap
bss
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AppendixAppendixProcess Address Space (6 / 6)Process Address Space (6 / 6)
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0x80be46c = 00001000000010111110010001101100
Dir Table Offset
0
0x80be46c
gloInitData
0x2fe4b067
pgd at 0xeff3a080
pte at 0xefe4b2f8
0x1def0067
__USER_DS, 0x7b
CR3 0xeff3a000
0x2fe4b000
0x1def00000x1def046c
content in 0x1def046c is 0x1e