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Advanced Porting The Advanced Porting The FrameworkFramework
Intel Corporation Software and Services Group
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Copyright © 2006-2008 Intel Corporation•Other trademarks and brands are the property of their respective owners
Slide 2
Agenda
• Create a New Platform Build • Minimal porting job to run EFI Shell• Platform specific porting features
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Slide 3
Create a New Project Directory• Identify the Platform that this Project is a part of,
PROJECT_PLATFORM. Platforms are usually closely tied to a processor/north bridge/south bridge combination.
• Choose a Project name, PROJECT_NAME. This is often defined in the PlatformTools.env. Currently we are describing Bearlake as an example project name.
• Choose a Project family, PROJECT_FAMILY. This is often defined in the PlatformTools.env.
• The Platform\PROJECT_FAMILY\• PROJECT_PLATFORM directory to Platform\
PROJECT_FAMILY \PROJECT_NAME. In the case of the Bearlake example platform, the source directory to copy is Platform\IntelDpg\PROJECT_PLATFORM.
New Platform Build
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Slide 4
The Framework Directory Tree8.x code base
\ Framework\ Application\ Bus\ Chipset
\ Lakeport - MemoryInit\ Blackford - MemoryInit\ ESB2\ IntelIch - ICHX - SmBus\ SMC
\ CPU\ CSM\ GUID\ Include\ Library\ Platform
\ IntelDpg – Lakeport Pei – Dxe - Platform\ IntelEsg – StarLake Pei – Dxe - Platform
\ IntelSSG \ Lakeport - Build
\ Ppi\ Protocol\ Tools
Bearlake
Bearlake
Bearlake
ICHX
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Slide 5
Agenda
• Create a New Platform Build • Minimal porting job to run EFI Shell• Platform specific porting features
• \$(PLATFORM_SOUTH_PATH) for LAKEPORT is \IntelDpg\Lakeport
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Slide 6
General Overview
SECurity
Pre-Efi Initialization
Driver Xecution Environment
Boot Device Selection
PEI
DXE
BDS
OS
PWR ON
SEC
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Slide 7
Boot Flow
Pre EFIInitialization
(PEI)
Driver Execution
Environment (DXE)
Boot DevSelect(BDS)
Transient System Load
(TSL)
After Life(AL)
Power on [ . . Platform initialization . . ] [ . . . . OS boot . . . . ] Shutdown
Run Time(RT)
?
OS-PresentApp
Final OS Environment
Final OS Boot Loader
OS-AbsentApp
Transient OS Environment
Transient OS Boot Loader
Boot Manager
CPUInit
Chipset Init
Board Init
veri
fy
Device, Bus, or Service Driver
ExposedPlatformInterface
Pre Verifier
EFI Driver Dispatche
r
Intrinsic Servicessecurity
Security (SEC)
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Slide 8
System Block Diagramleg
acy OS
Lo
ader
legacy O
SL
oad
er
HardwareHardware
Pre-EFI ModulesHardware Specific
Co
mp
atibility
Su
pp
ort M
od
ule
EFI OS Loader
Platfo
rm D
rivers
E F I
EF
I D
rivers
Architectural Protocols
PEI FoundationDXE Foundation
Co
mp
atibility
Su
pp
ort M
od
ule
EFI OS Loader
Fram
ewo
rk D
rivers
Platfo
rm D
rivers
E F I
EF
I D
rivers
Pre-E
FI In
itiialization
(P
EI)
Foundations
legacy
Op
tion
R
OM
s
legacy
Op
tion
R
OM
s
Driv
er Exe
cutio
n E
nviro
nm
ent
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Slide 9
The Framework Directory Tree8.x code base
\ Framework\ Application\ Bus\ Chipset
\ BearLake - MemoryInit\ Blackford - MemoryInit\ ESB2\ IntelIch - ICHX - SmBus\ SMC
\ CPU\ CSM\ GUID\ Include\ Library\ Platform
\ IntelDpg – Bearlake Pei – Dxe - Platform\ IntelEsg – StarLake Pei – Dxe - Platform
\ IntelSSG \ Bearlake - Build \ StarLake - Build
\ Ppi\ Protocol\ Tools
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Slide 10
Porting SEC
• Reset Fetches Code from FLASH– Enables Flat Protected Mode Execution
• SEC Enables Temp Memory– Data and Stack Cached– Enables Execution of C Code– Transfers Control to PEI Foundation
Minimal porting job to run EFI Shell
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Slide 11
Temporary Memory0xFFFF_FFFF
System ROM (16 MB)
0x0000_0000
0xFF00_0000
0xFEC0_0000
0xZZZ0_0000
0xYYY0_0000
Low Top Of Memory
0xFEF0_0000
0xFEE0_0000
0xFED0_0000
System FLASH (512 KB)
0xFFF8_0000
SEC Maps Unused Region as Temporary Memory
Temp Memory
Local APIC
I/O APIC
PCI Resources
System Memory
Framework Codeand Data Stored Here
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Slide 12
SEC phase
• Currently SEC phase is where the Reset vector will start
• \Platform\$(PLATFORM_SOUTH_PATH)\Common\Sec\Ia32\ResetVec.asm
• \Platform\$(PLATFORM_SOUTH_PATH)\Common\Sec\Ia32\Flat32.asm
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Slide 13
PEI Phase
• The PEI phase’s purpose is to:– Determine the boot mode– Perform low-level initialization of the platform– Discover and initialization main memory– Invoke recovery if desired– Transfer control to DXE or S3 waking vector
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Slide 14
PEI Phase Overall Initialization
• Two PEIMs contain the majority of the platform’s initialization code :Platform\$(SOUTH_PLATFORM_PATH)\Pei\Platform\Stage1
Platform\$(SOUTH_PLATFORM_PATH)\Pei\Platform\Stage2
• The Platform Stage1 PEIM module does the platform initialization according to platform policy or board layout. Stage1 focuses on ICH related platform initialization, such as ICH GPIO initialize, since GPIO usage and initialize value is according to board layout design.
• The Platform Stage2 PEIM module does the platform initialization according to platform policy or board layout. Platform Stage2 focuses on MCH related platform initialization, such as onboard Graphics enable/disable.
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Slide 15
Platform Specifics in Platform.h\Platform\$(PLATFORM_SOUTH_PATH)\Common\Pei\
Platform\Platform.h• Memory DIMM SMBUS address• Firmware Hub GPIO base address and recovery jumper
number• ICH ACPI base address, ICH GPIO base address, SIO
base address, ICH RCBA base address• Early resource address such as AC97 audio memory
mapped IO base address, ICH SMBUS base address, ICH IDE base address.
• ICH GPIO mappings• PEI memory usage• ICH ACPI timer related settings such as resolution,
address, and max value.
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Slide 16
• PEIM for ICH GPIO initialization• Table - mIchGpioInitTable
Register OFFSET
Value
GPIO_USE_SEL 0x1F3DF7C1
GPIO_IO_SEL 0xE6FFFFFF
GPIO_INV 0x0000A000
GPIO_IO_SEL2 0x000000FF
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GPIO Initialization
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Slide 17
Code Example
FILE: Platform\ \$(PLATFORM_SOUTH_PATH)\ Common\Pei\Platform\Stage1\IchInit.c
static const ICH_GPIO_DEV mIchGpioInitTable [] = {// Register OFFSET,Value// 0/1 - Native function/GPIO GPIO_USE_SEL, GPIO_USE_SEL_VAL, GPIO_USE_SEL2, GPIO_USE_SEL2_VAL,// 0/1 - Output/Input GPIO_IO_SEL, GPIO_IO_SEL_VAL, GPIO_IO_SEL2, GPIO_IO_SEL2_VAL,// 0/1 - Active High/Low GPIO_INV, GPIO_INV_VAL};
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Slide 18
GPIO Values
The table allows you to define the register offset and value that is needed to program the GPIO’s. You can set them up for input/output/tri-state and set the high/low values using the following defines:
GPIO_USE_SEL – which GPIO’s to programGPIO_IO_SEL – which directionGPIO_INV – switch High/Low state(setting)These values – GPIO_USE_SEL, GPIO_IO_SEL, and
GPIO_INV are defined in the file:\Platform\$(PLATFORM_SOUTH_PATH)\Common\Pei\Platform\Platform.h
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Slide 19
ICH Initialization• Power-on ICH initialization is performed in PEI to:
– Initialize the system buses (LPC, PCI, SMBUS)– Turn-off the watchdog timer– Program the interrupt pins– Other miscellaneous chipset initialization needed prior to
memory detection• This initialization is performed in the file:Platform\ $(PLATFORM_SOUTH_PATH)\Pei\Platform\Stage1\IchInit.c
• ICH address constants and additional ICH constants are declared in the file:
Platform\ $(PLATFORM_SOUTH_PATH)\Pei\Platform\Platform.h
• Platform component initialization based on user setup preferences is performed later in the DXE ICH initialization.
• Resetting of the ICH is performed in the file:Chipset\IntelIch\IchX\IchInit\Pei\IchReset.c
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Slide 20
Super I/O Initialization
• Power-on Super I/O initialization is performed in the file: – Platform\($(PLATFORM_SOURCE_PATH)\Pei\Platform\Stage1\
SioInit.c
• Devices connected to the LPC bus (e.g. fans, floppy) component initialization is performed later in the DXE Super I/O initialization
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Slide 21
PCI Routing• PCI IRQ routing table is required by
some legacy OSes • DXE driver that perform PCI devices
routing– Platform\$(PLATFORM_SOUTH_PATH)\
Common\Dxe\LegacyBios\platform.c
• Table – PirqTableHead
Pin 1 Pin 2 Pin 3 Pin 4
Bus Dev Reg Map Reg Map Reg Map Reg Map Slot
0x00 0x08 0x60 0xDEB8 0x61 0xDEB8 0x00 0x0000 0x00 0x0000 0x00 0x0000
0x02 0x10 0x61 0xDEB8 0x62 0xDEB8 0x63 0xDEB8 0x60 0xDEB8 0x03 0x0000
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Slide 22
PIRQ Table Code Example in File: Platform\$(PLATFORM_SOUTH_PATH)\Common\Dxe
\LegacyBios\platform.cEFI_LEGACY_PIRQ_TABLE PirqTableHead = { {0x52495024,00,01,0000,00,00,0000,0x8086, 0x122e,00000000,00,00,00,00,00,00,00, 00,00,00,00,00}, { // Memory Controller devices // DEFINE_PCI_ROUTINE (0, 1, PIRQA, PIRQB, PIRQC, PIRQD, 0, 0), //
PEG graphics port DEFINE_PCI_ROUTINE (1, 0, PIRQA, PIRQB, PIRQC, PIRQD, 0x7, 0xFF),
// PEG slot DEFINE_PCI_ROUTINE (0, 2, PIRQA, 0, 0, 0, 0, 0), // On-board
graphics DEFINE_PCI_ROUTINE (0, 3, PIRQA, PIRQB, PIRQC, 0, 0, 0), //
HECI
. . .
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Slide 23
PCI IRQ routing in the ACPI Tables Example in File:
Platform\$(PLATFORM_SOUTH_PATH)\Common\Dxe\AcpiTables\asl\OnBoardPrt.asi
It contains the internal PCI devices and onboard PCI devices IRQ routing information. Generally, all internal PCI devices with ICH or MCH should be listed. For example, USB, IDE, SATA and AC97 controllers in ICH and graphics controller in MCH
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Slide 24
Flash ROM • Implement EFI_FIRMWARE_VOLUME_
BLOCK_PROTOCOL
• Enables Variable Write Services
• Initializes platform specific flash device– Platform\Generic\RuntimeDxe\FvbServices\<Platform>– FWBlockService.c
• Possible functions for FWH or SPI access– EnableFvbWrites ( )– EnablePlatformFvb ( )– PlatformGetFvbWriteBase ( )– SetPlatformFvbLock ( )
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Slide 25
SMBusMinimal porting job to run EFI Shell
SM BusSM Bus
• PEIM for ICH SMBus initialize– Chipset\IntelIch\IchX\Smbus IchSmbus.c
• Functions to provide a standard way to access SMBus– SmbusExecute ( )– SmbusIoRead ( )– SmbusIoWrite ( )
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Slide 26
DXE IPL
• Shadow DXE IPL in permanent memory– To allow sharing of decompression algorithm with
DXE
• Allocate 128KB stack for DXE• Create HOBs
– Decompression protocol passed as HOB
• Firmware Volumes– Passed in HOB
• Handle S3 transition • Switch Stacks to call DXE Main
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Slide 27
Initialize System Memory• PEIM that performs system memory initialization
– Chipset\<Chipset>
• Memory detection – PEI_DUAL_CHANNEL_DDR_MEMORY_CONTROLLER_PPI
• Reset• RowInfo• GetMemoryMap• DetectMemory• ConfigureMemory
• Memory clock control– PEI_DUAL_CHANNEL_DDR_CLOCK_GENERATOR_PPI
• Capabilities• GetFrequency• SetFrequency
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SM BusSM Bus
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Slide 28
Integrating Memory Init Code
• MRC directory Chipset\<Chipset>\MemoryInit • The file MemoryInit.Inf describes the Memory Reference
code contained within its description (.dsc) file. • After calling the entry to this memory init routine and
successfully exiting, the memory should be ready to use. It builds HOBs to describe the memory address space and their attributes.
• Some of the HOB information that is produced by the MRC:
• S3 Memory• SMRAM Descriptor HOB• Memory Descriptor HOB• T-size configuration setup option (variable)
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Slide 29
PEI Modules
CPU PEIM
Stall PEIM
SMBus PEIM
Status Code PEIM
Motherboard PEIM
DXE IPL PEIM
Memory Controller PEIMs
Platform
South Bridge
Platform
Platform
Generic
North Bridge
PCAT
PCATPCI Configuration PEIM
Init and CPU I/O
Uses 8254 Timer
SMBus Transactions
Debug Messages
FLASH Map, Boot Policy
Starts DXE Foundation
Read SPD, Init Memory
Uses I/O 0xCF8, 0xCFC
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SM BusSM Bus
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Slide 30
PPI Example
typedefEFI_STATUS(EFIAPI *PEI_SMBUS_PPI_EXECUTE_OPERATION) ( IN EFI_PEI_SERVICE **PeiServices, IN struct EFI_PEI_SMBUS_PPI *This, IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, IN EFI_SMBUS_DEVICE_COMMAND Command, IN EFI_SMBUS_OPERATION Operation, IN BOOLEAN PecCheck, IN OUT UINTN *Length, IN OUT VOID *Buffer );
typedef struct { PEI_SMBUS_PPI_EXECUTE_OPERATION Execute; PEI_SMBUS_PPI_ARP_DEVICE ArpDevice;} EFI_PEI_SMBUS_PPI;
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Slide 31
#define SMBUS_R_HD0 0xEFA5#define SMBUS_R_HBD 0xEFA7
EFI_PEI_SERVICES *PeiServices;SMBUS_PRIVATE_DATA *Private;UINT8 Index, BlockCount *Length;UINT8 *Buffer;
BlockCount = Private->CpuIo.IoRead8 ( *PeiServices,Private->CpuIo,SMBUS_R_HD0);if (*Length < BlockCount) { return EFI_BUFFER_TOO_SMALL;} else { for (Index = 0; Index < BlockCount; Index++) { Buffer[Index] = Private->CpuIo.IoRead8 ( *PeiServices,Private->CpuIo,SMBUS_R_HBD); }}
PEIM Pseudo Code
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Slide 32
What Are Architectural Protocols
• Typically functions that isolate platform specific hardware (e.g. real-time clock)
• Provide support for boot services and runtime services
• Low level protocols that support DXE APIs (e.g. Boot and Runtime services)
• Directly called by DXE core
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Slide 33
DXE Architectural Protocols
Monotonic Counter
Runtime
Watchdog
Generic
Generic
Generic
Uses Variable Services
Platform Independent
Uses Timer-based Events
Timer
Metronome
CPU
PCAT
PCAT
Platform
Uses 8254 Timer
Uses 8254 Timer
Processor DXE Driver
Real Time Clock
Variable
Reset
PCAT
Platform
PCAT
I/O 0x70-0x71
Depends on FLASH Map
I/O 0xCF9
Status Code
BDS
Security
Platform
Platform
Platform
Debug Messages
Platform Policy and TSL phase
Platform Specific Authentication
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Slide 34
DXE Drivers Consuming Architectural Protocols
• Host bridge driver– Chipset\PcatCompatible\SimplePciHostBridge\Dxe
• ICH initialize driver– Chipset\IntelIch\IchX\IchxInit\Dxe
• IDE controller driver– Chipset\IntelIch\IchX\IdeController\Dxe
• SMBus DXE driver– Chipset\IntelIch\IchX\Smbus\Dxe
• Super I/O– Chipset\<SuperIO Vendor>\Dxe
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Slide 35
NT Emulation Timer Arch Protocol
EFI_STATUSTimerDriverSetTimerPeriod ( IN EFI_TIMER_ARCH_PROTOCOL *This, IN UINT64 TimerPeriod ){. . . gWinNt->EnterCriticalSection (&mNtCriticalSection); mTimerPeriod = TimerPeriod; mCancelTimerThread = FALSE; gWinNt->LeaveCriticalSection (&mNtCriticalSection); mNtLastTick = gWinNt->GetTickCount (); mNtTimerThreadHandle = gWinNt->CreateThread ( NULL, 0, NtTimerThread, &mTimer, 0, &NtThreadId);. . .}
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Slide 36
Itanium Timer Arch ProtocolEFI_STATUSTimerDriverSetTimerPeriod ( IN EFI_TIMER_ARCH_PROTOCOL *This, IN UINT64 TimerPeriod ){. . . mTimerCount = (mCpuFrequency * TimerPeriod) / NUMBER_OF_100NS_IN_A_SECOND; SetupItm (mTimerCount);// mov loc2 = ar.itc;;// add loc2 = loc2, in0;;// mov cr.itm = loc2// srlz.d;;
ItcInterruptControl (TRUE, TIMER_VECTOR_NUMBER);// mov loc2 = in1// mov loc3 = 0x1// mov loc4 = pr// cmp.eq p6,p7 = in0,r0;;//// (p7) dep loc2 = r0,loc2,16,1;; // Clear mask to enable intr// (p6) dep loc2 = loc3,loc2,16,1;; // Set mask to disable intr//// mov cr.itv = loc2;;// srlz.d;;// mov pr = loc4,0x1ffff
. . .}
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Slide 37
XScale Timer Arch ProtocolEFI_STATUSTimerDriverSetTimerPeriod ( IN EFI_TIMER_ARCH_PROTOCOL *This, IN UINT64 TimerPeriod ){ UINT64 Count; UINT32 Data;. . . Count = DivU64x32 (MultU64x32 (TimerPeriod, OST_CRYSTAL_FREQ) + 5000000, 10000000, NULL); mCpuIo->Mem.Read (mCpuIo,EfiWidthUint32,OSCR_BASE_PHYSICAL,1,&Data); Data += (UINT32)Count; mCpuIo->Mem.Write (mCpuIo,EfiWidthUint32,OSMR0_BASE_PHYSICAL,1,&Data); mCpuIo->Mem.Read (mCpuIo,EfiWidthUint32,OIER_BASE_PHYSICAL,1,&Data); Data |= (UINT32)1; mCpuIo->Mem.Write (mCpuIo,EfiWidthUint32,OIER_BASE_PHYSICAL,1,&Data); mCpuIo->Mem.Read (mCpuIo,EfiWidthUint32,ICMR_PHYSICAL,1,&Data); Data |= (UINT32)(1 << SA_OST0_IRQ_No); mCpuIo->Mem.Write (mCpuIo,EfiWidthUint32,ICMR_PHYSICAL,1,&Data);. . .}
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Slide 38
8254 Based Timer Arch ProtocolEFI_STATUSTimerDriverSetTimerPeriod ( IN EFI_TIMER_ARCH_PROTOCOL *This, IN UINT64 TimerPeriod ){ UINT64 Count; UINT8 Data;. . . Count = DivU64x32 (MultU64x32(119318, (UINTN) TimerPeriod) + 500000, 1000000, NULL); Data = 0x36; mCpuIo->Io.Write(mCpuIo,EfiCpuIoWidthUint8,TIMER_CONTROL_PORT, 1, &Data); mCpuIo->Io.Write(mCpuIo,EfiCpuIoWidthFifoUint8,TIMER0_COUNT_PORT,2,&Count); mLegacy8259->EnableIrq (mLegacy8259, Efi8259Irq0, FALSE);. . .}
Different ImplementationsDifferent ImplementationsSame Protocol InterfaceSame Protocol Interface
Different ImplementationsDifferent ImplementationsSame Protocol InterfaceSame Protocol Interface
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Slide 39
Serial Terminal Console Services
PCI Root Bridge I/O Protocol
PCI Host Bridge Resource Allocation Protocol
PCI I/O Protocol
ISA I/O Protocol
Serial I/O Protocol
Simple Input Protocol
Simple TextOutput Protocol
BDS / EFI Shell
Simple Input Protocol
Simple TextOutput Protocol
ISA ACPI Protocol
Physical Console
VirtualConsole
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Super I/OSuper I/O
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Slide 40
Serial Terminal Console Drivers
Console Splitter
Console Platform
BDS / EFI Shell
Generic
Platform
Generic
Platform Specific Policy
ISA Bus
PCI Bus
Terminal
Generic
Generic
Generic
PCI Host Bridge
PCI Root Bridge
North Bridge
North Bridge
Work with Chipset Vendor
Work with Chipset Vendor
ISA Serial
ISA ACPI
PCAT
Super I/O Work with Super I/O Vendor
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Super I/OSuper I/O
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Slide 41
DXE Driver for Console Services
• Console Splitter Driver– Edk\Sample\Universal\Console\ConSplitter\Dxe
• Graphics Console Driver – Edk\Sample\Universal\Console\GraphicsConsole\Dxe
• Terminal Driver– Edk\Sample\Universal\Console\Terminal\Dxe
• UGA Driver (optional)
– Chipset\<Vendor>\Uga\Dxe
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Slide 42
Porting SummaryDo Minimum to Run EFI Shell
Console Platform Platform
PCI Host Bridge
PCI Root Bridge
North Bridge
North Bridge
ISA ACPI Super I/O
Variable
Status Code
Security
Platform
Platform
SMBUS
Status Code
Motherboard
Memory Controller
South Bridge
Platform
Platform
North Bridge
DXE
DXE
DXE
DXE
DXE
DXE
DXE
PEI
PEI
PEI
PEI
Platform
Minimal porting job to run EFI Shell
SM BusSM Bus
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Slide 43
Further Information
• Documents Directory on CD – Framework Mini PortingGuide– FrameworkTechPortingRef– FrameworkPortingList
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Slide 44
Q & A
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Slide 45
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Slide 46
Back up
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Slide 47
2009 release Centrino Mobile Technology platform
• Porting example• New form footprint no longer North / South Bridge
template• Core / Uncore part of the Processor• Platform Control Hub (PCH) integrated successor to
MCH + ICH instead of South Bridge• Power management considerations on mobile• Silicon released as Separate UEFI reference modules
– PCH Reference code – Core / Uncore CPU Reference code– ACPI – Power Management– Memory Reference code
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Slide 48
Platform\ Platform
\ IntelDpg – Bearlake Pei – Dxe - Platform\ IntelEsg – StarLake Pei – Dxe - Platform\ IntelMpg – MobilePlatform
\ AcpiTables\ Dsdt\ SsdtPtid\ VaAcpiTables
\ Build\ Include\ LegacyBiosPlatform\ Library\ PciPlatform\ PlatformSetup\ SmbiosMisc
ACPI Module Package
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Slide 49
Platform Control Hub - Chipset\ Chipset
\ IntelIch\ IntelPch – Mobile Chipset (IbexPeak)
\ ActiveBios\ Include\ IoTrap\ LegacyInterrup\ Library\ PchInit\ PchSmiDispatcher\ PciExpress\ Ppi\ Protocol\ RaidRom\ Reset
\ S3Support\ SampleCOde\ SataController\ SerialGpio\ SmartTimer\ SmBus\ SmmControl\ Spi\ Uhci\ Veci
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Slide 50
Core/Uncore IIO Elements- \ CPU
\ UncoreCommon\ AcpiTables\ Guid\ Include\ LegacyRegion\ Library\ PciHostBridge\ SmbiosMemory\ SmmAccess
\ FieldUncore\ Iio (Integrated I/O )
\ IioInit\ IioInitLib\ Include\ Protocol
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Slide 51
Power Management- \ Platform
\ IntelDpg – Bearlake Pei – Dxe - Platform\ IntelEsg – StarLake Pei – Dxe - Platform\ IntelMpg – MobilePlatform
\ . . .\ Common
\ PowerManagement\ AcpiTables\ Guid\ Include\ Library\ Protocol\ Smm
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Slide 52
Memory Init \ CPU
\ UncoreCommon\ . . .\ FieldUncore
\ Iio (Integrated I/O )\ . . .
\ CsiMemoryInit\ CSI\ PPI\ PEI\ Memory
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Slide 53
Others \ Microcode updates\ CSM
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Slide 54
Agenda
• Create a New Platform Build • Minimal porting job to run EFI Shell• Platform specific porting features
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Slide 55
Add Platform Features - IDE
PCI Root Bridge I/O Protocol
PCI Host Bridge Resource Allocation Protocol
PCI I/O Protocol
Block I/O Protocol
BDS / EFI Shell
IDE Controller Init
Block I/O Protocol
Disk I/O Protocol Disk I/O Protocol
Block I/O Protocol Block I/O Protocol
Disk I/O Protocol Disk I/O Protocol
File Sys Protocol File Sys Protocol
Physical Disk
Partition
Platform specific porting features
SM BusSM Bus
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Slide 56
FAT
BDS / EFI Shell
Generic
Generic
IDE Bus
PCI Bus
Partition
PCAT
Generic
Generic
PCI Host Bridge
PCI Root Bridge
North Bridge
North Bridge
Disk I/O
IDE Controller Init
Generic
South Bridge IDE Channel Attributes
Add Platform Features - IDE
Platform specific porting features
SM BusSM Bus
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Slide 57
Add Platform Features
• Integrated USB– Work with Chipset Vendor– USB Host Controller Protocol
• Integrated Video– Work with Chipset Vendor– UGA Draw and UGA I/O Protocol
• Integrated LAN– Work with Chipset Vendor– UNDI Driver
• AGP and PCI Slots– Work with IHVs to Provide EFI Drivers
Platform specific porting features
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• Implement Platform and Chipset Specific Protocols– Legacy BIOS Platform– Legacy Region– Legacy Interrupt
• Enables POST of Legacy Option ROMs– Video Controllers– Disk Controllers– Network Interface Controllers
• Enables Legacy OS Boot– Linux, Windows XP, Windows 2000
Compatibility Support ModulePlatform specific porting features
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Slide 59
CSM drivers
• LegacyBios driver– Csm\LegacyBios\Dxe
• BiosThunk drivers – BIOS drivers for Legacy OS boot– Csm\BiosThunk\VgaMiniPort\Dxe– Csm\BiosThunk\Keyboard\Dxe– Csm\BiosThunk\Snp16\Dxe– Csm\BiosThunk\BlockIo\Dxe
Platform specific porting features
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Slide 60
CSM Drivers Cont’d
• Legacy Interrupt (PIRQ registers)– Chipset\IntelIch\LegacyInterrupt\Dxe\LegacyInterrupt.c
• Legacy Region (shadow regions)– Chipset\<Vendor>\LegacyRegion\Dxe\LegacyRegion.c
• Legacy BIOS Platform– Platform\<Vendor>\<Platform>\Dxe\
LegacyBiosPlatform\LegacyBiosPlatform.c
– Functions to prepare different tables (Option ROM services, etc.)
Platform specific porting features
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Slide 61
Add SMM support to DXE
• Base Protocol– Responsible for Processor state (in SMM)
initialization and allocates SMM Memory– Cpu\<Processor>Base\Smm\SmmBase.inf
• Access Protocol– Controls the visibility of the SMRAM on the platform– Chipset\<Vendor>\SmmAccess\Dxe\SmmAccess.inf
• Control Protocol– Initiate SMI/PMI activations– Chipset\IntelIch\IchX\SmmControl\Dxe\
SmmControl.inf
Platform specific porting features
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Slide 62
ACPI Support
• Provides ACPI support for a platform– Builds FADT table from built AML tables– Allows platform customization (APIC, GV3, OEMID)– Updates EFI System Table with ACPI table pointers
• Composed of two drivers:– ACPI Support Driver (generic)– ACPI Platform Driver (platform specific)
• Platform Driver runs during DXE phase (before BDS)• ScriptSave driver
– DXE drivers call ScriptSave protocol to save the chipset and CPU configuration at normal boot path
– The boot script engine in PEIM restores the chipset and CPU configuration done in previous DXE in S3 resume boot path
– Universal\Acpi\BootScriptSave\Dxe\ScriptSave.inf
Platform specific porting features
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Slide 63
Add ACPI support to DXE
• ACPI tables– Platform\<Vendor>\Dxe\AcpiTables
• ASL code– Platform\<Vendor>\Dxe\AcpiTables\Asl\*.asi
• Update Platform Driver for platform specifics– Platform\<Vendor>\<Platform>\Dxe\AcpiPlatform\
AcpiPlatform.c
Platform specific porting features
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Slide 64
EFI S3 path
SEC
PEI DXE BDS OS BootNormal Boot
Non-volatileStorage (NVS)
Resume ScriptTable in ACPI
NVS
SEC
S3 aware PEIMs restore
PEI Phase configuration
Boot Script PEIM restores
DXE phase configuration
Retrieve Execute
S3 Resume S3 Waking Vector
Save
Platform specific porting features
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Slide 65
Add S3 Support to DXE
• Architectural Protocol– Universal\Acpi\AcpiS3Save\Dxe– Universal\Acpi\S3Resume\Pei
• Platform dependent Protocol– Platform\<Vendor>\Smm\
IchS3Save
Platform specific porting features
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Slide 66
Framework Designed to be PortedFramework Designed to be PortedFramework Designed to be PortedFramework Designed to be Ported
BDS Driver
• BDS driver– Edk\Sample\Platform\Generic\Dxe\PlatformBds
• Connecting Consoles/Changing Platform Policy– Platform\<Vendor>\<Platform>\PlatformBds\Dxe\
BdsPlatform.c
• Language– Platform\Generic\Dxe\Bds\*.uni
• Memory Test
Platform specific porting features
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Slide 67
Summary
• Minimal porting effort for running EFI Shell.• Incrementally add platform specific features.• Modularity of drivers allows easy integration.• Legacy BIOS experience is still useful with the
Framework. • Framework knowledge easily transfers to
other architectures.
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Slide 68
Further Information
• Documents Directory on CD – Framework Mini PortingGuide– FrameworkTechPortingRef– FrameworkPortingList