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100 MHz to 4000 MHz RF/IF Digitally Controlled VGA
Data Sheet ADL5240
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices . Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Operating frequency from 100 MHz to 4000 MHz Digitally controlled VGA with serial and parallel interfaces 6-bit, 0.5 dB digital step attenuator 31.5 dB gain control range with ±0.25 dB step accuracy Gain block amplifier specifications
Gain: 19.7 dB at 2.14 GHz OIP3: 41.0 dBm at 2.14 GHz P1dB: 19.5 dBm at 2.14 GHz Noise figure: 2.9 dB at 2.14 GHz
Gain block or digital step attenuator can be first Single supply operation from 4.75 V to 5.25 V Low quiescent current of 93 mA Thermally efficient, 5 mm × 5 mm, 32-lead LFCSP The companion ADL5243 integrates a ¼ W driver amplifier to
the output of the gain block and DSA
APPLICATIONS
Wireless infrastructure Automated test equipment RF/IF gain control
GENERAL DESCRIPTION The ADL5240 is a high performance, digitally controlled variable gain amplifier (VGA) operating from 100 MHz to 4000 MHz. The VGA integrates a high performance, 20 dB gain, internally matched amplifier (AMP) with a 6-bit digital step attenuator (DSA) that has a gain control range of 31.5 dB in 0.5 dB steps with ±0.25 dB step accuracy. The attenuation of the DSA can be controlled using a serial or parallel interface.
Both the gain block and DSA are internally matched to 50 Ω at their inputs and outputs and are separately biased. The separate bias allows all or part of the ADL5240 to be used, which facilitates easy reuse throughout a design. The pinout of the ADL5240 also enables either the gain block or DSA to be first, giving the VGA maximum flexibility in a signal chain.
The ADL5240 consumes just 93 mA and operates from a single supply ranging from 4.75 V to 5.25 V. The VGA is packaged in a thermally efficient, 5 mm × 5 mm, 32-lead LFCSP and is fully specified for operation from −40°C to +85°C. A fully populated evaluation board is available.
FUNCTIONAL BLOCK DIAGRAM
ADL5240
AMP
9
NC
10
AM
POU
T/VC
C
11
NC
12
NC
13
NC
14
NC
15
AM
PIN
16
NC
SERIAL/PARALLEL INTERFACE24 VDD
23 NC
22 NC
21 DSAOUT
20 NC
19 NC
18 NC
17 NC
0.5dB 1dB 2dB 4dB 8dB 16dB
32
SEL
31
D0/
CLK
30
D1/
DA
TA
29
D2/
LE
28
D3
27
D4
26
D5
25
D6
1VDD
2NC
3NC
4DSAIN
5NC
6NC
7NC
8NC
0943
0-00
1
Figure 1.
ADL5240 Data Sheet
Rev. A | Page 2 of 28
TABLE OF CONTENTS Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 10
Applications Information .............................................................. 16
Basic Layout Connections ......................................................... 16
SPI Timing................................................................................... 18
Loop Performance ...................................................................... 20
Amplifier Drive Level for Optimum ACLR ............................ 22
Thermal Considerations ............................................................ 22
Evaluation Board ............................................................................ 23
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY 6/13—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................. 4 Changes to Table 3 ............................................................................. 9 Changes to Figure 3 ......................................................................... 11 Changes to Figure 16 ....................................................................... 12 Added Figure 29, Renumbered Sequentially ............................... 14 Changes to Table 5, Figure 35, and Figure 36 .............................. 18 Added Amplifier Drive Level for Optimum ACLR Section and Figure 39 .................................................................................... 22 Changes to Evaluation Board Section ........................................... 23 Changes to Figure 41 and Table 8 .................................................. 24 Added Figure 42 ............................................................................... 25 Changes to Figure 43 and Figure 44 .............................................. 26 Added Figure 45 ............................................................................... 27
7/11—Revision 0: Initial Version
Data Sheet ADL5240
Rev. A | Page 3 of 28
SPECIFICATIONS VDD = 5 V, VCC = 5 V, TA = 25oC
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
OVERALL FUNCTION Frequency Range 100 4000 MHz
AMPLIFIER FREQUENCY = 150 MHz Using the AMPIN and AMPOUT pins Gain 17.6 dB
vs. Frequency ±50 MHz ±1.0 dB vs. Temperature −40°C ≤ TA ≤ +85°C ±0.04 dB
vs. Supply 4.75 V to 5.25 V ±0.04 dB Input Return Loss S11 −10.4 dB Output Return Loss S22 −7.7 dB Output 1 dB Compression Point 18.3 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone 30.0 dBm Noise Figure 2.8 dB
AMPLIFIER FREQUENCY = 450 MHz Using the AMPIN and AMPOUT pins Gain 20.3 dB
vs. Frequency ±50 MHz ±0.11 dB vs. Temperature −40°C ≤ TA ≤ +85°C ±0.36 dB
vs. Supply 4.75 V to 5.25 V ±0.01 dB Input Return Loss S11 −18.3 dB Output Return Loss S22 −15.7 dB Output 1 dB Compression Point 20.2 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone 39.0 dBm Noise Figure 2.9 dB
AMPLIFIER FREQUENCY = 748 MHz Using the AMPIN and AMPOUT pins Gain 20.6 dB
vs. Frequency ±50 MHz ±0.01 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.31 dB vs. Supply 4.75 V to 5.25 V ±0.01 dB
Input Return Loss S11 −25.7 dB Output Return Loss S22 −23.7 dB Output 1 dB Compression Point 20.2 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone 40.0 dBm Noise Figure 2.7 dB
AMPLIFIER FREQUENCY = 943 MHz Using the AMPIN and AMPOUT pins Gain 19.0 20.5 22.0 dB
vs. Frequency ±18 MHz ±0.01 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.27 dB vs. Supply 4.75 V to 5.25 V ±0.01 dB
Input Return Loss S11 −30.3 dB Output Return Loss S22 −24.8 dB
Output 1 dB Compression Point 18.5 20.1 dBm Output Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone 40.0 dBm Noise Figure 2.7 dB
ADL5240 Data Sheet
Rev. A | Page 4 of 28
Parameter Test Conditions/Comments Min Typ Max Unit AMPLIFIER FREQUENCY = 1960 MHz Using the AMPIN and AMPOUT pins
Gain 19.8 dB
vs. Frequency ±30 MHz ±0.03 dB vs. Temperature −40°C ≤ TA ≤ +85°C ±0.26 dB vs. Supply 4.75 V to 5.25 V ±0.03 dB
Input Return Loss S11 −11.9 dB Output Return Loss S22 −12.6 dB
Output 1 dB Compression Point 19.8 dBm Output Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone 40.0 dBm Noise Figure 2.9 dB
AMPLIFIER FREQUENCY = 2140 MHz Using the AMPIN and AMPOUT pins Gain 18.0 19.7 22.0 dB
vs. Frequency ±30 MHz ±0.02 dB vs. Temperature −40°C ≤ TA ≤ +85°C ±0.25 dB vs. Supply 4.75 V to 5.25 V ±0.04 dB
Input Return Loss S11 −11.0 dB
Output Return Loss S22 −12.0 dB Output 1 dB Compression Point 17.5 19.5 dBm Output Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone 41.0 dBm Noise Figure 2.9 dB
AMPLIFIER FREQUENCY = 2630 MHz Using the AMPIN and AMPOUT pins Gain 18.0 19.6 22.0 dB
vs. Frequency ±60 MHz ±0.01 dB vs. Temperature −40°C ≤ TA ≤ +85°C ±0.22 dB vs. Supply 4.75 V to 5.25 V ±0.04 dB
Input Return Loss S11 −11.0 dB
Output Return Loss S22 −13.3 dB Output 1 dB Compression Point 18.0 19.9 dBm Output Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone 41.0 dBm Noise Figure 2.9 dB
AMPLIFIER FREQUENCY = 3600 MHz Using the AMPIN and AMPOUT pins Gain 19.6 dB
vs. Frequency ±100 MHz ±0.03 dB vs. Temperature −40°C ≤ TA ≤ +85°C ±0.05 dB vs. Supply 4.75 V to 5.25 V ±0.10 dB
Input Return Loss S11 −15.1 dB
Output Return Loss S22 −12.2 dB Output 1 dB Compression Point 18.8 dBm Output Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone 37.0 dBm Noise Figure 3.1 dB
DSA FREQUENCY = 150 MHz Using the DSAIN and DSAOUT pins Insertion Loss Minimum attenuation −1.5 dB
vs. Frequency ±50 MHz ±0.12 dB vs. Temperature −40°C ≤ TA ≤ +85°C ±0.09 dB
Attenuation Range 28.8 dB Attenuation Step Error All attenuation states ±0.18 dB
Attenuation Absolute Error All attenuation states ±1.35 dB Input Return Loss Minimum attenuation −13.3 dB Output Return Loss Minimum attenuation −13.4 dB Input Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation 47.9 dBm
Data Sheet ADL5240
Rev. A | Page 5 of 28
Parameter Test Conditions/Comments Min Typ Max Unit DSA FREQUENCY = 450 MHz Using the DSAIN and DSAOUT pins
Insertion Loss Minimum attenuation −1.5 dB
vs. Frequency ±50 MHz ±0.02 dB vs. Temperature −40°C ≤ TA ≤ +85°C ±0.10 dB
Attenuation Range 30.7 dB Attenuation Step Error All attenuation states ±0.14 dB Attenuation Absolute Error All attenuation states ±0.42 dB
Input Return Loss Minimum attenuation −17.6 dB Output Return Loss Minimum attenuation −17.6 dB Input Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation 45.0 dBm
DSA FREQUENCY = 748 MHz Using the DSAIN and DSAOUT pins Insertion Loss Minimum attenuation −1.6 dB
vs. Frequency ±50 MHz ±0.02 dB vs. Temperature −40°C ≤ TA ≤ +85°C ±0.11 dB
Attenuation Range 30.9 dB Attenuation Step Error All attenuation states ±0.15 dB Attenuation Absolute Error All attenuation states ±0.32 dB Input Return Loss Minimum attenuation −17.4 dB
Output Return Loss Minimum attenuation −17.4 dB Input Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation 43.5 dBm
DSA FREQUENCY = 943 MHz Using the DSAIN and DSAOUT pins Insertion Loss Minimum attenuation −1.6 dB
vs. Frequency ±18 MHz ±0.01 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.12 dB Attenuation Range 30.9 dB Attenuation Step Error All attenuation states ±0.13 dB Attenuation Absolute Error All attenuation states ±0.30 dB Input Return Loss Minimum attenuation −16.6 dB
Output Return Loss Minimum attenuation −16.5 dB Input 1 dB Compression Point Minimum attenuation 30.5 dBm Input Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation 50.9 dBm
DSA FREQUENCY = 1960 MHz Using the DSAIN and DSAOUT pins Insertion Loss Minimum attenuation −2.4 dB
vs. Frequency ±30 MHz ±0.02 dB vs. Temperature −40°C ≤ TA ≤ +85°C ±0.16 dB
Attenuation Range 31.0 dB Attenuation Step Error All attenuation states ±0.15 dB
Attenuation Absolute Error All attenuation states ±0.29 dB Input Return Loss Minimum attenuation −12.0 dB Output Return Loss Minimum attenuation −11.5 dB Input 1 dB Compression Point Minimum attenuation 31.5 dBm Input Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation 49.5 dBm
DSA FREQUENCY = 2140 MHz Using the DSAIN and DSAOUT pins
Insertion Loss Minimum attenuation −2.5 dB vs. Frequency ±30 MHz ±0.02 dB vs. Temperature −40°C ≤ TA ≤ +85°C ±0.17 dB
Attenuation Range 31.0 dB Attenuation Step Error All attenuation states ±0.12 dB
Attenuation Absolute Error All attenuation states ±0.26 dB Input Return Loss Minimum attenuation −11.9 dB Output Return Loss Minimum attenuation −11.2 dB Input 1 dB Compression Point Minimum attenuation 31.5 dBm Input Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation 49.2 dBm
ADL5240 Data Sheet
Rev. A | Page 6 of 28
Parameter Test Conditions/Comments Min Typ Max Unit DSA FREQUENCY = 2630 MHz Using the DSAIN and DSAOUT pins
Insertion Loss Minimum attenuation −2.6 dB
vs. Frequency ±60 MHz ±0.04 dB vs. Temperature −40°C ≤ TA ≤ +85°C ±0.19 dB
Attenuation Range 31.2 dB Attenuation Step Error All attenuation states ±0.16 dB Attenuation Absolute Error All attenuation states ±0.19 dB
Input Return Loss Minimum attenuation −13.1 dB Output Return Loss Minimum attenuation −12.0 dB Input 1 dB Compression Point Minimum attenuation 31.5 dBm Input Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation 47.6 dBm
DSA FREQUENCY = 3600 MHz Using the DSAIN and DSAOUT pins
Insertion Loss Minimum attenuation −2.8 dB vs. Frequency ±100 MHz ±0.03 dB vs. Temperature −40°C ≤ TA ≤ +85°C ±0.21 dB
Attenuation Range 32.1 dB
Attenuation Step Error All attenuation states ±0.37 dB Attenuation Absolute Error All attenuation states ±0.31 dB Input Return Loss Minimum attenuation −20.2 dB Output Return Loss Minimum attenuation −18.2 dB Input 1 dB Compression Point Minimum attenuation 31.0 dBm
Input Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation 48.5 dBm
DIGITAL STEP ATTENUATOR GAIN SETTLING Minimum Attenuation to Maximum Attenuation 36 ns Maximum Attenuation to Minimum Attenuation 36 ns
AMP-DSA LOOP FREQUENCY = 943 MHz Using the AMPIN and DSAOUT pins, DSA at minimum attenuation
Gain 18.9 dB vs. Frequency ±18 MHz ±0.01 dB
Gain Range Between maximum and minimum attenuation states 30.8 dB
Input Return Loss S11 −20.5 dB Output Return Loss S22 −19.7 dB Output 1 dB Compression Point 18.6 dBm Output Third-Order Intercept ∆f = 1 MHz, POUT = 1 dBm/tone 36.0 dBm Noise Figure 2.7 dB
AMP-DSA LOOP FREQUENCY = 2140 MHz Using the AMPIN and DSAOUT pins, DSA at minimum attenuation
Gain 18.2 dB vs. Frequency ±30 MHz ±0.01 dB
Gain Range Between maximum and minimum attenuation states 31.3 dB Input Return Loss S11 −14.9 dB Output Return Loss S22 −16.4 dB Output 1 dB Compression Point 17.9 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 1 dBm/tone 37.5 dBm Noise Figure 3.0 dB
Data Sheet ADL5240
Rev. A | Page 7 of 28
Parameter Test Conditions/Comments Min Typ Max Unit AMP-DSA LOOP FREQUENCY = 2630 MHz Using the AMPIN and DSAOUT pins, DSA at
minimum attenuation
Gain 17.7 dB vs. Frequency ±60 MHz ±0.11 dB
Gain Range 31.5 dB
Input Return Loss S11 −15.2 dB Output Return Loss S22 −9.6 dB Output 1 dB Compression Point 16.9 dBm Output Third-Order Intercept ∆f = 1 MHz, POUT = 1 dBm/tone 33.7 dBm
Noise Figure 3.0 dB DSA-AMP LOOP FREQUENCY = 943 MHz Using the DSAIN and AMPOUT pins, DSA at
minimum attenuation
Gain 18.9 dB vs. Frequency ±18 MHz ±0.01 dB
Gain Range Between maximum and minimum attenuation states 30.8 dB Input Return Loss S11 −17.2 dB Output Return Loss S22 −23.7 dB Output 1 dB Compression Point 20.2 dBm
Output Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone 40.0 dBm Noise Figure 4.4 dB
DSA-AMP LOOP Frequency = 2140 MHz Using the DSAIN and AMPOUT pins, DSA at minimum attenuation
Gain 18.0 dB vs. Frequency ±30 MHz ±0.01 dB
Gain Range Between maximum and minimum attenuation states 31.1 dB Input Return Loss S11 −13.7 dB
Output Return Loss S22 −10.0 dB Output 1 dB Compression Point 19.7 dBm Output Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone 37.5 dBm Noise Figure 4.9 dB
DSA-AMP LOOP Frequency = 2630 MHz Using the DSAIN and AMPOUT pins, DSA at minimum attenuation
Gain 18.2 dB vs. Frequency ±60 MHz ±0.01 dB
Gain Range Between maximum and minimum attenuation states 31.7 dB
Input Return Loss S11 −15.7 dB Output Return Loss S22 −16.9 dB Output 1 dB Compression Point 19.8 dBm Output Third-Order Intercept ∆f = 1 MHz, POUT = 4 dBm/tone 40.8 dBm
Noise Figure 5.2 dB
LOGIC INPUTS CLK, DATA, LE, SEL, D0~D6 Input High Voltage, VINH 2.5 V Input Low Voltage, VINL 0.8 V Input Current, IINH/IINL 0.1 µA
Input Capacitance, CIN 1.5 pF POWER SUPPLIES Using the VDD and VCC pins
Voltage 4.75 5.0 5.25 V Supply Current
Amplifier 93 120 mA Digital Step Attenuator 0.5 mA
ADL5240 Data Sheet
Rev. A | Page 8 of 28
ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage (VDD, VCC) 6.5 V Input Power
AMPIN 16 dBm DSAIN 30 dBm
Internal Power Dissipation 0.5 W θJA (Exposed Pad Soldered Down) 36.8°C/W θJC (Exposed Pad is the Contact) 6.9°C/W Maximum Junction Temperature 150°C
Lead Temperature (Soldering, 60 sec) 240°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Data Sheet ADL5240
Rev. A | Page 9 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
PIN 1INDICATOR
1VDD2NC3NC4DSAIN5NC6NC7NC8NC
24 VDD23 NC22 NC21 DSAOUT20 NC19 NC18 NC17 NC
9N
C10
AM
POU
T/VC
C11
NC
12N
C13
NC
14N
C15
AM
PIN
16N
C
32SE
L31
D0/
CLK
30D
1/D
ATA
29D
2/LE
28D
327
D4
26D
525
D6
TOP VIEW(Not to Scale)
ADL5240
0943
0-00
2
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1, 24 VDD Supply Voltage for DSA. Connect this pin to a 5 V supply. 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 14, 16, 17, 18, 19, 20, 22, 23
NC No Connect. Do not connect to this pin.
4 DSAIN RF Input to DSA.
10 AMPOUT/VCC RF Output from Amplifier/Supply Voltage for Amplifier. A bias to the amplifier is provided through a choke inductor connected to this pin.
15 AMPIN RF Input to Amplifier.
21 DSAOUT RF Output from DSA. 25 D6 Data Bit in Parallel Mode (LSB). Connect this pin to the supply in serial mode. 26 D5 Data Bit in Parallel Mode. Connect this pin to ground or leave open in serial mode. 27 D4 Data Bit in Parallel Mode. Connect this pin to ground or leave open in serial mode.
28 D3 Data Bit in Parallel Mode. Connect this pin to ground or leave open in serial mode. 29 D2/LE Data Bit in Parallel Mode/Latch Enable in Serial Mode. 30 D1/DATA Data Bit in Parallel Mode (MSB)/Data in Serial Mode. 31 D0/CLK Connect this pin to ground in parallel mode. This pin functions as a clock in serial mode.
32 SEL Select Pin. Connect this pin to the supply to select parallel mode operation; connect this pin to ground to select serial mode operation.
EPAD Exposed Pad. The exposed pad must be connected to ground.
ADL5240 Data Sheet
Rev. A | Page 10 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
0
5
10
15
20
25
30
35
40
45
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 4.03.6
OIP3
P1dB
GAIN
NOISE FIGURE
NO
ISE
FIG
UR
E,
GA
IN,
P1d
B,
OIP
3 (d
B,
dB
m)
FREQUENCY (GHz) 0943
0-00
3
Figure 3. AMP: Gain, P1dB, OIP3 at POUT = 4 dBm/Tone and Noise Figure vs. Frequency
17.5
21.0
20.5
20.0
19.5
19.0
18.5
18.0
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6
–40°C
+25°C
+85°C
GA
IN (
dB
)
FREQUENCY (GHz) 0943
0-00
4
Figure 4. AMP: Gain vs. Frequency and Temperature
–40
–35
–30
–25
–20
–15
–10
–5
0
0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1
S12
S-P
AR
AM
ET
ER
S (
dB
)
FREQUENCY (GHz)
S11
S22
0943
0-00
5
Figure 5. AMP: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency
16
30
28
26
24
22
20
18
10
45
40
35
30
25
20
15
P1d
B (
dB
m)
OIP
3 (d
Bm
)
FREQUENCY (GHz)
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6
–40°C+25°C+85°C
0943
0-00
6
Figure 6. AMP: OIP3 at POUT = 4 dBm/Tone and P1dB vs. Frequency and Temperature
22
46
44
42
40
38
36
34
32
30
28
26
24
–5 1715131197531–1–3
OIP
3 (d
Bm
)
POUT PER TONE (dBm)
150MHz
450MHz
748MHz
943MHz
1960MHz 2140MHz
2630MHz
3600MHz
0943
0-00
7
Figure 7. AMP: OIP3 vs. POUT and Frequency
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0 4.03.63.22.82.42.01.61.20.80.4
NO
ISE
FIG
UR
E (
dB
)
FREQUENCY (GHz)
–40°C
+25°C
+85°C
0943
0-00
8
Figure 8. AMP: Noise Figure vs. Frequency and Temperature
Data Sheet ADL5240
Rev. A | Page 11 of 28
–40
–35
–30
–25
–20
–15
–10
–5
0
0.1 4.13.73.32.92.52.11.71.30.90.5
ATT
ENU
ATI
ON
(dB
)
FREQUENCY (GHz)
0dB
31.5dB
0943
0-00
9
Figure 9. DSA: Attenuation vs. Frequency
–36
–31
–26
–21
–16
–11
–6
–1
0.1 4.13.73.32.92.52.11.71.30.90.5
ATT
ENU
ATI
ON
(dB
)
FREQUENCY (GHz)
0dB
4dB
8dB
16dB
31.5dB
–40°C+25°C+85°C
0943
0-01
0
Figure 10. DSA: Attenuation vs. Frequency and Temperature
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0 32282420161284
STEP
ER
RO
R (d
B)
ATTENUATION (dB)
450MHz748MHz943MHz
1960MHz2140MHz2630MHz3600MHz
0943
0-01
1
Figure 11. DSA: Step Error vs. Attenuation
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1
STEP
ER
RO
R (d
B)
FREQUENCY (GHz) 0943
0-01
6
31.5dB30.5dB
16dB
31dB
Figure 12. DSA: Step Error vs. Frequency, All Attenuation States
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0 32282420161284
AB
SOLU
TE E
RR
OR
(dB
)
ATTENUATION (dB)
450MHz
748MHz
943MHz
1960MHz
2140MHz
2630MHz
3600MHz
0943
0-01
2
Figure 13. DSA: Absolute Error vs. Attenuation
–40
–35
–30
–25
–20
–15
–10
–5
0
0.1 4.1
0dB
3.73.32.92.52.11.71.30.90.5
INPU
T R
ETU
RN
LO
SS (d
B)
FREQUENCY (GHz)
31.5dB
0943
0-01
3
Figure 14. DSA: Input Return Loss vs. Frequency, All States
ADL5240 Data Sheet
Rev. A | Page 12 of 28
–40
–35
–30
–25
–20
–15
–10
–5
0
0.1 4.1
0dB
3.73.32.92.52.11.71.30.90.5
OU
TPU
T R
ETU
RN
LO
SS (d
B)
FREQUENCY (GHz)
31.5dB
0943
0-01
4
Figure 15. DSA: Output Return Loss vs. Frequency, All States
30
31
32
33
34
35
36
25
30
35
40
45
55
50
0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
IP1d
B (d
Bm
)
IIP3
(dB
m)
FREQUENCY (GHz)
IIP3
IP1dB
0943
0-01
5
Figure 16. DSA: Input P1dB and Input IP3 vs. Frequency,
Minimum Attenuation State
–150
–100
–50
0
50
100
150
200
0 4 8 12 16 20 24 28 32
PHA
SE (D
egre
es)
ATTENUATION (dB)
943MHz
1960MHz
2140MHz
2630MHz
0943
0-01
7
Figure 17. DSA: Phase vs. Attenuation
0943
0-01
8
CH3 2.00V CH4 200mV M10ns 10GS/sIT 1.0ps/pt
A CH3 1.24V
3
4
Figure 18. DSA: Gain Settling Time, 0 dB to 31.5 dB
0943
0-01
9
CH3 2.00V CH4 200mV M10ns 10GS/sIT 1.0ps/pt
A CH3 1.24V
3
4
Figure 19. DSA: Gain Settling Time, 31.5 dB to 0 dB
0
22
20
18
16
14
12
10
8
6
4
2
0.1 4.13.73.32.92.52.11.71.30.90.5
GA
IN A
ND
NO
ISE
FIG
UR
E (d
B)
FREQUENCY (GHz)
GAIN
NOISE FIGURE
0943
0-02
0
Figure 20. AMP-DSA Loop: Gain and Noise Figure vs. Frequency, Minimum Attenuation State
Data Sheet ADL5240
Rev. A | Page 13 of 28
–40
0
–5
–10
–15
–20
–25
–30
–35
0.1 4.13.73.32.92.52.11.71.30.90.5
S-PA
RAM
ETER
S (d
B)
FREQUENCY (GHz)
S11
S12
S22
0943
0-02
1
Figure 21. AMP-DSA Loop: Input Return Loss (S11), Output Return Loss (S22),
and Reverse Isolation (S12) vs. Frequency, Minimum Attenuation State
20
40
38
36
34
32
30
28
26
24
22
–6 1612 141086420–2–4
OIP
3 (d
Bm
)
POUT (dBm)
943MHz
2140MHz
2630MHz
0943
0-02
2
Figure 22. AMP-DSA Loop: OIP3 vs. POUT and Frequency,
Minimum Attenuation State
16.0
16.5
17.0
17.5
18.0
18.5
19.0
19.5
20.0
–4 2012 14 16 181086420–2
GA
IN (d
B)
POUT (dBm)
943MHz
2140MHz
2630MHz
0943
0-02
3
Figure 23. AMP-DSA Loop: Gain vs. POUT and Frequency,
Minimum Attenuation State
0
22
20
18
16
14
12
10
8
6
4
2
0.1 4.13.73.32.92.52.11.71.30.90.5
GAI
N AN
D NO
ISE
FIG
URE
(dB)
FREQUENCY (GHz)
GAIN
NOISE FIGURE
0943
0-02
4
Figure 24. DSA-AMP Loop: Gain and Noise Figure vs. Frequency,
Minimum Attenuation State
–35
–30
–25
–20
–15
–10
–5
0
0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1
S12
S-PA
RAM
ETER
S (d
B)
FREQUENCY (GHz)
S11
S22
0943
0-02
5
Figure 25. DSA-AMP Loop: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency, Minimum Attenuation State
24
44
38
40
42
36
34
32
30
28
26
–6 1612 141086420–2–4
OIP
3 (d
Bm
)
POUT (dBm)
943MHz
2140MHz
2630MHz
0943
0-02
6
Figure 26. DSA-AMP Loop: OIP3 vs. POUT and Frequency,
Minimum Attenuation State
ADL5240 Data Sheet
Rev. A | Page 14 of 28
16.0
16.5
17.0
17.5
18.0
18.5
19.0
19.5
20.0
–4 2012 14 16 181086420–2
GAI
N (d
B)
POUT (dBm)
943MHz
2140MHz
2630MHz
0943
0-02
7
Figure 27. DSA-AMP Loop: Gain vs. POUT and Frequency, Minimum Attenuation State
80
110
105
100
95
90
85
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
SUPP
LY C
URRE
NT (m
A)
TEMPERATURE (°C)
5.25V
5.00V
4.75V
0943
0-02
8
Figure 28. AMP: Supply Current vs. Voltage and Temperature
80
110
105
100
95
90
85
–6 –4 –2 0 2 4 6 8 10 12 14 16 18 20 22
SUPP
LY C
UR
REN
T (m
A)
POUT PER TONE (dBm) 0943
0-10
0
+85°C
+25°C
–40°C
Figure 29. AMP: Supply Current vs. POUT and Temperature
0
35
30
25
20
15
10
5
PER
CEN
TAG
E (%
)
GAIN (dB)
18.8
18.9
19.0
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
20.0
20.1
20.2
20.3
20.4
20.5
0943
0-02
9
Figure 30. AMP: Gain Distribution at 2140 MHz
0
30
25
20
15
10
5
PER
CEN
TAG
E (%
)
P1dB (dBm)
18.8
18.9
19.0
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
19.9
20.0
20.1
20.2
20.3
20.4
20.5
0943
0-03
0
Figure 31. AMP: P1dB Distribution at 2140 MHz
0
30
25
20
15
10
5
PERC
ENTA
GE
(%)
OIP3 (dBm)33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
0943
0-03
1
Figure 32. AMP: OIP3 Distribution at 2140 MHz
Data Sheet ADL5240
Rev. A | Page 15 of 28
0
70
60
50
40
30
20
10
PER
CEN
TAG
E (%
)
NOISE FIGURE (dB)2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
0943
0-03
2
Figure 33. AMP: Noise Figure Distribution at 2140 MHz
ADL5240 Data Sheet
Rev. A | Page 16 of 28
APPLICATIONS INFORMATION BASIC LAYOUT CONNECTIONS The basic connections for operating the ADL5240 are shown in Figure 34.
NC
VDD
NC
NC
NCNC
NC
NC
D1/
DA
TA
NC
D2/
LE D3
D5
D4
DSAOUT
NC
NC
D6
NCNC
D0/
CLKSE
L
AM
PIN
NC
NC
VDD
DSAIN ADL5240 NC
NCNC
NC
SERIAL PARALLEL INTERFACE
AM
POU
T/VC
C
68pF
100pF
1.2nF
470nH
VDD
100pF
VDD
0.1µF
AMPOUT
DSAIN DSAOUT
0.1µF AMPIN
1µF
VCC
0.1µF
C1C2
C3
C4
C5
C6 C7
C8
L1
1
2
3
4
5
6
7
8
9 10 161514131211
24
23
22
21
20
19
18
17
32 31 252627282930
0943
0-03
3
Figure 34. Basic Connections
Data Sheet ADL5240
Rev. A | Page 17 of 28
Amplifier Bias
The dc bias for the amplifier in ADL5240 is supplied through Inductor L1 and is connected to the AMPOUT pin. Three decoupling capacitors (C3, C4, and C5) are used to prevent RF signals from propagating onto the dc lines. The dc supply ranges from 4.75 V to 5.25 V and should be connected to the VCC test point on the evaluation board.
Digital Step Attenuator Bias
The bias for the DSA is provided through the VDD pin. At least one decoupling capacitor (C8) is recommended on the VDD trace. The voltage ranges from 4.75 V to 5.25 V and should be connected to the VDD test point on the evaluation board. The DSA is shown to work for dc voltages as low as 2.5 V.
Amplifier RF Input Interface
Pin 15 is the RF input for the amplifier of ADL5240. The amplifier is internally matched to 50 Ω at the input; therefore, no external components are required. Only a dc blocking capacitor (C1) is required.
Amplifier RF Output Interface
Pin 10 is the RF output for the amplifier of ADL5240. The amplifier is internally matched to 50 Ω at the output; therefore, no external components are required. Only a dc blocking capacitor (C2) is required. The bias is provided through this pin via a choke inductor.
DSA RF Input Interface
Pin 4 is the RF input for the DSA of ADL5240. The input impedance of the DSA is close to 50 Ω over the entire frequency range; therefore, no external components are required. Only a dc blocking capacitor (C6) is required.
DSA RF Output Interface
Pin 21 is the RF output for the DSA of ADL5240. The output impedance of the DSA is close to 50 Ω over the entire frequency range; therefore, no external components are required. Only a dc blocking capacitor (C7) is required.
DSA SPI Interface
The DSA of the ADL5240 can operate in either serial or parallel mode. Pin 32 (SEL) controls the mode of operation. To select serial mode, connect SEL to ground; to select parallel mode, connect SEL to VDD. In parallel mode, Pin 25 to Pin 30 (D6 to D1) are the data bits, with D6 being the LSB. Connect Pin 31 (D0) to ground during the parallel mode of operation. In serial mode, Pin 29 is the latch enable (LE), Pin 30 is the data (DATA), and Pin 31 is the clock (CLK). Pin 26, Pin 27, and Pin 28 are not used in serial mode and should be connected to ground. Pin 25 (D6) should be connected to VDD during the serial mode of operation. To prevent noise from coupling onto the digital signals, an RC filter can be used on each data line.
ADL5240 Data Sheet
Rev. A | Page 18 of 28
SPI TIMING Table 5 provides details about the timing characteristics for the SPI signals—namely, the clock (CLK), latch enable (LE), and data (DATA) signals—and Figure 35 shows the corresponding SPI timing diagram.
SPI Timing Sequence
Figure 36 is the timing sequence for the SPI function using a 6-bit operation. The clock can be as fast as 20 MHz. In serial mode, Register B5 (MSB) is first and Register B0 (LSB) is last.
Table 4. Mode Selection Table Pin 32 (SEL) Functionality Connect to Ground Serial mode Connect to Supply Parallel mode
Table 5. SPI Timing Setup Parameter Limit Unit Test Conditions/Comments
fCLK 10 MHz Data clock frequency t1 25 ns min Clock high time t2 25 ns min Clock low time t3 10 ns min Data to clock setup time
t4 10 ns min Clock to data hold time t5 10 ns min Clock low to LE setup time t6 30 ns min LE pulse width
0943
0-03
4
t3 t1t2
t5
t6
t4
DON'T CARE
DON'T CARE B4 B3 B2 B1
DON'T CARE
DON'T CARE
LE
MSBB5
CLK
DATA LSBB0
Figure 35. SPI Timing Diagram (Data Is Loaded MSB First), Serial Mode
0943
0-03
5
DON'T CARE
DON'T CARE B4 B3 B2 B1
DON'T CARE
DON'T CARE
D2/LE
MSBB5
D0/CLK
D1/DATA LSBB0
D6 Figure 36. SPI Timing Sequence, Serial Mode
Data Sheet ADL5240
Rev. A | Page 19 of 28
Table 6. DSA Attenuation Truth Table—Serial Mode Attenuation State (dB) B5 (MSB) B4 B3 B2 B1 B0 (LSB)
0 (Reference) 1 1 1 1 1 1 0.5 1 1 1 1 1 0 1.0 1 1 1 1 0 1 2.0 1 1 1 0 1 1 4.0 1 1 0 1 1 1
8.0 1 0 1 1 1 1 16.0 0 1 1 1 1 1 31.5 0 0 0 0 0 0
Table 7. DSA Attenuation Truth Table—Parallel Mode Attenuation State (dB) D1 (MSB) D2 D3 D4 D5 D6 (LSB) 0 (Reference) 1 1 1 1 1 1 0.5 1 1 1 1 1 0
1.0 1 1 1 1 0 1 2.0 1 1 1 0 1 1 4.0 1 1 0 1 1 1 8.0 1 0 1 1 1 1
16.0 0 1 1 1 1 1 31.5 0 0 0 0 0 0
ADL5240 Data Sheet
Rev. A | Page 20 of 28
LOOP PERFORMANCE The ADL5240 can be configured so that either the DSA precedes the amplifier (see Figure 37) or the amplifier precedes the DSA (see Figure 38). The performance of the loop configurations is presented in Figure 20 to Figure 27. To improve the overall return loss, a shunt capacitor can be placed between the amplifier and DSA. This helps to align the phases of the two blocks.
NC
VDD
NC
NC
NCNC
NCN
CD
1/D
ATA
NC
D2/
LE D3
D5
D4
DSAOUT
NC
NC
D6
NCNC
D0/
CLKSE
L
AM
PIN
NC
NC
VDD
DSAIN ADL5240 NC
NCNC
NC
SERIAL PARALLEL INTERFACE
AM
POU
T/VC
C
68pF
100pF
1.2nF
470nH
VDD
VDD
0.1µF
RFOUT
RFIN
100pF
1µF
VCC
0.1µF
C1C2
C3
C4
C5
C6
C7
L1
1
2
3
4
5
6
7
8
9 10 161514131211
24
23
22
21
20
19
18
17
32 31 252627282930
0943
0-03
6
Figure 37. DSA-AMP Loop Configuration
Data Sheet ADL5240
Rev. A | Page 21 of 28
NC
VDD
NC
NC
NCNC
NC
NC
D1/
DA
TA
NC
D2/
LE D3
D5
D4
DSAOUT
NC
NC
D6
NCNC
D0/
CLKSE
L
AM
PIN
NC
NC
VDD
DSAIN ADL5240 NC
NCNC
NC
SERIAL PARALLEL INTERFACE
AM
POU
T/VC
C
68pF
1.2nF
470nH
VDD
100pF
VDD
0.1µF
RFOUT
0.1µF RFIN
1µF
VCC
C1
C3
C4
C5
C6
C7
C2100pF
L1
1
2
3
4
5
6
7
8
9 10 161514131211
24
23
22
21
20
19
18
17
32 31 252627282930
0943
0-03
7
Figure 38. AMP-DSA Loop Configuration
ADL5240 Data Sheet
Rev. A | Page 22 of 28
AMPLIFIER DRIVE LEVEL FOR OPTIMUM ACLR It is usually required to drive the amplifier as high as possible in order to maximize output power. However, properly driving Amplifier at the ADL5240 is required to achieve optimum ACLR performance. Once output power approaches P1dB and OIP3, there is ACLR degradation. The driving level of amplifier with a modulated signal should be backed off properly from P1dB by at least the amount of a signal crest factor for optimum ACLR. So assuming a gain and output P1dB of Amplifier at 2140 MHz are 19 dB and 19 dBm respectively, the output power, which is backed off by 11 dB crest factor at the modulated signal case, is 8 dBm. Therefore, the proper input driving level should be under −11 dBm.
–90
–30
–40
–50
–60
–70
–80
–40 –35 –30 –25 –20 –15 –10 –5
AC
PR (d
Bc)
PIN (dBm) 0943
0-10
1
AMP_ADJ
AMP_ALT
Figure 39. Single Carrier WCDMA Adjacent Chanel Power Ratio vs. Input
Power at Amplifier, 2140 MHz
THERMAL CONSIDERATIONS The ADL5240 is packaged in a thermally efficient, 5 mm × 5 mm, 32-lead LFCSP. The thermal resistance from junction to air (θJA) is 36.8oC/W. The thermal resistance for the product was extracted assuming a standard 4-layer JEDEC board with 25 conductive, epoxy filled thermal vias. The thermal resistance from junction to case (θJC) is 6.9oC/W, where case is the exposed pad of the lead frame package.
The ADL5240 consumes approximately 93 mA with a 5 V supply voltage. Even though the part dissipates less than 0.5 W, for the best thermal performance, it is recommended to add as many thermal vias as possible under the exposed pad of the LFCSP. The thermal resistance values given in this section assume a minimum of 25 thermal vias arranged in a 5 × 5 array with a diameter of 13 mils and a pitch of 25 mils. Figure 40 shows a close-up of the thermal via distribution under the exposed pad.
0943
0-03
8
Figure 40. Exposed Pad with Thermal Via Distribution
Data Sheet ADL5240
Rev. A | Page 23 of 28
EVALUATION BOARD The schematic of the ADL5240 evaluation board is shown in Figure 41, the evaluation board configuration options are detailed in Table 8, and the layout of the ADL5240 evaluation board is shown in Figure 43 and Figure 44. Each RF trace on the evaluation board has a characteristic impedance of 50 Ω and is fabricated on Rogers3003 material. In addition, each trace is a coplanar waveguide (CPWG) with a width of 25 mils, a spacing of 20 mils, and a dielectric thickness of 10 mils. The input to and output from the DSA and amplifier should be ac-coupled with capacitors of appropriate values to ensure the broadband performance. The bias to the amplifier is provided by connecting a choke to the AMPOUT pin. Bypassing capacitors are recommended on all supply lines to minimize the RF coupling. The DSA and the amplifier can be individually biased or connected to the VDD plane using Resistors R2 and R1.
The ADL5240 can be operated in two ways: the amplifier can precede the DSA (AMP-DSA loop configuration) or the DSA can precede the amplifier (DSA-AMP loop configuration). The evaluation board can be configured to handle either option. In normal operation, R12 and R13 are open, and R10 and R11 are 0 Ω and are used to terminate any RF coupling onto the bypass trace. To configure the ADL5240 in AMP-DSA loop configuration, R12 should be replaced with a capacitor, R13 should be replaced with a 0 Ω resistor, and R10 and R11 should be left open. Similarly, to configure the ADL5240 in the DSA-AMP loop configuration, R16 should be replaced with a capacitor, R17 should be replaced with a 0 Ω resistor, and R14 and R15 should be left open.
The digital signal traces incorporate a footprint for an RC filter to prevent potential noise from coupling onto the signal. In normal operation, series resistors are 0 Ω and shunt resistors and capacitors are open.
The evaluation board is designed to control DSA in either parallel or serial mode by connecting the SEL pin to the supply or ground by a switch.
For adjusting attenuation at DSA, the ADL5240 can be programmed in two ways: through the on-board USB interface from a PC USB port, or through an SDP board, which will become the Analog Devices common control board in the future. The on-board USB interface circuitry of the evaluation board is powered directly by the PC. USB based programming software is available to download from the ADL5240 product page at www.analog.com. Figure 45 shows the window of the programming software where the user selects serial or parallel mode for the attenuation adjustment at DSA. The selection of the mode in the window should match the mode of the evaluation board switch.
It is highly recommended to refer the evaluation board layout for the optimal and stable performance of each block as well as for the improvement of thermal efficiency.
ADL5240 Data Sheet
Rev. A | Page 24 of 28
0943
0-03
9
5 4 3 2
1AMPIN
5 4 3 2
1DSAOUT
C8
C5
R15
R17
R14
R16
R2
C17
23
1
S1
VDD
241
32
1211
9
8765
32322
20191817
161413
2
PAD
214
2526272829303110 15
U1
R1
5432
1AMPOUT
C13
VCC
C4
5432
1DSAIN C1
C14 C15
R11
R10
R13
R12
2 1L1
VDD
VDD
D5D4
D6
CLK_D0DATA_D1LE_D2
D3
0DNI
1µF
RED
1200pF
0.1µF
100pF
DNI0
DNI0
0.1µF
DNI0
68pF
470nH
0DNI
0DNI
ADL5240ACPZ
RED
DNI0
DNI0
0.1µF
0DNI
0DNI
100pF
EPA
DSE
LD
0/C
LKD
1/D
ATA
D2/
LE D3
D4
D5
D6
VDDNCNC
DSAOUTNCNCNCNC
NC
AM
PIN
NC
NC
NC
NC
AM
POU
T/VC
CN
C
NCNCNCNCDSAINNCNCVDD
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND AGND
Figure 41. ADL5240 Evaluation Board
Table 8. Evaluation Board Configuration Options Component Function/Notes Default Value
C1, C2 Input/output dc blocking capacitors for DSA. C1, C2 = 100 pF C3, C4 Input/output dc blocking capacitors for AMP. C3, C4 = 0.1 µF C5, C6, C7 Power supply decoupling for amplifier. The bias associated with the AMPOUT pin is
the most sensitive to noise because the bias is connected directly to the output. The smallest capacitor (C7) should be the closest to the AMPOUT pin.
C5 = 1 µF C6 = 1.2 nF C7 = 68 pF
C8 Power supply decoupling for the DSA. C8 = 0.1 µF
L1 The bias for the amplifier comes through L1 when VCC is connected to a 5 V supply. L1 should be high impedance for the frequency of operation while providing low resistance for the dc current.
L1 = 470 nH
R1, R2 Resistors to connect the supply for the amplifier and the DSA to the same VDD plane. R1, R2 = open R10, R11, R14, R15 These resistors are used to terminate RF coupling onto the traces and to close the loop. R10, R11, R14, R15 =
0 Ω
R12, R13, R16, R17 R12 and R16 are replaced with capacitors, and R13 and R17 are replaced with 0 Ω to close the loop.
R12, R13, R16, R17 = open
S1 Switch to change between the serial mode and parallel mode of operation. Connect to supply for parallel mode and to ground for serial mode operation.
S1 connected to ground
Data Sheet ADL5240
Rev. A | Page 25 of 28
DEC
OU
PLIN
G F
OR
U1
PLA
CEH
OLD
ER
R29
C19
R28
C18
R27
C16
C12
R26
R25
R23
R20
R19
R46
AC
CR
2R
8R
55
R24
R54
R53
C53
R13
C55
R14
C56
98765432 101P3
4
5
44
554332271711
1615 42 14
21
52515049484746452524232221201918
PAD
403938373635343313
565341282612
8 9 31302954
73
106
U4
C35
C36
C38
C39
C45
C46
C48
R45
AC
D1
R4
C37
6 PAD
2187
5
3U3
R3C44
R9
C47
7
8
56
4
321U
2R
5
C49
C34
R47
R7
C31
C50
54321 G4
G3
G2
G1
P1
C51
31
42
Y1
C52
C33C9
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
330p
FD
NI
DN
I1.00kΩ
0Ω
JED
EC_T
YPE=
QFN
56_8
X8_P
AD
5_2X
4_5
DN
ID
NI
DN
I 330p
FD
NI
330p
FD
NI
330p
FD
NI
330p
F
1.00kΩ
SML-
210M
TT86
330p
F33
0pF
100kΩ
DN
I100kΩ
CY7
C68
013A
-56L
TXC
PA5
PA6
PA4
PB0
PA1
PA3
PA2
LE_D
2
DA
TA_D
1
CLK
_D0
PA7
PB3
CTL
2_FL
AG
C
24LC
64-I-
SN
LE_D
2
CLK
_D0
TSW
-105
-08-
G-D
897-
43-0
05-0
0-10
0001
DA
TA_D
1
CTL
1_FL
AG
BC
TL0_
FLA
GA
DM
5V_U
SB
PD5
D4
D3
D6
D6
D5
D5
D4
D3
DN
I1.00kΩ
DN
I1.00kΩ
DN
I
1.00kΩ
0Ω
DN
I
PA0 0Ω 0Ω 0Ω
0Ω 0Ω
DP
2kΩ
PD1
PD2
CLK
OU
T
RES
ETN
PD7
PD4
PD6
PD3
PD0
PB7
PB5
PB6
PB2
PB4
PB1
IFC
LK
2kΩ
AD
P333
4AC
PZ
3V3_
USB
XTA
LIN
22pF
1.00kΩ
DN
I1.00kΩ
DN
I
0.1µ
F
10pF
0.1µ
F
2kΩ
DN
I
0.1µ
F0.
1µF
0.1µ
F0.
1µF
0.1µ
F0.
1µF
SML-
210M
TT86
2kΩ
78.7kΩ
1000
pF140kΩ
FB
E013
815
10pF
0.1µ
F22
pF
XTA
LOU
T
0.1µ
F
SDA
WA
KEU
P
SCL
1µF
1µF
24.0
0000
0MH
Z
3V3_
USB
0Ω
5V_U
SB
0.1µ
F
OU
T
PIN
SG
ND
DG
ND
DG
ND
CA
SE
DG
ND
AG
ND
DG
ND
PAD
CLK
OU
T
PD7_
FD15
PD6_
FD14
PD5_
FD13
PD4_
FD12
PD3_
FD11
PD2_
FD10
PD1_
FD9
PD0_
FD8
WA
KEU
P
RES
ET_N
PA7_
FLA
GD
_SLC
S_N
PA6_
PKTE
ND
PA5_
FIFO
AD
R1
PA4_
FIFO
AD
R0
PA3_
WU
2PA
2_SL
OE
PA1_
INT1
_NPA
0_IN
T0_N
VCC C
TL2_
FLA
GC
CTL
1_FL
AG
BC
TL0_
FLA
GA
GN
D
PB7_
FD7
PB6_
FD6
PB5_
FD5
PB4_
FD4
PB3_
FD3
PB2_
FD2
PB1_
FD1
PB0_
FD0
SDA
SCL
RES
ERVE
D
IFC
LKD
MIN
US
DPL
US
AG
ND
XTA
LIN
XTA
LOU
TA
VCC
RD
Y1_S
LWR
RD
Y0_S
LRD
DG
ND
DG
ND
IN
IO
IN1
IN2
OU
T2O
UT1
PAD
FBG
ND
SD_N
DG
NDG
ND
SCL
SDA
WC
_N
A2
A1
A0
VCC
ININ IN
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
OU
T
OU
T
OU
T
OU
T
OU
T
OU
T
OU
T
OU
T
OU
T
OU
T
OU
T
OU
T
OU
T
OU
T
OU
T
OU
T
(FR
OM
MA
IN B
OA
RD
; 200
mA
MIN
IMU
M)
1D
GN
D1
1
5V_S
DP
R21
R22
R17
R42R6
R18
R43
R44
7
48
56321
U5
112
113
114
61115
62636465666768697071116
72737475767778798081117
82838485868788899091118
9293949596979899100
101
119
102
103
104
105
106
107
108
109
110
111
120
P2
987 606 595857565554535251505 494847464544434241404 393837363534333231303 292827262524232221202 191817161514131211101P2
DG
ND
DG
ND
LE_D
2
CLK
_D0
TBD
0603
DN
I
100kΩ
100kΩ
DN
I
24LC
32A
-I/M
S
JED
EC_T
YPE=
MSO
P8E0
1416
0
0ΩD
NI
FX8-
120S
-SV(
21)
DN
I
0ΩD
ATA
_D1
0Ω
0Ω 0Ω
DN
ID
5D
4D
3
RED
5V_S
DP
FX8-
120S
-SV(
21)
D6
BLK
DG
ND
DG
ND
VSS
VCC
WP
A2
A1
A0
SCL
SDA
OU
T
OU
TO
UT
OU
TO
UT
OU
TO
UT
OU
T
OU
TO
UT
OU
TO
UT
09430-102
Figure 42. USB/SDP Interface Circuitry on the Customer Evaluation Board
ADL5240 Data Sheet
Rev. A | Page 26 of 28
0943
0-04
0
Figure 43. Evaluation Board Layout—Top
0943
0-04
0
Figure 44. Evaluation Board Layout—Bottom
Data Sheet ADL5240
Rev. A | Page 27 of 28
0943
0-10
3
Figure 45. Evaluation Board Control Software
ADL5240 Data Sheet
Rev. A | Page 28 of 28
OUTLINE DIMENSIONS
3.453.30 SQ3.15
FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
132
89
2524
1716
COPLANARITY0.08
3.50 REF
0.50BSC
PIN 1INDICATOR
PIN 1INDICATOR
0.300.250.18
0.20 REF
12° MAX 0.80 MAX0.65 TYP
1.000.850.80 0.05 MAX
0.02 NOM
SEATINGPLANE
0.500.400.30
5.00BSC SQ
4.75BSC SQ
0.60 MAX0.60 MAX
0.25 MIN
05-2
3-20
12-A
TOP VIEW
EXPOSEDPAD
BOTTOM VIEW
Figure 46. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad (CP-32-3)
Dimensions shown in millimeters
ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADL5240ACPZ-R7 −40°C to +85°C 32 Lead LFCSP_VQ, 7" Tape and Reel CP-32-3
ADL5240-EVALZ Evaluation Board 1 Z = RoHS Compliant Part.
©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09430-0-6/13(A)