12-June-03Concept for Booster LLRF - G. W. Foster A Concept for Using the Digital Damper Board to...

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12-June-03 Concept for Booster LLRF - G. W. Foster

A Concept for A Concept for Using the Using the

Digital Damper Digital Damper Board to Board to

Upgrade the Upgrade the Booster LLRFBooster LLRF

Bill Foster June 12, 2003

Talk Outline• Motivation• System Concept• Options for Clock Domains • Digital Phase Detector & PLL• Radial Position Signal• Notching & Multi-Batch Sync.• 12 Step Plan

MOTIVATION

Booster Low-Level RF.

The Final Frontier.

Booster Low-Level RF

Ya Got Trouble :--Professor Harold Hill in “The Music Man”

“Well, either you're closing your eyes To a situation you do not wish to acknowledge

Or you are not aware of the caliber of disaster indicatedBy the presence of a pool table in your community.

Booster LLRF in your accelerator.Ya got trouble, my friend, right here, I say, trouble right here in River City…

...that’s Trouble with a capital T that rhymes with B…”

If something breaks…

SHIRLEYJONESAT ~25

Shirley Jones hit her prime in the 1960’s …much like the Booster.

Shirley Jones in “The Partridge Family”

mother of David & Shaun

Cassidy

Married to Jack Cassidy

Booster LLRF External Connections• ~5 Inputs:

1. Wall-Current Monitor (Phase)2. Transverse Pickup (RPOS) (BNL Uses two…)3. Start Pulse (TCLK)4. BDOT (Low bandwidth… replace w/lookup?)5. MI AA Marker (Phase lock & notch cogging)

• Two Outputs: Cavity A&B Drives• (Optional?) Beam Clock Output

2. RPOS

3. TCLK

1. WCM

5. MI RF4. BDOT

A&B DRIVE OUT

Notching and Cogging

Generic Hardware Concept for Accelerator Instrumentation & Control

Monster FPGA

53 MHz, TCLK, MDAT,...

MinimalAnalogFilter

FASTADC

Cables from Tunnel

MinimalAnalogFilter

FASTADC

.........

FASTDAC

CPU BusVME/VXI/PCI/PMCetc.

INPUTS:BPMStripline PickupResistive WallFlying Wire PMTRF FanbackKicker Monitor…etc.

OUTPUTS:Stripline KickerRF FanoutAnalog Monitor…etc.

..OR.. NIMWith

Ethernet or

FireWire

Damper With Frequency Sweep

FIFO needed due to phase shifts between DAC and ADC clocks as beam accelerates

RFClock

BeamPickup

ADC ClockDelay Cable

INADCSignal Cable

DAC OUT

KICKER

PipelinedDigital Calc.

All LogicInsideFPGA

53 MHz, TCLK, MDAT,...

All-Coordinate Digital Damper

Monster FPGA(s)

MinimalAnalogFilter

FASTADC

Stripline Pickup

MinimalAnalogFilter

FASTADC

106 / 212 MHz

Stripline Kicker

PowerAmp

MinimalAnalogFilter

FASTADC

Resistive Wall Monitor

Broadband Cavity

FASTDACs

> 27 MHz

FASTDACs

PowerAmp

TransverseDampers

IdenticalX & Y

Longi-tudinal

(Z)Damper

TCLK, 53 MHz, MI AA, MDAT,...

Digital Booster LLRF Concept

Monster FPGA

DDS Beam Synched Clock 160-212 MHz

(4x Booster RF)

MinimalAnalogFilter

FASTADC

WallCurrentMonitor(PHASE)

FASTDAC 12

ETHERNET

MinimalAnalogFilter

FASTADC

MinimalAnalogFilter

FASTADC

12RPOS

[crystal] 400 MHz

FASTDAC

“A” Drive

FASTDAC

“B” Drive12

Echotek Card Used for Initial Dampers

105 MSPS AD6645

•Echotek Board Originally Built to SLAC Design Specification•65MHz DDC version to be used for RR BPM upgrade•105 MHz version (with DAC “daughter card”) used for Dampers

212 MHz DAC Daughter Card

(S. Hansen/ PPD)

Butchering the Echotek Board• Scorched-Earth FPGA rewrite (GWF)

– ~65 pages of firmware since Jan ‘03• 212 MHz DAC “Daughtercard”

– Sten Hansen & T. Wesson (PPD)– 3 channels for X,Y,Z

• 212 MHz Output FIR (W. Schappert, RFI)– Pre-emphasis compensation for analog outputs– Prototype for 424 MHz output on final board

• Input Buffer Amp/Splitter Box (Brian Fellenz,RFI)

New Damper Board (A. Seminov)• SINGLE high-end FPGA (Altera Stratix EP1S25F672)

• Four 212 MHz, 12-Bit ADCs (AD 9430) (With AD8369 VGA controlled by FPGA on input)

• Four 424 MHz, 14-Bit DACs (TI DAC5675)

• Digital Inputs:– TCLK, MDAT, BSYNCH, 53 MHz, Marker Pulse

• Digital Outputs:– TTL, scope trigger, 1 GHz serial Links, firewire..

• Megabytes of Fast Memory (FIFOs & DSP RAM)

• “NIM module” with Ethernet interface to ACNET

This ADC can sample 53 MHz signals at 4 samples per RF cycle to measure both In-Phase and Quadrature on each cycle

Digital Gain Control via FPGAChange gains “on the fly” or cycle-by-cycle

Clock Domain Option #1:(being pursued at BNL – PAC’03)

Single crystal ~212 MHz clocks everything.• Fixed Frequency ADCs & DACs, No Explicit PLLs • Asynchronous to Beam • Classical Digital Receiver for Phase Detector• Classical Direct Digital Synthesis of RF Outputs

Concerns:- funny behavior as frequency sweeps?- lots of clock boundary crossings- approach does not naturally provide beam clock- bunch-by-bunch phase measurement difficult

12-June-03 Concept for Booster LLRF - G. W. FosterBNL Switching from Digital Reciever ChipTo FPGA Firmware Implementation

BNL PAC’03

Clock Domain Option #2:(preferred)

1. Use one DAC Channel for Crystal-Controlled DDS of Beam-Synched RF Clock (38-53MHz)

2. The rest of circuit operates from this RF clock• Variable Frequency ADCs & DACs• Synchronous to Beam • Simple Implementation of Phase Detector & RF out• naturally provides beam clock• Few clock boundary crossings, simpler pipeline logicConcerns:

- Tracking of PLLs on FPGA, ADCs, & DACs

Q: What ADC Clock Speed is needed?

A: 4x RF Bunch Frequency

• Minimum needed for bunch-by-bunch Phase and Amplitude measurement

• In frequency domain, 4x RF sampling measures both in-phase and quadrature components.

• For Fermilab’s 53 MHz RF 212 MHz ADC’s

212 MHz Sampling of RWM Pulse

Low-pass Filter

Spreads signal +/-5ns in time so it will not be missed by

ADCFilterReduces ADC

Dynamic Range

requirement, since spike does not

have to be digitized

FilteredOutput

Input Pulse from RWM

-25 ns -15 ns -5 ns 5 ns 15 ns 25 ns

single-bunch "phase" signal = samples (B - D)

single-bunch "intensity" signal = C - average(A,E)

Longitudinal Beam Instability in MI

• Driven by cavity wake fields within bunch train• Seeded by Booster & amplified near MI flat top.

First Bunch ~ OK 7th Bunch Trashed

• Occurs with as few as 7 bunches (out of 588)

• Prevents low emittance bunch coalescing and efficient Pbar bunch rotation

Bunch-By-Bunch Phase vs. Turn NumberMeasured with MI Digital Damper

1 501 1001 1501 2001 2501 3001 3501

• LLRF will Feed Back on Digital average of 84 Bunches

• Damper Output derived from individual bunch phase errors

Bunch-By-Bunch Intensity

Radial Position (RPOS)

1. Use existing detector (RF Module)• Requires special RF clock out?• Low Digitization Bandwidth Required

2. Digitize BPM plates directly to get signal• More general approach• Less hardware• Choose which bunch(es) to feed back on• Gives a bunch-by-bunch signal for damper &

diagnostics

212 MHz Sampling of Stripline Signal

Roles of “Phase” and “Amplitude” signals are reversed

from unipolar case.

FilteredOutput

Input Doublet

-25 ns -15 ns -5 ns 5 ns 15 ns 25 ns

Single-Bunch Amplitude signal is(B - D) samples of filtered output

Phase Signal isC - Average(A,E)

Repetitive Waveform looks like simple sine wave, but contains bunch-by-bunch phase and amplitude

“A - B” gives bunch-by-bunch “in-

phase” signal

Vector Sum sqrt(I**2 +Q**2) is

insensitive to clock jitter

FilteredOutput

Input Doublet

-25 ns -15 ns -5 ns 5 ns 15 ns 25 ns

“D - (C+E)/2” gives

bunch-by-bunch “out-of-

phase” or “quadrature”

signal

MAIN INJECTOR VERTICAL BPM (8 Bits)

DIGITAL DAMPER POSITIONSIGNAL (Batch Average)

Single-Bunch BPM Measurement was tested by blowing out nearby bunches during Stacking Cycle

MAIN INJECTOR VERTICAL BPM (8 Bits)

DIGITAL DAMPER POSITIONFOR SINGLE 53 MHz BUNCH

SINGLE-TURN (non-averaged)

BPM Resolution for 212 MHz Digitization of Single 53 MHz Bunch

Bunch-By-Bunch Control RAM(in FPGA Firmware)

• Bunch-by-bunch Damping Gain

• Damping or Anti-Damping

• Pinger with Programmable Tune, Timing…

• Digital Random Noise Injected Into any Bunch

Filter for Undamped, Damped, and Anti-Damped Bunches

Blowing Selected Bunches out of the Machine (in X,Y, or both)

Neutrino Communications! …1110111001110001111…

ACNET CONTROLS• LLRF can behave differently on different

cycles– Each control register becomes an ACNET Array

Device indexed by MI State– Register contents switch automatically when MI

State changes (D. Nicklaus)

ACNET Control Devices (>250 total)• Master control

registers & diagnostics are typically single devices

• Configuration control registers are array devices indexed by MI State

Adding a new ACNET Device

Takes about 10 minutes from concept to Fast-Time Plot

1) Add register(s) to FPGA Firmware

2) Start Recompile (takes ~6 minutes)3) Meanwhile, use DABBEL/D80 to define

properties of new ACNET device4) Download Firmware & Reboot Crate (~2 min.)

So, What Problems are You Trying to Solve with this?

• Reliability & Maintainability• Spares (incl. Hot spare for Experiments)• Cycle-By-Cycle Programmability• Notching & MI Synchronization• Digital Reproducibility• “Virtual Oscilloscope” on all signals• Documentation• Office Space!

12-June-03Concept for Booster LLRF - G. W. Foster A Concept for Using the Digital Damper Board to...

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