Post on 05-Dec-2015
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Close Your Coverage Loop with Graph-Based Scenario Models
Jörg Große
Applications Engineer
Breker Verification Systems, Inc.
Verification Futures 2012
• The Universal Verification Methodology (UVM) is breaking down for full-SoC verification– Full-chip simulation too slow to run long random tests– No link between testbench and embedded processors
• Hard to hand-write C tests for embedded processors– Can’t track multi-threaded, multi-processor tests in parallel– Hand written C-test are difficult to maintain and extend
• Weak quality metrics– Only interface toggle coverage– Hand written C tests == functional coverage
Verification Futures 2012 © 2005 - 2012 Breker Verification Systems, Inc. All rights reserved.
SoC Verification Has a Problem
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• Many SoC teams just “stitch and ship”– Run checks for connectivity of blocks within the full chip– Run a few sanity tests with an incomplete UVM testbench– Do basic IP integration testing with hand-written C tests– Insufficient coverage metrics at the full-SoC level
• Some SoC teams rely on emulation and prototyping– Bugs found post-simulation are harder to diagnose and fix– Bugs found late in the project tend to delay the schedule– Production software is well-behaved and unlikely to hit
corner cases
Verification Futures 2012 © 2005 - 2012 Breker Verification Systems, Inc. All rights reserved.
Today’s Reality
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The SoC Verification “Iceberg”
Verification Futures 2012 © 2005 - 2012 Breker Verification Systems, Inc. All rights reserved.
Connectivity Tests
System and Power Management
Concurrency
Coherency
IP Integration Tests
Performance Verification
System Use Cases
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Manually Developed SoC Tests
• Manual development and maintenance
• Difficult to manage:
• Multiple threads
• Multiple processors
• Multiple memories
• Interaction with I/O ports
Verification Futures 2012 © 2005 - 2012 Breker Verification Systems, Inc. All rights reserved.
Connectivity Tests
System & Power Management
Concurrency
Coherency
IP Integration Tests
Performance Verification
System Use Cases
Connectivity Tests
System & Power Management
Concurrency
Coherency
IP Integration Tests
Performance Verification
System Use Cases
Testbench
SoCRTL CPU Image
ProcessorMemory
CameraDisplay
Controller
Fabric
Fabric
BFM
SD CardController
BFM BFM
Systemand
PowerControl
Compiler
test.ctest.ctest.ctest.ctest.ctest.c
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test.ctest.ctest.cTrekSoC
TrekSoC Automatic Self-Verifying C Test Cases
Connectivity Tests
Register / Memory Map
System & Power Management
System Scenarios
Concurrency
Coherency
IP Integration Tests
Driver Scenarios
Performance Verification
System Use Cases
Application Scenarios
Concurrency
Coherency
Compiler
Verification Futures 2012 © 2005 - 2012 Breker Verification Systems, Inc. All rights reserved.
Testbench
SoCRTL CPU Image
ProcessorMemory
CameraDisplay
Controller
Fabric
Fabric
BFM
SD CardController
BFM BFM
Systemand
PowerControl
test.ctest.cevents.rc
Tre
kBo
x
mailbox
6
test.ctest.ctest.cTrekSoC
TrekSoC Automatic Self-Verifying C Test Cases
Connectivity Tests
System & Power Management
Concurrency
Coherency
IP Integration Tests
Performance Verification
System Use Cases
Concurrency
Coherency
Compiler
Verification Futures 2012 © 2005 - 2012 Breker Verification Systems, Inc. All rights reserved.
Testbench
SoCRTL CPU Image
ProcessorMemory
CameraDisplay
Controller
Fabric
Fabric
BFM
SD CardController
BFM BFM
Systemand
PowerControl
test.ctest.cevents.rc
Tre
kBo
x
mailbox
SD
SoC
IPScenarioModel
Cam
7
Multiple Design Level Support
Verification Futures 2012 © 2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 8
test.ctest.ctest.cTrekSoC
Compiler
Testbench
SoCRTL CPU Image
ProcessorMemory
CameraDisplay
Controller
Fabric
Fabric
BFM
SD CardController
BFM BFM
Systemand
PowerControl
test.ctest.cevents.rc
Tre
kBo
x
mailbox
TrekSoC
Testbench
SoCRTL
ImageProcessor
Memory
CameraDisplay
Controller
Fabric
Fabric
BFM
SD CardController
BFM BFM
Systemand
PowerControl
BFM
SD
SoC Cam
TrekSoC
Testbench
ImageProcessor
BFM
BFM
IPScenarioModel
Scenario Models: Visualize Your Verification Space
Configure:Tables,Modes
Verification Futures 2012 © 2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 9
Pre-Simulation Reachability
Unreachable Input Case
© 2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 10Verification Futures 2012
Coverage
Cases Not Yet Covered
© 2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 11Verification Futures 2012
Closed-Loop Coverage
Automatically Close Coverage Targets with minimal cyclesExample: “cross the two sets and walk all 8 paths”
© 2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 12Verification Futures 2012
• Stitch and ship verification is not sufficient for an SoC
• TrekSoC automatically generates C test cases
– Run on the embedded processors and link to testbench
– Quickly satisfy your functional coverage requierments
– But still generating deep corner case scenarios
• Scenario models are easy and natural to create
– Graphs efficiently capture verification knowledge
– Graphs help internal communication and allow teams to define the functional coverage requirements
Summary
© 2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 13Verification Futures 2012
Verification Futures 2012 © 2005 - 2012 Breker Verification Systems, Inc. All rights reserved.
Thanks for Listening!
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