Post on 31-Dec-2015
transcript
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
ANGLES
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
DATE
APPDENG
DATE
APPDCK
ECNZONEREV
DO NOT SCALE DRAWING
X.XXX
X.XX
XX
DIMENSIONS ARE IN MILLIMETERS
THIRD ANGLE PROJECTIOND
SIZE
APPLICABLENOTED AS
MATERIAL/FINISH
NONE
SCALE
DESIGNER
MFG APPD
DESIGN CK
RELEASE
QA APPD
ENG APPD
DRAFTER
METRIC
OFSHT
DRAWING NUMBER
TITLE
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PARTII NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
Apple Computer Inc.
12345678
12345678
B
C
D
A
B
C
D
A
REV.
DESCRIPTION OF CHANGE
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD
DRAWING
TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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03/03/2006SCHEM,MLB,M1
Schematic / PCB #’s
4541 (MASTER)(MASTER)FireWire Port Power
4440 08/29/2005(M42)FIREWIRE CONTROLLER
4339 (MASTER)(MASTER)Yukon Power Control
4238 (MASTER)(MASTER)Ethernet Connector
4137 10/12/2005M42ETHERNET CONTROLLER
3836 (MASTER)(MASTER)PATA Connector
3735 (MASTER)(MASTER)Mobile Clocking
3434 (MASTER)(MASTER)Clock Termination
3333 10/12/2005M42CLOCKS
3232 (MASTER)(MASTER)DDR2 VRef
3131 (MASTER)(MASTER)Memory Vtt Supply
3030 (MASTER)(MASTER)Memory Active Termination
2929 (MASTER)(MASTER)DDR2 SO-DIMM Connector B
2828 (MASTER)(MASTER)DDR2 SO-DIMM Connector A
2727 (MASTER)(MASTER)M1 SMBus Connections
2626 (MASTER)(MASTER)SB Misc
2525 11/16/2005M42SB Decoupling
2424 11/16/2005M38SB: 4 OF 4
2323 11/16/2005M38SB: 3 OF 4
2222 09/08/2005(M38)SB: 2 of 4
2121 11/16/2005M38SB: 1 OF 4
2020 (MASTER)(MASTER)NB Config Straps
1919 (MASTER)(MASTER)NB (GM) Decoupling
1818 (MASTER)(MASTER)NB Grounds
1717 (MASTER)(MASTER)NB Power 2
1616 (MASTER)(MASTER)NB Power 1
1515 (MASTER)(MASTER)NB DDR2 Interfaces
1414 (MASTER)(MASTER)NB Misc Interfaces
1313 (MASTER)(MASTER)NB PEG / Video Interfaces
1212 (MASTER)(MASTER)NB CPU Interface
1111 10/12/2005M42CPU ITP700FLEX DEBUG
1010 10/07/2005M42CPU MISC1-TEMP SENSOR
99 (MASTER)(MASTER)CPU Decoupling & VID
88 11/16/2005M42CPU 2 OF 2-PWR/GND
77 11/16/2005M42CPU 1 OF 2-FSB
66 N/AN/ASignal Aliases
55 N/AN/AFunctional / ICT Test
44 N/AN/ABOM Configuration
33 N/AN/APower Block Diagram
22 N/AN/ASystem Block Diagram
(MASTER)104 (MASTER)
M1 Net Properties79N/A
100 N/ARevision History78
(MASTER)99 (MASTER)
LVDS Interface Pull-downs77(MASTER)
98 (MASTER)M1 Specific Connectors76
(MASTER)97 (MASTER)
External Display Connector75(MASTER)
94 (MASTER)Internal Display Connectors74
(MASTER)93 (MASTER)
ATI M56 Video Interfaces73(MASTER)
91 (MASTER)ATI M56 GPIO/DVO/Misc72
(MASTER)90 (MASTER)
GDDR3 Frame Buffer B71(MASTER)
89 (MASTER)GDDR3 Frame Buffer A70
(MASTER)88 (MASTER)
GPU Straps69(MASTER)
87 (MASTER)ATI M56 Frame Buffer I/F68
(MASTER)86 (MASTER)
ATI M56 Core Power67(MASTER)
85 (MASTER)GPU (M56) Core Supplies66
(MASTER)84 (MASTER)
ATI M56 PCI-E65(MASTER)
82 (MASTER)PBus-In & Battery Connectors64
(MASTER)81 (MASTER)
Power Aliases63(MASTER)
80 (MASTER)3.3V G3Hot Supply & Power Control62
(MASTER)79 (MASTER)
3.3V / 1.05V Power Supplies61(MASTER)
78 (MASTER)1.8V Supply60
(MASTER)77 (MASTER)
2.5V & 1.2V Regulators59(MASTER)
76 (MASTER)5V / 1.5V Power Supply58
(MASTER)75 (MASTER)
IMVP6 CPU VCore Regulator57M38
67 11/16/2005TPM56
(MASTER)66 (MASTER)
Sudden Motion Sensor (SMS)55(MASTER)
65 (MASTER)Fan Connectors54
(MASTER)64 (MASTER)
ALS Support53M42
63 11/16/2005SPI BOOTROM52
(MASTER)62 (MASTER)
Current & Voltage Sensing51(MASTER)
61 (MASTER)Thermal Sensors50
M4260 07/20/2005
LPC+ Debug Connector49(MASTER)
59 (MASTER)SMC Support48
M3858 10/07/2005
SMC47(MASTER)
57 (MASTER)PCI-E Connections46
(MASTER)55 (MASTER)
Left I/O Board Connector45(MASTER)
52 (MASTER)External USB Connector44
(MASTER)49 (MASTER)
Internal USB Connections43
D051-7099
SCHEM,MLB,M1
1041
?D PRODUCTION RELEASED428208 03/04/06
Page Contents Sync(.csa) Date Date
Contents Sync(.csa)
Page
LAST_MODIFIED=Fri Mar 3 15:00:30 2006
TITLE=M1_MLBABBREV=DRAWING
(MASTER)46 (MASTER)
FireWire Ports4211 N/AN/ATable of Contents
1 PCB820-1881 CRITICALPCBF,MLB,M1
051-7099 1 SCH CRITICALSCHEM,MLB,M1
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
& REGULATOR
DDR2 VTT
P.28
Upper Connector
Lower ConnectorDDR2 SO-DIMM A
DDR2 SO-DIMM B
P.11
J2800
J2900
P.29 P.30-31
P.45
ConnectorAudio BoardLeft I/O &
DDR2 VREFBUFFER
P.32
P.57-64,66
SuppliesPower
Azalia (HD-Audio)
PCIe x1
PCIe x1
Connector
ITP700FLEXCPU Debug
479 BGA
CH.A
CH.B
FSB
P.7-9
NB1466UFCBGA
945GM
Core Duo(Yonah)
CPUTHERMAL
P.10
P.65-69,72-73
ATI M56P
GDDR3Frame Buffer128MB/256MB
P.70-71
GPUS-Video/Composite
Dual-Channel LVDS
Dual-Channel TMDS
PWM
DMI x4
P.12-20
SB USB
USB
609 BGA
P.21-26
ICH7-M
P.53,76ALS
Debug
P.49
LPC
Connector
Sensors
P.55
Analog
P.51
LPC 33MHZ
H8S/2116
SMC
SPI
P.47-48
BootROM
SMBus
USB
USB
SATA
USB
USB x2
P.52
P.27
SB SMBus
P.27
SMC SMBus
PATA66MHZ16BITS
P.64Connector
Battery SMBus
P.33-34
CK410 ClockController
P.74,77
P.75
P.74
P.43
P.43
ConnectorRight USB 2.0
TP ConnectorGeyser KB /
Connector ODD
Connector
ConnectorHDD/IR/BT
Camera
LCD Panel
CONNECTORINVERTER
w/TV-Out SupportDVI-I/DL Connector
SENSOR
Yukon PowerYukon Gig-EENET
PCIe x1
P.39
PCI
FW323-06 FireWireController
Controller
P.40
P.37
Port Power
P.41
FWConnector
Connector
1394a (FireWire)
RJ45 (Ethernet)
PCIe x16
P.56
TPM
SMS
FanConnectors
P.54
SMBus x5
PWM/Tach
TemperatureSensors
P.50
P.36
P.76
P.44
P.42
P.38
System Block Diagram
D
2 104
051-7099
SYNC_MASTER=N/A SYNC_DATE=N/A
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
5V/1.5V
PM_SLP_S3_L
U8500
NC
1.5V
PGOOD
(ISL6269)
S5
3.3V
ENABLE
PPVCORE_S0_CPU
1.05V
PP1V05_S0
PGOOD
1.05V
U7950
PPVCORE_S0_GPUS0
(ISL6269)
PGOOD
GPU VCore
ENABLE
NC
(LTC3412)
S3
PGOOD
1.2V
ENABLEU7750
1.2V
PP1V2_S3
2.5V
PP2V5_S0
2.5V
PP2V5_S3
(LTC3411)
2.5V
S3
PGOOD
ENABLEU7700
3.3V
PP3V3_S3
PP5V_S0
5.0V
PP5V_S3
PP1V5_S0
5.0V
PP5V_S5
SMC_PM_G2_ENABLE
NC
(LTC3728)
S5/S0
PGOOD
ENABLESU76005
V
1.5V PM_SLP_S3_L
SMC_PM_G2_ENABLE
PGOOD
VR_PWRGOOD_DELAY
"IMVP6"
S0
(ISL6262)
CPU VCore
ENABLES
IMVP_PWRGD_IN
IMVP_VR_ON
RSMRST_PWRGD
S0
IMVP_PWRGD_IN/ALL_SYS_PWRGD
PM_SLP_S3_L
PM_SLP_S4_LS5V
PM_SLP_S3_LS5V
PM_SLP_S4_LS5V
PM_SLP_S3_LS5V_L
ENABLE
ENABLE
J5500
Connector
Inverter
PP1V8_S3
1.8V
NC
1.8V
U7800
S3
ENABLE
(ISL6269)
PGOOD
PM_SLP_S3_L
U3100
0.9V (Vtt)
S0
(BD3533FVM)
PP0V9_S0
0.9V
Q4565
12.6V - 9V
PPBUS_S5_FWPORT
PP1V2_S0
1.2V
PM_SLP_S3_LS5V_L
PM_SLP_S3_LS5V_L
PP1V8_S0
1.8V
5.0V
U8000
3.425V
PP3V42_G3H
(LT3470)
G3Hot
3.425
ENABLE
12.6V - 9V
18.5V - 9V
PPDCIN_G3H
J5500
LIO Flex
Connector
PM_SLP_S4_L
3.3V
U7900
PPBUS_G3H
J8200
LIO Power
Connector
PM_SLP_S3_LS5V
3.3V
PP3V3_S0
Q3820
5V
PP5V_S0_IDE_ODD
ODD_PWR_EN_L (SB GPIO14)
PP3V3_S3AC
3.3V
Q4300
PM_SLP_S3BATT
NC
PM_SLP_S3BATT
PM_SLP_S3BATT
FWPWR_EN_L
U7530 PP3V3_S5
Q7610
Q7615
Q7720
Q7770
Q7845
Q7945
Q79471.1V - 0.95V
1.25V - 0.8V
(ISL6269)
Power Block DiagramSYNC_MASTER=N/A SYNC_DATE=N/A
D051-7099
3 104
TABLE_BOMGROUP_ITEM
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
TABLE_BOMGROUP_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD
BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
"Best" BOM
"Better" BOM
Bar Code Label / EEE #’s
M1,1.83GHZ,SAM128
M1,2.0GHZ,SAM256
Module Parts
Alternate Parts
BOMOPTION Groups
"CTO" BOM
M1,2.16GHZ,SAM256
150uF,6.3V,25MOHM,C2128S0061128S0081 ALL
330uF,2V,6MOHM,D2128S0095 ALL128S0060
330uF,2V,9MOHM,D2128S0060128S0094 ALL
128S0086 ALL 7mOhm alt for 8mOhm128S0077
4
D
BOM Configuration
051-7099
SYNC_MASTER=N/A SYNC_DATE=N/A
104
U2100IC,SB,652BGA343S0385 1 CRITICAL
341S1797 IC,EEPROM,SERIAL IIC,8KBIT,SO81 CRITICALU4102
338S0270 1 U4101IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO CRITICAL
IC,945GM,SOUTHBRIDGE338S0269 1 U1200 CRITICAL
U0700 CRITICAL1337S3267 IC,YDC,CO,2.0G,31W,667M,2M,479BGA CPU_2_0GHZ
U8900,U8950,U9000,U90504333S0354 CRITICAL VRAM_128_SAMSUNGIC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA
[EEE:VHV]1826-4393 LBL,P/N LABEL,PCB,28MM X 6 MM EEE_VHVCRITICAL
1 CRITICALU0700337S3282 IC,YDC,CO,1.83G,31W,667M,2M,479BGA CPU_1_83GHZ
M1_COMMON3 RTUSB_ESD,SMC_PRGRM,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU
GPU_MEM_256M,GPU_MEM_HYNIX,VRAM_256_HYNIXVRAM_HY256
VRAM_SAM256 GPU_MEM_256M,VRAM_256_SAMSUNG
[EEE:VHT] EEE_VHT826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL
M1_COMMON1 BOOTROM_DEVEL,ENET_LOM_DISABLE,ENETPWR_S3AC,GPU_BB_CTL,GPUTHM_A_GPU,HSTHMSNS_HAS
[EEE:VHU] CRITICAL1826-4393 LBL,P/N LABEL,PCB,28MM X 6 MM EEE_VHU
CRITICAL4 IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 VRAM_128_HYNIX333S0358
IC,PRGRM,SMC (NEW),M1 SMC_PRGRMCRITICAL1341S1875 U5800
VRAM_128_SAMSUNGVRAM_SAM128
M1_COMMON2 ITP,INVERTER_BUF,KBDLED_HAS,LPCPLUS,LVDS_PD,MEMVREF_S3,MEMVTT_EN_PU
M1_COMMON ALTERNATE,COMMON,M1_COMMON1,M1_COMMON2,M1_COMMON3
359S0101 IC,CY28445-5,CLOCK GEN,68PIN QFN U33011 CRITICAL
IC,FW32306,1394A LINK,BGA,129P338S0268 1 U4400 CRITICAL
IC,YDC,CO,2.16G,31W,667M,2M,479BGA U0700 CRITICAL1337S3268 CPU_2_16GHZ
630-7569 EEE_VHT,M1_COMMON,CPU_1_83GHZ,VRAM_SAM128PCBA,1.83GHZ,128VRAM_M1_MBPRO_15
CRITICAL4 IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA U8900,U8950,U9000,U9050 VRAM_256_HYNIX333S0351
630-7570 EEE_VHU,M1_COMMON,CPU_2_0GHZ,VRAM_SAM256PCBA,2.0GHZ,256VRAM_M1_MBPRO_15
630-7571 EEE_VHV,M1_COMMON,CPU_2_16GHZ,VRAM_SAM256PCBA,2.16GHZ,256VRAM_M1_MBPRO_15
341S1789 IC, TPM, 28-PIN TSSOP1 U6700 CRITICAL
338S0309 U84001 CRITICALIC,ATI,M56P,GRPHSCTRL,880BGA,LF
VRAM_HY128 GPU_MEM_HYNIX,VRAM_128_HYNIX
1 CRITICALU6301 BOOTROM_DEVELIC,EFI,BOOTROM DEVELOPMENT (NEW),M1341S1873
CRITICALIC,CPU VOLTAGE REGULATOR,IMVP,TWO PHASE1353S1235 U7530
IC,SMC,HS8/2116 SMC_BLANK338S0274 U58001 CRITICAL
4 U8900,U8950,U9000,U9050 CRITICAL333S0350 IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA VRAM_256_SAMSUNG
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Thermal Diode Connectors
opening for use as engineering probe point.
FUNC_TEST
NOTE: 10 additional GND test points arecalled out separately in these notes.
Request for at least 10 GND test points
Left I/O Power Connector
Left ALS Connector
Battery Digital Connector
Functional Test Points
8 TPs, 2 with each of above TP pairs
2 TPs per
Current Sense Calibration
Other Func Test Points
FUNC_TEST
FUNC_TEST
FUNC_TEST
Camera Connector
Left I/O Data Connector
Fan Connectors
LPC+ Debug Connector
FUNC_TEST
FUNC_TEST
FUNC_TEST FUNC_TEST
EXPOSED_VIA
Misc EXPOSED_VIA Nets
EXPOSED_VIA
EXPOSED_VIA property indicates that the netshould have a via with 10-mil soldermask
FUNC_TEST
FUNC_TEST property removedsince these test pointsare not on the proper sidefor Functional Test points.
FUNC_TEST
NO_TEST
NO_TEST EXPOSED_VIA
Power Supply NO_TESTs
CPU FSB NO_TESTs
Functional / ICT TestSYNC_DATE=N/ASYNC_MASTER=N/A
5 104
D051-7099
FSB_DINV_L<3..0>TRUE TRUETRUE FSB_DRDY_L
GPUBBP_ADJTRUE
GPUVCORE_COMPTRUE
TRUE FSB_DSTBN_L<3..0>TRUE
FSB_HIT_LTRUE
GPUVCORE_FSETTRUE
P3V42G3H_FBTRUE
FSB_DBSY_LTRUE
P1V5S0_RUNSSTRUE
P1V2S3_RUNSSTRUE
P1V8S3_COMPTRUE
P1V2S3_RTTRUE
P3V3S5_COMPTRUEP3V3S5_FSETTRUE
P2V5S3_SHDNRTTRUE
P5VS5_RUNSSTRUE
IMVP6_COMPTRUE
P1V05S0_FSETTRUE
IMVP6_RBIASTRUE
P2V5S3_MODETRUE
P1V8S3_FSETTRUE
P1V05S0_COMPTRUE
TRUE =PP3V3_S5_LPCPLUS
ACZ_SDATAOUTTRUE
TRUE SMC_BATT_CHG_ENTRUE SMC_BC_ACOK
=PP1V5_S0_LIOTRUETRUE =PPDCIN_G3H_LIO
=PP5V_S5_LIOTRUE
TRUE PP5V_S0_AUDIO
TRUE PCIE_CLK100M_EXCARD_N
=PCIE_EXCARD_D2R_NTRUE
TRUE =SMBUS_BATT_SCLTRUE SMC_BS_ALRT_L
TRUE =SMBUS_BATT_SDA
TRUE SMC_ADAPTER_EN
=PCIE_EXCARD_D2R_PTRUE
=PCIE_EXCARD_R2D_PTRUE
TRUE =USB2_EXCARD_NTRUE =USB2_EXCARD_P
TRUE =USB2_LT_NTRUE =USB2_LT_P
TRUE ACZ_SYNC
TRUE SMC_EXCARD_PWR_ENLIO_PLT_RESET_LTRUE
TRUE SMC_EXCARD_CPTRUE MINI_CLKREQ_L
TRUE SMC_BATT_TRICKLE_EN_LTRUE LIO_P3V3S3_EN
LIO_DCIN_ISENSETRUE
TRUE LIO_BATT_ISENSETRUE SMC_SYS_ISET
SMC_TDOTRUETRUE SMC_MD1
TRUE SMC_TRST_L
TRUE PP5V_S0_AUDIO_PWRTRUE =PP3V42_G3H_LIO
GND_AUDIO_PWRTRUEGND_AUDIOTRUE
TRUE SMC_RX_L
TRUE SMC_RST_L
TRUE SMC_TX_L
TRUE LPC_AD<1>
ACZ_SDATAIN<0>TRUE
TRUE =PP5V_S0_LPCPLUS
TRUE DEBUG_RST_L
TRUE BOOT_LPC_SPI_LTRUE PM_CLKRUN_LTRUE LPC_FRAME_L
TRUE LPC_AD<0>
TRUE SMC_TMSACZ_BITCLKTRUE
TRUE PCIE_CLK100M_EXCARD_P
FSB_A_L<31..3>TRUETRUE FSB_ADS_LTRUE FSB_ADSTB_L<1..0>TRUE
FSB_D_L<63..0>TRUEFSB_BREQ0_LTRUEFSB_BNR_LTRUE
FSB_REQ_L<4..0>TRUEFSB_LOCK_LTRUEFSB_HITM_LTRUE
FSB_DSTBP_L<3..0>TRUE TRUE
DMI_N2S_N<1..0>TRUEDMI_N2S_P<1..0>TRUE
SB_CLK100M_SATA_NTRUESB_CLK100M_SATA_PTRUE
FAN_RT_TACH
FAN_LT_PWMFAN_LT_TACH
FAN_RT_PWM
=PP5V_S0_FAN_LT
LPC_AD<3>TRUE
TRUE PCI_CLK_PORT80_LPCTRUE LPC_AD<2>
TRUE INT_SERIRQ
TRUE SMC_TDI
TRUE =PCIE_EXCARD_R2D_N
TRUE SV_SET_UP
TRUE SMC_NMI
TRUE SMC_TCK
TRUE PM_SUS_STAT_L
TRUE FWH_INIT_L
TRUE =SMBUS_ATS_SDA
=PP3V3_S3_LTALSTRUEALS_GAINTRUE
TRUE LTALS_OUTTRUE GND
RSFSTHMSNS_D_PTRUERSFSTHMSNS_D_NTRUE
TRUE =USB2_CAMERA_P
TRUE GNDTRUE =SMBUS_ATS_SCL
TRUE PM_SYSRST_LTRUE SMC_ONOFF_L
TRUE =PP1V05_S0_REG
TRUE GND
TRUE GND_BATT
LTUSB_OC_LTRUE
ACZ_RST_LTRUEEXCARD_OC_LTRUE
TRUE SMC_BATT_ISET
TRUE LIO_P3V3S0_EN_L
TRUE SYS_ONEWIRE
TRUE =USB2_CAMERA_NTRUE =PP5V_S3_CAMERA TRUE =PCIE_MINI_R2D_N
=PCIE_MINI_R2D_PTRUE
=PCIE_MINI_D2R_PTRUE=PCIE_MINI_D2R_NTRUE
PCIE_CLK100M_MINI_PTRUE
=SMBUS_LIO_SMC_SCLTRUEPCIE_CLK100M_MINI_NTRUE
=SMBUS_LIO_SMC_SDATRUE=SMBUS_LIO_SB_SCLTRUE=SMBUS_LIO_SB_SDATRUEPCIE_WAKE_LTRUE
TRUE GNDTRUE =PPBUS_G3H_LIO_CONN
TRUE HSTHMSNS_DX_NHSTHMSNS_DX_PTRUE
TRUE ISENSE_CAL_EN
TRUE EXCARD_CLKREQ_L
TRUE PPVCORE_S0_CPUTRUE PPVCORE_S0_GPU
=PP1V5_S0_REGTRUE=PP1V8_S3_REGTRUE
=PP5V_S0_ISENSECALTRUE
56
56
48
56
49
56
56
56
56
56
49
51
79
79
79
79
79
79
48
48
64
47
79
48
48
49
49
49
49
49
79 49
47
49
49
49
79
79
79
79
79
79
79
79
79
79
79
49
49
49
49
49
48
49
76
47
48
63
79
48
48
45
63
12
12
12
12
12
62
59
62
63
45
47
47
63
63
63
45
46
64
48
64
45
46
46
45
45
45
45
45
47
45
47
45
47
62
51
51
47
48
49
49
63
48
48
48
47
45
63
49
47
40
47
47
48
45
45
12
12
12
12
12
12
12
12
12
12
22
22
34
34
63
47
49
47
47
48
46
49
49
48
47
48
43
76
47
76
43
43
26
47
61
45
45
45
47
62
47
43
63 46
46
46
46
45
45
45
45
45
45
37
64
45
63
60
7
7
66
66
7
7
66
62
7
58
39
60
59
61
61
59
58
57
61
57
59
60
61
49
21
45
45
45
45
45
45
34
45
27
47
27
41
45
45
6
6
6
6
21
45
26
45
34
45
45
45
45
45
47
47
47
45
45
45
45
47
47
47
21
21
49
26
22
23
21
21
47
21
34
7
7
7
7
7
7
7
7
7
7
14
14
21
21
54
54
54
54
54
21
34
21
23
47
45
23
47
47
23
21
27
63
6
53
50
50
6
27
23
43
51
64
6
21
6
45
45
45
6
43 45
45
45
45
34
27
34
27
27
27
23
63
50
50
34
63
63
58
51
IN OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
"ENET_LOM_DISABLE" are mutually-exclusive.NOTE: BOM options "USB_G_OC_PU" and
Ethernet Power Management Support
NOTE: NB_CFG<13..12> require test access
Trace deleted to make room for other diffpairs over RAM connector.
USB Port "H" = Reserved (PCI-E Mini Card)
USB Port "E" = ExpressCard
USB Port "B" = Trackpad (Geyser)
USB Port "A" (Debug Port) = Right USB 2.0 Port
USB Port "G" = Bluetooth (M13P)
USB Port "C" = Left USB 2.0 Port
USB Port "F" = IR Receiver
USB Port "D" = Camera
Chassis connection to be made at the mounting hole east of the LVDS connector
Chassis connection to be made at the mounting hole northwest of the DVI connector
Chassis connection to be made at the mounting hole southwest of the USB connector
HOLE-VIA-P5RP25ZT0600
1
HOLE-VIA-P5RP25ZT0601
1
HOLE-VIA-P5RP25ZT0602
1
SHLD-SM-LFOG-503040SH0600
1
2
3
5%1/16WMF-LF402
ENET_LOM_DISABLE
0R06001 2
SYNC_DATE=N/ASYNC_MASTER=N/A
6 104
D051-7099
Signal Aliases
=GND_CHASSIS_DVI5=GND_CHASSIS_DVI3
GND_CHASSIS_DVI_BOT
MAKE_BASE=TRUEVOLTAGE=0V
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm =GND_CHASSIS_DVI1
=GND_CHASSIS_DVI2=GND_CHASSIS_DVI4
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=0VMAKE_BASE=TRUE
GND_CHASSIS_DVI_TOPMIN_NECK_WIDTH=0.25 mm
=GND_CHASSIS_ENET=GND_CHASSIS_FW_EMI=GND_CHASSIS_FW_PORT1=GND_CHASSIS_RTUSB
MAKE_BASE=TRUELTUSB_OC_L
=USB_IR_P USB_F_P
=USB2_LT_N
USB_E_P=USB2_EXCARD_P
=USB2_EXCARD_N
MAKE_BASE=TRUEUSB_BT_N
USB_BT_PMAKE_BASE=TRUE
MAKE_BASE=TRUEUSB2_EXCARD_P
=USB2_CAMERA_N USB2_CAMERA_NMAKE_BASE=TRUE
MAKE_BASE=TRUEUSB2_CAMERA_P
USB_G_P
USB_G_N
USB_E_N
MAKE_BASE=TRUEEXCARD_OC_L USB_E_OC_L
USB_D_OC_L
USB_D_N
=USB2_LT_P
=USB_TRACKPAD_NMAKE_BASE=TRUEUSB_TRACKPAD_N
MAKE_BASE=TRUEUSB_TRACKPAD_P
=RTUSB_OC_L RTUSB_OC_LMAKE_BASE=TRUE
USB_C_N
USB_C_OC_L
USB_C_P
MAKE_BASE=TRUEUNUSED_USB_B_OC_L USB_B_OC_L
USB_B_N
USB_B_P
USB_A_OC_L
USB_A_N
USB_A_P
=USB2_RT_N
=USB2_RT_P USB2_RT_PMAKE_BASE=TRUE
MAKE_BASE=TRUEUSB2_RT_N
=GND_CHASSIS_LCD1
=GND_CHASSIS_INVERTER
=GND_CHASSIS_LCD4=GND_CHASSIS_LCD3
GND_CHASSIS_LVDS
MAKE_BASE=TRUEVOLTAGE=0V
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
NC_CPU_A32_LMAKE_BASE=TRUENO_TEST=TRUENC_CPU_A33_LMAKE_BASE=TRUENO_TEST=TRUENC_CPU_A34_LMAKE_BASE=TRUENO_TEST=TRUENC_CPU_A35_LMAKE_BASE=TRUENO_TEST=TRUE
NC_CPU_A37_LMAKE_BASE=TRUENO_TEST=TRUENC_CPU_A38_LMAKE_BASE=TRUENO_TEST=TRUENC_CPU_A39_LMAKE_BASE=TRUENO_TEST=TRUE
NC_CPU_HFPLLMAKE_BASE=TRUENO_TEST=TRUENC_CPU_SPARE0MAKE_BASE=TRUENO_TEST=TRUE
NC_CPU_SPARE2MAKE_BASE=TRUENO_TEST=TRUE
NC_CPU_SPARE1NO_TEST=TRUEMAKE_BASE=TRUE
NC_CPU_SPARE4NO_TEST=TRUEMAKE_BASE=TRUE
TP_CPU_A32_L
TP_CPU_A33_L
TP_CPU_A34_L
TP_CPU_A35_L
TP_CPU_A37_L
TP_CPU_A36_L
TP_CPU_A38_L
TP_CPU_A39_L
TP_CPU_APM1_L
TP_CPU_EXTBREF
TP_CPU_SPARE0
TP_CPU_SPARE2
TP_CPU_SPARE1
TP_CPU_SPARE4
MAKE_BASE=TRUEUNUSED_USB_D_OC_L
USB_F_N
=USB_BT_N
=USB_IR_N
USB_IR_PMAKE_BASE=TRUEUSB_IR_N
MAKE_BASE=TRUE
USB_D_P
=USB_TRACKPAD_P
USB2_LT_PMAKE_BASE=TRUE
MAKE_BASE=TRUEUSB2_LT_N
NC_CPU_EXTBREFMAKE_BASE=TRUENO_TEST=TRUE
TP_CPU_HFPLL
NC_CPU_APM0_LNO_TEST=TRUEMAKE_BASE=TRUE
NC_CPU_APM1_LMAKE_BASE=TRUENO_TEST=TRUE
NC_CPU_A36_LMAKE_BASE=TRUENO_TEST=TRUE
GND_CHASSIS_INVERTER
MAKE_BASE=TRUEVOLTAGE=0V
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
=GND_CHASSIS_LCD2
=USB2_CAMERA_P
USB2_EXCARD_NMAKE_BASE=TRUE
USB_H_P
USB_H_N
TP_USB2_HPMAKE_BASE=TRUETP_USB2_HN
MAKE_BASE=TRUE
TP_CPU_APM0_L
=USB_BT_P
MEM_A_A<15..14>NO_TEST=TRUEMAKE_BASE=TRUENC_MEM_A_A<15..14>
MEM_B_A<15..14>NO_TEST=TRUEMAKE_BASE=TRUENC_MEM_B_A<15..14>
NB_CFG<4..3>MAKE_BASE=TRUETP_NB_CFG<4..3>
NB_CFG<6>MAKE_BASE=TRUETP_NB_CFG<6>
NB_CFG<8>MAKE_BASE=TRUETP_NB_CFG<8>
NB_CFG<11..10>MAKE_BASE=TRUETP_NB_CFG<11..10>
NB_CFG<15..14>MAKE_BASE=TRUETP_NB_CFG<15..14>
NB_CFG<17>MAKE_BASE=TRUETP_NB_CFG<17>
NB_CFG<13..12>MAKE_BASE=TRUETP_NB_CFG<13..12>
SUS_CLK_SBMAKE_BASE=TRUETP_SB_SUS_CLK
TP_SB_XOR_T5MAKE_BASE=TRUENO_TEST=TRUE
NC_SB_XOR_T5
TP_SB_XOR_V3MAKE_BASE=TRUENO_TEST=TRUE
NC_SB_XOR_V3
TP_SB_XOR_U5MAKE_BASE=TRUENO_TEST=TRUE
NC_SB_XOR_U5
TP_SB_XOR_W3MAKE_BASE=TRUENO_TEST=TRUE
NC_SB_XOR_W3
TP_SB_XOR_V4MAKE_BASE=TRUENO_TEST=TRUE
NC_SB_XOR_V4
SMC_RSTGATE_LMAKE_BASE=TRUETP_SMC_RSTGATE_L
=RTALS_GAINMAKE_BASE=TRUEALS_GAIN
ENET_CTRL12MAKE_BASE=TRUENO_TEST=TRUE
NC_ENET_CTRL12
ENET_CTRL25MAKE_BASE=TRUENO_TEST=TRUE
NC_ENET_CTRL25
ENET_LOM_DIS_LSB_GPIO30
48
76
45
45
45
45
43
45
45
43
47
75
75
75
75
75
38
42
42
44
5
76 22
5
22 5
5
5
22
22
22
5 22
22
22
5
43
44
22
22
22
22
22
22
22
22
22
44
44
74
74
74
74
7
7
7
7
7
7
7
7
7
7
7
7
7
7
22
76
76
22
43
7
74
5
22
22
7
76
28
29
14
14
14
14
14
14
14
23
21
21
21
21
21
47
53 5
37
37
37 22
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IN
IN
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
A7*
RSVD14
RSVD15
BCLK1
BCLK0
RSVD20
RSVD17
RSVD18
RSVD19
RSVD16
RSVD13
RSVD12
THERMTRIP*
THERMDC
THERMDA
PROCHOT*
DBR*
TRST*
TMS
TDO
TDI
TCK
PREQ*
PRDY*
BPM3*
BPM1*
BPM2*
BPM0*
HITM*
HIT*
TRDY*
RS2*
RS1*
RS0*
RESET*
LOCK*
INIT*
IERR*
BR0*
DBSY*
DRDY*
DEFER*
BPRI*
BNR*
ADS*
RSVD11
RSVD6
RSVD7
RSVD8
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD9
RSVD10
SMI*
LINT0
LINT1
STPCLK*
IGNNE*
FERR*
A20M*
ADSTB1*
A30*
A31*
A27*
A28*
A29*
A26*
A25*
A24*
A22*
A23*
A21*
A20*
A19*
A18*
A17*
REQ4*
REQ3*
REQ1*
REQ0*
REQ2*
ADSTB0*
A14*
A15*
A16*
A13*
A12*
A11*
A10*
A9*
A8*
A6*
A5*
A4*
A3*
(1 OF 4)
THERM
HCLK
RESERVED
ADDR GROUP1
ADDR GROUP0
CONTROL
XDP/ITP SIGNALS
PSI*
SLP*
PWRGOOD
DPRSTP*
DPSLP*
DPWR*
COMP2
COMP3
COMP1
COMP0
DSTBP3*
DSTBN3*
DINV3*
D63*
D62*
D61*
D60*
D59*
D58*
D57*
D56*
D55*
D54*
D52*
D53*
D51*
D50*
D49*
D48*
DINV2*
DSTBN2*
D47*
DSTBP2*
D45*
D46*
D44*
D43*
D42*
D41*
D40*
D39*
D38*
D37*
D36*
D35*
D34*
D33*
D32*
BSEL2
DSTBN1*
BSEL0
BSEL1
TEST2
TEST1
DINV1*
DSTBP1*
D31*
D30*
D29*
D26*
D27*
D28*
D24*
D25*
D23*
D21*
D22*
D20*
D19*
D18*
D16*
D17*
DINV0*
DSTBP0*
DSTBN0*
D15*
D14*
D13*
D12*
D11*
D10*
D9*
D8*
D7*
D6*
D5*
D4*
D3*
D2*
D1*
D0*
GTLREF
NC
(2 OF 4)
MISC
DATA GRP0
DATA GRP2
DATA GRP1
DATA GRP3
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
0.1" AWAY
ROUTE TO TP VIA ANDSPARE[7-0],HFPLL:
STUB)
PM_THRMTRIP#SHOULD CONNECT TO
CPU_PROCHOT_L TO SMC
COMP1,3 CONNECT WITH ZO=55OHM, MAKE
LAYOUT NOTE:COMP0,2 CONNECT WITH ZO=27.4OHM, MAKETRACE LENGTH SHORTER THAN 0.5".
TRACE LENGTH SHORTER THAN 0.5".
ICH7-M AND GMCH
LAYOUT NOTE: 0.5" MAX LENGTH
PLACE TESTPOINT ONFSB_IERR_L WITH A GND
PLACE GND VIA W/IN 1000 MILS
TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50
CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9
WITHOUT T-ING (NO
AND CPU VR TO INFORMCPU IS HOT
1%54.9MF-LF4021/16W
R07021
2
681/16W5%
402MF-LF
R07041
2
1KMF-LF402
1%1/16W
R07051
2
2.0KMF-LF402
1%1/16W
R07061
21%402
54.9R07191 2
27.4R07181 2
1% 402
54.9R07171 2
27.4402
R07161 2
NOSTUFF
402
0R07301 2
1/16W5%
402MF-LF
1K
NOSTUFFR07071
2
511/16W5%
402MF-LF
R07121
2
402MF-LF1/16W1%54.9R07031
2
1%402
54.9R07201 2
54.9
4021%
R07211 2
1%402
54.9R07221 2
OMIT
CPUYONAH
BGA
U0700
N3P5P2L1P4P1R1
Y2U5R3W6
A6
U4Y5U2R4T5T3W3W5Y4
J4
W2Y1
L4M3K5M1N2J1
H1
L2
V4
A22A21
E2
AD4AD3AD1AC4
G5
F1
C20
E1
H5F21
A5
G6E4
D20
C4
B3
C6B4
H4
AC2AC1
D21
K3H2K2J3L5
B1F3F4G3
AA1
C3
B25
T22
D2F6D3C1AF1D22C23
AA4
C24
AB2AA3M4N5T2V3B2
A3
D5
AC5AA6AB3
A24A25
C7
AB5
G2
AB6
OMIT
BGA
YONAHCPU
U0700
B22B23C21
R26U26U1V1
E22F24
J24J23H26F26K22H25
N22K25P26R23
E26
L25L22L23M23P25P22P23T24R24L26
H22
T25N24
AA23AB24V24V26W25U23U25U22
F23
AB25W22Y23AA26Y26Y22AC26AA24
AC22AC23
G25
AB22AA21AB21AC25AD20AE22AF23AD24AE21AD21
E25
AE25AF25AF22AF26
E23K24G24
J26
M26
V23
AC20
E5B5D24
H23
M24
W24
AD23
G22
N25
Y25
AE24
AD26A2
AE6
D6D7
C26
D25
CPU 1 OF 2-FSBSYNC_MASTER=M42
7
D051-7099
104
SYNC_DATE=11/16/2005
FSB_RS_L<0>FSB_RS_L<1>
XDP_BPM_L<5>
FSB_HITM_LFSB_HIT_L
FSB_RS_L<2>FSB_TRDY_L =PP1V05_S0_CPU
XDP_BPM_L<1>
FSB_DBSY_L
=PP1V05_S0_CPU
=PP1V05_S0_CPU
=PP1V05_S0_CPU
XDP_TMS
XDP_TDI
XDP_TCK
FSB_A_L<3>FSB_A_L<4>FSB_A_L<5>FSB_A_L<6>
FSB_A_L<8>FSB_A_L<9>FSB_A_L<10>FSB_A_L<11>FSB_A_L<12>FSB_A_L<13>
FSB_A_L<16>FSB_A_L<15>FSB_A_L<14>
FSB_ADSTB_L<0>
FSB_REQ_L<2>
FSB_REQ_L<0>FSB_REQ_L<1>
FSB_REQ_L<3>FSB_REQ_L<4>FSB_A_L<17>FSB_A_L<18>FSB_A_L<19>FSB_A_L<20>FSB_A_L<21>
FSB_A_L<23>FSB_A_L<22>
FSB_A_L<24>FSB_A_L<25>FSB_A_L<26>
FSB_A_L<29>FSB_A_L<28>FSB_A_L<27>
FSB_A_L<31>FSB_A_L<30>
FSB_ADSTB_L<1>CPU_A20M_LCPU_FERR_LCPU_IGNNE_LCPU_STPCLK_L
CPU_NMICPU_INTR
CPU_SMI_L
TP_CPU_APM1_LTP_CPU_APM0_L
TP_CPU_A36_LTP_CPU_A35_LTP_CPU_A34_LTP_CPU_A33_LTP_CPU_A32_L
TP_CPU_A39_LTP_CPU_A38_LTP_CPU_A37_L
TP_CPU_HFPLL
FSB_DEFER_LFSB_DRDY_L
FSB_BREQ0_LFSB_IERR_LCPU_INIT_LFSB_LOCK_LFSB_CPURST_L
XDP_BPM_L<0>
XDP_BPM_L<2>XDP_BPM_L<3>XDP_BPM_L<4>
XDP_TCKXDP_TDIXDP_TDOXDP_TMSXDP_TRST_LXDP_DBRESET_L
CPU_PROCHOT_LCPU_THERMD_PCPU_THERMD_NPM_THRMTRIP_L
TP_CPU_EXTBREF
TP_CPU_SPARE0
TP_CPU_SPARE3
TP_CPU_SPARE6TP_CPU_SPARE5TP_CPU_SPARE4
TP_CPU_SPARE7
FSB_CLK_CPU_PFSB_CLK_CPU_N
TP_CPU_SPARE2TP_CPU_SPARE1
FSB_A_L<7>
CPU_GTLREF
FSB_D_L<0>FSB_D_L<1>FSB_D_L<2>FSB_D_L<3>FSB_D_L<4>FSB_D_L<5>FSB_D_L<6>FSB_D_L<7>FSB_D_L<8>FSB_D_L<9>FSB_D_L<10>FSB_D_L<11>FSB_D_L<12>FSB_D_L<13>FSB_D_L<14>FSB_D_L<15>FSB_DSTBN_L<0>FSB_DSTBP_L<0>FSB_DINV_L<0>
FSB_D_L<17>FSB_D_L<16>
FSB_D_L<18>FSB_D_L<19>FSB_D_L<20>
FSB_D_L<22>FSB_D_L<21>
FSB_D_L<23>
FSB_D_L<25>FSB_D_L<24>
FSB_D_L<28>FSB_D_L<27>FSB_D_L<26>
FSB_D_L<29>FSB_D_L<30>FSB_D_L<31>
FSB_DSTBP_L<1>FSB_DINV_L<1>
CPU_TEST1CPU_TEST2
CPU_BSEL<1>CPU_BSEL<0>
FSB_DSTBN_L<1>
CPU_BSEL<2>
FSB_D_L<32>FSB_D_L<33>FSB_D_L<34>FSB_D_L<35>FSB_D_L<36>FSB_D_L<37>FSB_D_L<38>FSB_D_L<39>FSB_D_L<40>FSB_D_L<41>FSB_D_L<42>FSB_D_L<43>FSB_D_L<44>
FSB_D_L<46>FSB_D_L<45>
FSB_DSTBP_L<2>
FSB_D_L<47>FSB_DSTBN_L<2>
FSB_DINV_L<2>FSB_D_L<48>FSB_D_L<49>FSB_D_L<50>FSB_D_L<51>
FSB_D_L<53>FSB_D_L<52>
FSB_D_L<54>FSB_D_L<55>FSB_D_L<56>FSB_D_L<57>FSB_D_L<58>FSB_D_L<59>FSB_D_L<60>FSB_D_L<61>FSB_D_L<62>FSB_D_L<63>
FSB_DINV_L<3>
FSB_DSTBN_L<3>FSB_DSTBP_L<3>
CPU_COMP<0>CPU_COMP<1>
CPU_COMP<3>CPU_COMP<2>
FSB_DPWR_LCPU_DPSLP_LCPU_DPRSTP_L
CPU_PWRGDFSB_SLPCPU_LCPU_PSI_L
FSB_ADS_LFSB_BNR_LFSB_BPRI_L
63
63
63
63
11
11
11
11
79
79
9
79
9
9
9 79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
48
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
12
12
79
79 8
79
12
8
8
8
11
11
11
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
79
79
79
79
79
79
79
12
12
79
12
12
79
79
79
79
11
11
11
26
21
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
79
79
57
79
12
12
79
12
12
11
5
5
12
12 7
11
5
7
7
7
7
7
7
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
21
21
21
21
21
21
21
6
6
6
6
6
6
6
6
6
6
6
12
5
5
79
21
5
11
11
11
11
11
7
7
11
7
11
11
48
10
10
14
6
6
6
34
34
6
6
5
79
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
34
34
5
34
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
79
79
79
79
12
21
21
21
12
57
5
5
12
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
VSS_82
VSS_83
VSS_84
VSS_85
VSS_87
VSS_86
VSS_88
VSS_89
VSS_90
VSS_92
VSS_91
VSS_93
VSS_94
VSS_95
VSS_97
VSS_96
VSS_100
VSS_98
VSS_99
VSS_102
VSS_101
VSS_105
VSS_103
VSS_104
VSS_106
VSS_107
VSS_110
VSS_109
VSS_108
VSS_111
VSS_112
VSS_115
VSS_114
VSS_113
VSS_116
VSS_117
VSS_118
VSS_120
VSS_119
VSS_123
VSS_121
VSS_122
VSS_124
VSS_125
VSS_128
VSS_126
VSS_127
VSS_129
VSS_130
VSS_133
VSS_131
VSS_132
VSS_134
VSS_135
VSS_138
VSS_136
VSS_137
VSS_139
VSS_140
VSS_141
VSS_143
VSS_142
VSS_146
VSS_144
VSS_145
VSS_147
VSS_148
VSS_151
VSS_150
VSS_149
VSS_152
VSS_153
VSS_156
VSS_155
VSS_154
VSS_157
VSS_158
VSS_159
VSS_161
VSS_160
VSS_162
VSS_1
VSS_2
VSS_3
VSS_5
VSS_4
VSS_6
VSS_7
VSS_8
VSS_10
VSS_9
VSS_11
VSS_12
VSS_15
VSS_13
VSS_14
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_23
VSS_22
VSS_21
VSS_24
VSS_25
VSS_28
VSS_27
VSS_26
VSS_29
VSS_30
VSS_33
VSS_32
VSS_31
VSS_34
VSS_35
VSS_38
VSS_37
VSS_36
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_46
VSS_44
VSS_45
VSS_47
VSS_48
VSS_51
VSS_49
VSS_50
VSS_52
VSS_53
VSS_56
VSS_54
VSS_55
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_63
VSS_62
VSS_64
VSS_65
VSS_66
VSS_69
VSS_68
VSS_67
VSS_70
VSS_71
VSS_74
VSS_73
VSS_72
VSS_75
VSS_76
VSS_79
VSS_78
VSS_77
VSS_80
VSS_81
(4 OF 4)
VCC_67
VCC_64
VCC_66
VCC_65
VCC_63
VCC_62
VCC_61
VCC_59
VCC_60
VCC_58
VCC_57
VCC_56
VCC_54
VCC_55
VCC_53
VCC_51
VCC_52
VCC_49
VCC_50
VCC_48
VCC_47
VCC_46
VCC_44
VCC_45
VCC_43
VCC_41
VCC_42
VCC_40
VCC_39
VCC_38
VCC_36
VCC_37
VCC_33
VCC_35
VCC_34
VCC_31
VCC_32
VCC_29
VCC_30
VCC_28
VCC_26
VCC_27
VCC_23
VCC_25
VCC_24
VCC_22
VCC_21
VCC_20
VCC_18
VCC_19
VCC_17
VCC_16
VCC_15
VCC_13
VCC_14
VCC_12
VCC_10
VCC_11
VCC_8
VCC_9
VCC_7
VCC_6
VCC_5
VCC_3
VCC_4
VCC_2
VCC_1 VCC_68
VCC_69
VCC_71
VCC_70
VCC_72
VCC_74
VCC_76
VCC_75
VCC_78
VCC_77
VCC_79
VCC_81
VCC_80
VCC_84
VCC_82
VCC_83
VCC_86
VCC_85
VCC_87
VCC_89
VCC_88
VCC_90
VCC_91
VCC_92
VCC_94
VCC_93
VCC_95
VCC_96
VCC_97
VCC_99
VCC_98
VCC_100
VCCP_1
VCCP_2
VCCP_3
VCCP_4
VCCP_5
VCCP_6
VCCP_7
VCCP_9
VCCP_8
VCCP_11
VCCP_10
VCCP_12
VCCP_13
VCCP_14
VCCP_16
VCCP_15
VCCA
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VSSSENSE
VCCSENSE
VCC_73(3 OF 4)
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
VCCA=1.5 ONLY
LAYOUT NOTE: CONNECT R0803
PULL-DOWNIF NO USE, NEED PULL-UP ORVID FOR CPU POWER SUPPLY
TRANSMISSION LINERESISTORS TERMINATE THE 55 OHM
LAYOUT NOTE:
(CPU CORE POWER)
(CPU IO POWER 1.05V)
STUB.
LAYOUT NOTE:VCCSENSE AND VSSSENSE LINESSHOULD BE OF EQUAL LENGTH
LOCATION WHERE THE TWO 54.9 OHMBETWEEN VCCSENSE AND VSSSENSE AT THETO CONNECT A DIFFERENCTIAL PROBEPROVIDE A TEST POINT (WITH NO STUB)
LAYOUT NOTE:
TO TP_VSSSENSE WITH NO
(CPU INTERNAL PLL POWER 1.5V)
ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.CPU_VCCSENSE_P/CPU_VCCSENSE_N USE
79 9
79 9
79 9
79 9
79 9
79 9
1/16W1%
402MF-LF
100R08031
2
79 9
79 57
79 57
100MF-LF402
1%1/16W
R08021
2
OMIT
BGA
YONAHCPU
U0700A4
B8
V25W1W4W23W26Y3Y6Y21Y24AA2
B11
AA5AA8AA11AA14AA16AA19AA22AA25AB1AB4
B13
AB8AB11AB13AB16AB19AB23AB26AC3AC6AC8
B16
AC11AC14AC16AC19AC21AC24AD2AD5AD8AD11
B19
AD13AD16AD19AD22AD25AE1AE4AE8AE11AE14
B21
AE16AE19AE23AE26AF3AF6AF8AF11AF13AF16
B24
AF19AF21AF24
C5C8
C11
A8
C14C16C19C2
C22C25D1D4D8
D11
A11
D13D16D19D23D26E3E6E8
E11E14
A14
E16E19E21E24F5F8
F11F13F16F19
A16
F2F22F25G4G1
G23G26H3H6
H21
A19
H24J2J5
J22J25K1K4
K23K26L3
A23
L6L21L24M2M5
M22M25N1N4
N23
A26
N26P3
P6P21P24R2R5R22R25T1
B6 T4T23T26U3U6U21U24V2V5V22
OMIT
BGA
YONAHCPU
U0700A7
B7
AF20
B9B10B12B14B15B17B18B20C9
A9
C10C12C13C15C17C18D9
D10D12D14
A10
D15D17D18E7E9
E10E12E13E15E17
A12
E18E20F7F9
F10F12F14F15F17F18
A13
F20AA7AA9
AA10AA12AA13AA15AA17AA18AA20
A15
AB9AC10AB10AB12AB14AB15AB17AB18
AB20AB7
A17
AC7AC9AC12AC13AC15AC17AC18AD7AD9AD10
A18
AD12AD14AD15AD17AD18AE9AE10AE12AE13AE15
A20
AE17AE18AE20AF9AF10AF12AF14AF15AF17AF18
B26
V6
N6R21R6T21T6V21W21
G21J6K6M6J21K21M21N21
AF7
AD6AF5AE5AF4AE3AF2AE2
AE7
CPU 2 OF 2-PWR/GNDSYNC_MASTER=M42
051-7099 D
8 104
SYNC_DATE=11/16/2005
=PPVCORE_S0_CPU
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VID<6>CPU_VID<5>CPU_VID<4>CPU_VID<3>CPU_VID<2>CPU_VID<1>CPU_VID<0>
=PP1V5_S0_CPU
=PP1V05_S0_CPU
=PPVCORE_S0_CPU
63
63
63
51
11
51
9
9
9
8
7
8
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
CPU VCORE HF AND BULK DECOUPLING
VCCA (CPU AVdd) Decoupling
NOTE: This cap is shared
VCCP (CPU I/O) Decoupling
Will probably be removed before productionResistors to allow for override of CPU VID
CPU VCORE VID Connections4x 470uF. 20x 22uF 0805
1x 10uF, 1x 0.01uF
between CPU and NB
1x 470uF, 6x 0.1uF 0402
22UF
805CERM
20%6.3V
C09061
2805
22UF
CERM
20%6.3V
C09041
2
805
22UF
CERM
20%6.3V
C09161
2805
22UF
CERM
20%6.3V
C09141
2
805
22UF
CERM
20%6.3V
C09081
2805
22UF
CERM
20%6.3V
C09031
2805
22UF
CERM
20%6.3V
C09071
2805
22UF
CERM
20%6.3V
C09021
2
22UF
805CERM
20%6.3V
C09011
2
22UF
805CERM
20%6.3V
C09131
2
22UF
CERM
20%6.3V
805
C09121
2805
22UF
CERM
20%6.3V
C09111
2805
22UF
CERM
20%6.3V
C09191
2
805
22UF
CERM
20%6.3V
C09001
2
805
22UF
CERM
20%6.3V
C09101
2
10V20%
402CERM
0.1UFC09361
220%
2.5VTANTD2T
CRITICAL
470uFC0935 1
2 3
805
22UF
CERM
20%6.3V
C09051
2805
22UF
CERM
20%6.3V
C09091
2
805
6.3V
22UF
CERM
20%
C09151
2805
22UF
CERM
20%6.3V
C09171
2
10V20%
402CERM
0.1UFC09371
2 10V20%
402CERM
0.1UFC09381
2 10V20%
402CERM
0.1UFC09391
2 10V20%
402CERM
0.1UFC09401
2 10V20%
402CERM
0.1UFC09411
2
805
6.3V20%
CERM
22UFC09181
2
D2T
CRITICAL
2.5V20%470uF-8MOHM
POLY
C09501
23
D2T
CRITICAL
2.5V20%
POLY
470uF-8MOHMC09521
23
D2T
CRITICAL
2.5V20%470uF-8MOHM
POLY
C09531
23
D2T
CRITICAL
2.5V20%470uF-8MOHM
POLY
C09541
23
20%
402CERM
0.01UF16V
C09811
2603
6.3V20%
10uF
X5R
C0980 1
2
402MF-LF1/16W5%
0R09961 2
402MF-LF1/16W5%
0R09951 2
0
5%1/16WMF-LF402
R09931 2
MF-LF
0
5%1/16W
402
R09941 2
0
5%1/16WMF-LF402
R09911 2
0
5%1/16WMF-LF402
R09921 2
0
5%1/16WMF-LF402
R09901 2
1049
D
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
051-7099
CPU Decoupling & VID
=PP1V5_S0_CPU
=PP1V05_S0_CPU
IMVP6_VID<1>
CPU_VID<6>
IMVP6_VID<4>CPU_VID<4>
IMVP6_VID<2>CPU_VID<2>
IMVP6_VID<0>CPU_VID<0>
IMVP6_VID<5>CPU_VID<5>
IMVP6_VID<3>CPU_VID<3>
CPU_VID<1>
IMVP6_VID<6>
=PPVCORE_S0_CPU
63 11
63
63
8
79
79
79
79
79
79
79
51
8
7
57
8
57 8
57 8
57 8
57 8
57 8
8
57
8
D+
D-
ALERT*/
THM*
SCLK
SDATA
VDD
GND
THM2*
IO
IO
IN
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
PLACEHOLDER ADT7461A
LAYOUT NOTE:
(TO CPU INTERNAL THERMAL DIODE)
CPU_THERMD_N
LAYOUT NOTE:
CPU ZONE THERMAL SENSOR
ROUTE CPU_THERMD_P AND
10 MIL TRACE
LAYER.
10 MIL SPACING
FOR CPU_THERMD_P AND CPU_THERMD_N ON SAME
ADD GND GUARD TRACE
PLACE U1001 NEAR THE U1200
CRITICAL
MSOP
ADT7461
U10016
2
3
5
8
7
4
1
MF-LF
499
1/16W
402
1%
R10011 2
CERM50V
0.001uF10%
402
C10011
2
X5R
0.1UF16V10%
402
C10021
2
499
1%
MF-LF402
1/16W
R10021 2
1/16W5%
402
10K
MF-LF
R10051
2
10K1/16W
402MF-LF
5%
R10061
2
051-7099 D
10 104
SYNC_MASTER=M42 SYNC_DATE=10/07/2005
CPU MISC1-TEMP SENSOR
THRM_CPU_DX_PTHRM_CPU_DX_N
CPU_THERMD_P
CPU_THERMD_N
=PP3V3_S0_THRM_SNR
THRM_ALERT_L
THRM_ALERT
SMB_THRM_CLKSMB_THRM_DATA
50
50
7
7
63
27
27
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IO
IO
IO
IO
IO
IO
OUT
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’STCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX
INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.
(FROM CK410M HOST 133/167MHZ)
(DEBUG PORT RESET)(AND WITH RESET BUTTON) TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC
NC
NC
NC
(DBA#)
(DBR#)(DEBUG PORT ACTIVE)
CPU ITP700FLEX DEBUG SUPPORT
(FBO)
(TCK)
518S0320
CONNECTOR’S FBO PIN.
ITP TCK SIGNAL LAYOUT NOTE:
MF-LF
22.61%
1/16W402
ITP
R11001 2
ITP
402
1%
22.6
1/16WMF-LF
R11021 2
54.91/16W1%
402MF-LF
ITPR11031
2
402X5R16V10%0.1UFC11001
2
1/16W240
402MF-LF5%
R11041
2
F-RT-SM52435-2872
CRITICALITPCONN
J1101
1
10111213141516171819
2
202122232425262728
29
3
30
456789
1/16W402
54.91%MF-LF
R11011
2
680
402
5%1/16WMF-LF
R11061
2
CPU ITP700FLEX DEBUGSYNC_DATE=10/12/2005
051-7099 D
11 104
SYNC_MASTER=M42
=PP1V05_S0_CPU
FSB_CPURST_L
XDP_BPM_L<0>
XDP_TCK
XDP_TDI
XDP_TDO
=PP3V3_S5_SB_PM
=PP1V05_S0_CPU
XDP_TMS
CPU_XDP_CLK_N
XDP_TRST_L
XDP_BPM_L<1>XDP_BPM_L<2>XDP_BPM_L<3>XDP_BPM_L<4>XDP_BPM_L<5>XDP_TCKCPU_XDP_CLK_PITP_TDO
XDP_DBRESET_L
ITPRESET_L
63
63
11
11
9
79
63
9
8
12
26
8
79
26
7
7
7
7
23
7
7
7
34
7
79
IO
IO
IO
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
IO
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IN
IO
IN
IO
IO
HD4*
HD6*
HD16*
HTRDY*
HSLPCPU*
HRS1*
HRS0*
HHITM*
HLOCK*
HHIT*
HDSTBP2*
HDTSBP3*
HDSTBP1*
HDSTBP0*
HDSTBN3*
HDSTBN1*
HDSTBN2*
HDSTBN0*
HDINV2*
HDINV3*
HDINV1*
HDINV0*
HDVREF
HDRDY*
HDPWR*
HDEFER*
HDBSY*
HCPURST*
HBREQ0*
HBPRI*
HBNR*
HAVREF
HCLKIN*
HCLKIN
HYSWING
HYRCOMP
HYSCOMP
HXSWING
HXSCOMP
HXRCOMP
HA13*
HADS*
HADSTB0*
HD3*
HD2*
HD1*
HD0*
HD63*
HD62*
HD61*
HD60*
HD59*
HD58*
HD57*
HD56*
HD55*
HD54*
HD53*
HD52*
HD51*
HD50*
HD49*
HD48*
HD47*
HD46*
HD45*
HD44*
HD43*
HD42*
HD41*
HD40*
HD39*
HD38*
HD37*
HD36*
HD35*
HD34*
HD33*
HD32*
HD31*
HD29*
HD28*
HD27*
HD26*
HD25*
HD24*
HD23*
HD22*
HD21*
HD20*
HD19*
HD18*
HD17*
HD15*
HD10*
HD11*
HD12*
HD13*
HD14*
HD5*
HD7*
HD8*
HD9*
HA30*
HA29*
HA28*
HA27*
HA26*
HA25*
HA24*
HA23*
HA31*
HA20*
HA19*
HA18*
HA16*
HA15*
HA14*
HA21*
HA22*
HA17*
HA9*
HA8*
HA7*
HA6*
HA5*
HA4*
HA3*
HA10*
HA11*
HA12*
HADSTB1*
HREQ0*
HREQ1*
HREQ2*
HREQ3*
HD30*
HREQ4*
HRS2*
(1 OF 10)
HOST
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
402X5R16V10%
0.1uFC1211 1
2
2001%1/16WMF-LF402
R12111
2
1001%1/16WMF-LF402
R12101
2
54.91%
1/16WMF-LF
402
R12201
2
402MF-LF1/16W
1%24.9
R12211
2
2211%1/16WMF-LF402
R12251
2
1%1/16WMF-LF402
100R12261
2
0.1uF
402X5R16V10%
C12261
2
402X5R16V10%0.1uFC12361
2
2211%1/16WMF-LF402
R12351
2
54.91%
1/16WMF-LF
402
R12301
2
1%1/16WMF-LF402
100R12361
2402MF-LF1/16W
1%24.9
R12311
2
BGA
NB945GM
OMIT
U1200
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
H9
C14
D14
C9
E11
G11
F11
G12
F9
E8
B9
C13
J13
C6
F6
C7
AG2
AG1
B7
F1
J1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
H1
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
J6
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
H3
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
K2
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
G1
AB5
AD10
AD4
AC8
G2
K9
K1
A7
C3
J7
W8
U3
AB10
J9
H8
K4
T7
Y5
AC4
K3
T6
AA5
AC5
K13
D3
D4
B3
D8
G8
B8
F8
A8
B4
E6
D6
E3
E7
E1
E2
E4
Y1
U1
W1
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
NB CPU Interface
D
12 104
051-7099
FSB_D_L<17>
FSB_DSTBN_L<2>FSB_DSTBN_L<3>
FSB_DSTBP_L<1>FSB_DSTBP_L<2>FSB_DSTBP_L<3>
FSB_DINV_L<0>
FSB_DSTBN_L<0>
FSB_DINV_L<1>FSB_DINV_L<2>
NB_FSB_VREF
FSB_D_L<1>FSB_D_L<2>
FSB_D_L<4>FSB_D_L<5>FSB_D_L<6>
FSB_D_L<10>FSB_D_L<9>FSB_D_L<8>FSB_D_L<7>
FSB_D_L<3>
FSB_D_L<0>
FSB_D_L<16>
FSB_TRDY_LFSB_SLPCPU_L
FSB_RS_L<1>FSB_RS_L<0>
FSB_HITM_LFSB_LOCK_L
FSB_HIT_L
FSB_DSTBP_L<0>
FSB_DSTBN_L<1>
FSB_DINV_L<3>
FSB_DRDY_LFSB_DPWR_LFSB_DEFER_LFSB_DBSY_LFSB_CPURST_LFSB_BREQ0_LFSB_BPRI_LFSB_BNR_L
FSB_CLK_NB_NFSB_CLK_NB_P
NB_FSB_YSWING
NB_FSB_YRCOMPNB_FSB_YSCOMP
NB_FSB_XSWINGNB_FSB_XSCOMP
FSB_A_L<13>
FSB_ADS_LFSB_ADSTB_L<0>
FSB_D_L<63>FSB_D_L<62>FSB_D_L<61>FSB_D_L<60>FSB_D_L<59>FSB_D_L<58>FSB_D_L<57>FSB_D_L<56>FSB_D_L<55>FSB_D_L<54>FSB_D_L<53>FSB_D_L<52>FSB_D_L<51>FSB_D_L<50>FSB_D_L<49>FSB_D_L<48>FSB_D_L<47>FSB_D_L<46>FSB_D_L<45>FSB_D_L<44>FSB_D_L<43>FSB_D_L<42>FSB_D_L<41>FSB_D_L<40>FSB_D_L<39>FSB_D_L<38>FSB_D_L<37>FSB_D_L<36>FSB_D_L<35>FSB_D_L<34>FSB_D_L<33>FSB_D_L<32>FSB_D_L<31>
FSB_D_L<29>FSB_D_L<28>FSB_D_L<27>FSB_D_L<26>FSB_D_L<25>FSB_D_L<24>FSB_D_L<23>FSB_D_L<22>FSB_D_L<21>FSB_D_L<20>FSB_D_L<19>FSB_D_L<18>
FSB_D_L<15>
FSB_D_L<11>FSB_D_L<12>FSB_D_L<13>FSB_D_L<14>
FSB_A_L<30>FSB_A_L<29>FSB_A_L<28>FSB_A_L<27>FSB_A_L<26>FSB_A_L<25>FSB_A_L<24>FSB_A_L<23>
FSB_A_L<31>
FSB_A_L<20>FSB_A_L<19>FSB_A_L<18>
FSB_A_L<16>FSB_A_L<15>FSB_A_L<14>
FSB_A_L<21>FSB_A_L<22>
FSB_A_L<17>
FSB_A_L<9>FSB_A_L<8>FSB_A_L<7>FSB_A_L<6>FSB_A_L<5>FSB_A_L<4>FSB_A_L<3>
FSB_A_L<10>FSB_A_L<11>FSB_A_L<12>
FSB_ADSTB_L<1>
FSB_REQ_L<0>FSB_REQ_L<1>FSB_REQ_L<2>FSB_REQ_L<3>
FSB_D_L<30>
FSB_REQ_L<4>
FSB_RS_L<2>
=PP1V05_S0_FSB_NB
=PP1V05_S0_FSB_NB
=PP1V05_S0_FSB_NB
NB_FSB_XRCOMP
63
63
63
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
34
34
34
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
79
79
79
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
79
19
19
19
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
5
5
5
5
5
5
34
34
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
7
12
12
12
CRT_BLUE*
CRT_BLUE
CRT_GREEN*
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_RED*
HSYNC
CRT_DDC_DATA
CRT_VSYNC
CRT_IREF
TV_IRTNC
TV_IRTNB
TV_IREF
TV_IRTNA
TV_DACB_OUT
TV_DACC_OUT
TV_DACA_OUT
LB_DATA2
LB_DATA1
LB_DATA0
LB_DATA2*
LB_DATA1*
LB_DATA0*
LA_DATA2
LA_DATA1
LA_DATA0
LA_DATA2*
LA_DATA1*
LA_DATA0*
LB_CLK
LB_CLK*
LA_CLK
LA_CLK*
L_VDDEN
L_VREFL
L_VREFH
L_VBG
L_IBG
L_DDC_CLK
L_DDC_DATA
EXP_A_COMPI
EXP_A_COMPO
EXP_A_RXN0
EXP_A_RXN1
EXP_A_RXN2
EXP_A_RXN3
EXP_A_RXN4
EXP_A_RXN5
EXP_A_RXN6
EXP_A_RXN7
EXP_A_RXN8
EXP_A_RXN9
EXP_A_RXN10
EXP_A_RXN11
EXP_A_RXN12
EXP_A_RXN13
EXP_A_RXN15
EXP_A_RXN14
EXP_A_RXP0
EXP_A_RXP1
EXP_A_RXP2
EXP_A_RXP4
EXP_A_RXP3
EXP_A_RXP5
EXP_A_RXP6
EXP_A_RXP7
EXP_A_RXP10
EXP_A_RXP9
EXP_A_RXP8
EXP_A_RXP11
EXP_A_RXP12
EXP_A_RXP14
EXP_A_RXP13
EXP_A_RXP15
EXP_A_TXN1
EXP_A_TXN0
EXP_A_TXN3
EXP_A_TXN2
EXP_A_TXN6
EXP_A_TXN5
EXP_A_TXN4
EXP_A_TXN7
EXP_A_TXN8
EXP_A_TXN9
EXP_A_TXN10
EXP_A_TXN11
EXP_A_TXN12
EXP_A_TXN14
EXP_A_TXN13
EXP_A_TXN15
EXP_A_TXP0
EXP_A_TXP2
EXP_A_TXP1
EXP_A_TXP3
EXP_A_TXP4
EXP_A_TXP5
EXP_A_TXP7
EXP_A_TXP6
EXP_A_TXP8
EXP_A_TXP9
EXP_A_TXP10
EXP_A_TXP12
EXP_A_TXP11
EXP_A_TXP13
EXP_A_TXP14
EXP_A_TXP15
L_CLKCTLB
L_BKLTEN
L_CLKCTLA
L_BKLTCTL
(3 OF 10)
LVDS
TV
VGA
PCI-EXPRESS GRAPHICS
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
IO
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
SDVO_FLDSTALL#
SDVO Alternate Function
SDVO_TVCLKIN#SDVO_INT#
SDVO_TVCLKINSDVO_INTSDVO_FLDSTALL
SDVOB_GREENSDVOB_RED
SDVOC_CLKNSDVOC_BLUE#SDVOC_GREEN#SDVOC_RED#SDVOB_CLKNSDVOB_BLUE#SDVOB_GREEN#SDVOB_RED#
SDVOB_CLKPSDVOB_BLUE
SDVOC_REDSDVOC_GREENSDVOC_BLUESDVOC_CLKP
Otherwise, tie VCCD_LVDS to GND also.
LVDS Disable
VCCD_LVDS must remain powered with proper decoupling.
Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie
filtering components. Unused DAC outputs should
Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.
VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.
rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.
Component: DACA, DACB & DACC
Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and
connect to GND through 75-ohm resistors.
S-Video: DACB & DACC only
Unused DAC outputs must remain powered, but can omit
HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core
TV-Out Signal Usage:
Composite: DACA only
TV-Out Disable
CRT Disable
Can leave all signals NC if LVDS is not implementedTie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used
BGANB
945GM
OMIT
U1200
E23
D23
C26
C25
C22
B22
J22
A21
B21
H23
D40
D38
F34
G38
V34
W38
Y34
AA38
AB34
AC38
H34
J38
L34
M38
N34
P38
R34
T38
D34
F38
T34
V38
W34
Y38
AA34
AB38
G34
H38
J34
L38
M34
N38
P34
R38
F36
G40
V36
W40
Y36
AA40
AB36
AC40
H36
J40
L36
M40
N36
P40
R36
T40
D36
F40
T36
V40
W36
Y40
AA36
AB40
G36
H40
J36
L40
M36
N40
P36
R40
G23
D32
J30
H30
H29
G26
G25
B38
C35
F32
C33
C32
A32
A33
B37
C37
B34
B35
A36
A37
E26
E27
F30
G30
D29
D30
F28
F29
A16
C18
A19
J20
B16
B18
B19
402MF-LF1/16W1%24.9R13101
2
051-7099 D
10413
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
NB PEG / Video Interfaces
TV_DACA_OUTTV_DACB_OUTTV_DACC_OUT
TV_IREFTV_IRTNATV_IRTNBTV_IRTNC
PEG_D2R_N<7>
PEG_D2R_N<9>
PEG_D2R_N<15>
CRT_BLUE_LCRT_BLUE
CRT_GREEN_LCRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_RED_L
CRT_DDC_DATA
CRT_IREF
LVDS_B_DATA_P<2>LVDS_B_DATA_P<1>LVDS_B_DATA_P<0>
LVDS_B_DATA_N<2>LVDS_B_DATA_N<1>LVDS_B_DATA_N<0>
LVDS_A_DATA_P<2>LVDS_A_DATA_P<1>LVDS_A_DATA_P<0>
LVDS_A_DATA_N<2>LVDS_A_DATA_N<1>LVDS_A_DATA_N<0>
LVDS_B_CLK_PLVDS_B_CLK_NLVDS_A_CLK_PLVDS_A_CLK_N
LVDS_VDDEN
LVDS_VREFLLVDS_VREFH
TP_LVDS_VBGLVDS_IBG
LVDS_DDC_CLKLVDS_DDC_DATA
PEG_COMP
PEG_D2R_N<0>PEG_D2R_N<1>PEG_D2R_N<2>PEG_D2R_N<3>PEG_D2R_N<4>PEG_D2R_N<5>PEG_D2R_N<6>
PEG_D2R_N<8>
PEG_D2R_N<10>PEG_D2R_N<11>PEG_D2R_N<12>PEG_D2R_N<13>PEG_D2R_N<14>
PEG_D2R_P<0>PEG_D2R_P<1>PEG_D2R_P<2>
PEG_D2R_P<4>PEG_D2R_P<3>
PEG_D2R_P<5>PEG_D2R_P<6>PEG_D2R_P<7>
PEG_D2R_P<10>PEG_D2R_P<9>PEG_D2R_P<8>
PEG_D2R_P<11>PEG_D2R_P<12>
PEG_D2R_P<14>PEG_D2R_P<13>
PEG_D2R_P<15>
PEG_R2D_C_N<1>PEG_R2D_C_N<0>
PEG_R2D_C_N<3>PEG_R2D_C_N<2>
PEG_R2D_C_N<6>PEG_R2D_C_N<5>PEG_R2D_C_N<4>
PEG_R2D_C_N<7>PEG_R2D_C_N<8>PEG_R2D_C_N<9>PEG_R2D_C_N<10>PEG_R2D_C_N<11>PEG_R2D_C_N<12>
PEG_R2D_C_N<14>PEG_R2D_C_N<13>
PEG_R2D_C_N<15>
PEG_R2D_C_P<0>
PEG_R2D_C_P<2>PEG_R2D_C_P<1>
PEG_R2D_C_P<3>PEG_R2D_C_P<4>PEG_R2D_C_P<5>
PEG_R2D_C_P<7>PEG_R2D_C_P<6>
PEG_R2D_C_P<8>PEG_R2D_C_P<9>PEG_R2D_C_P<10>
PEG_R2D_C_P<12>PEG_R2D_C_P<11>
PEG_R2D_C_P<13>PEG_R2D_C_P<14>PEG_R2D_C_P<15>
LVDS_BKLTENLVDS_CLKCTLA
LVDS_BKLTCTL
=PP1V5_S0_NB_PCIE
LVDS_CLKCTLB
CRT_VSYNC_R
CRT_HSYNC_R
63
19
19
19
19
19
19
19
65
65
65
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
19
19
19
19
19
19
19
SM_CS0*RSVD15
RSVD14
SM_CKE2
RSVD2
RSVD3
RSVD6
RSVD4
RSVD5
RSVD8
RSVD7
RSVD9
RSVD1
RSVD10
RSVD11
RSVD12
RSVD13
CFG1
CFG0
CFG2
CFG3
CFG4
CFG6
CFG5
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG17
CFG16
CFG15
CFG18
CFG19
CFG20
PM_BM_BUSY*
PM_EXTTS0*
PM_EXTTS1*
PW_THRMTRIP*
PWROK
RSTIN*
SDVO_CTRLCLK
SDVO_CTRLDATA
ICH_SYNC*
CLK_REQ*
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC0
NC1
NC13
NC12
NC11
NC10
NC18
NC17
NC16
NC15
NC14
SM_CK0
SM_CK1
SM_CK2
SM_CK0*
SM_CK3
SM_CK1*
SM_CK2*
SM_CK3*
SM_CKE0
SM_CKE1
SM_CKE3
SM_CS1*
SM_CS2*
SM_CS3*
SMOCDCOMP0
SMOCDCOMP1
SM_ODT1
SM_ODT0
SM_ODT2
SMRCOMP*
SM_ODT3
SMRCOMP
SMVREF0
SMVREF1
G_CLKIN*
G_CLKIN
D_REFCLKIN*
D_REFCLKIN
D_REFSSCLKIN*
D_REFSSCLKIN
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP2
DMI_TXP1
DMI_TXP3
DDR MUXING
CFG
NC
PM
CLK
DMI
MISC
(2 OF 10)
RSVD
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NCNC
IPD
IPD
(LA_DATAN3)(LA_DATAP3)(LB_DATAN3)(LB_DATAP3)
(H_EDRDY#)(D_PLLMON1)
(H_PROCHOT#)(TESTIN#)
(TV_DCONSEL0)(TV_DCONSEL1)
(H_PLLMON1)(H_PLLMON1#)
(H_PCREQ#)
(VSS_MCHDETECT)
(D_PLLMON1#) NCNCNC
NC
NCNC
NCNCNCNCNCNCNCNCNC
NC
NCNCNCNCNC
IPU
IPD
IPU
IPU
IPUIPU
IPU
IPUIPUIPU
IPUIPUIPUIPU
NCNC
IPU
IPU
NC
NC
NC
BGANB
945GM
OMIT
U1200
K16
K18
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J18
J26
F18
E15
F15
E18
D19
D16
G16
H32
A26
A27
D41
C40
AE35
AF39
AG35
AH39
AC35
AE39
AF35
AG39
AE37
AF41
AG37
AH41
AC37
AE41
AF37
AG41
AG33
AF33
K28
D1
C41
B2
AY41
AY1
AW41
AW1
A40
A4
A39
A3
C1
BA41
BA40
BA39
BA3
BA2
BA1
B41
G28
F25
H26
G6
AH33
AH34
T32
J29
A41
A35
A34
D28
D27
R32
F3
F7
AG11
AF11
H7
J19
K30
H28
H27
AY35
AW35
AR1
AT1
AW7
AY7
AW40
AY40
AU20
AT20
BA29
AY29
AW13
AW12
AY21
AW21
BA13
BA12
AY20
AU21
AL20
AF10
AT9
AV9
AK1
AK41
402MF-LF1/16W5%
100R14301 2
10K
402
5%
MF-LF1/16W
R14411
2
10K
402
5%1/16WMF-LF
R14401
2
0.1uF
402CERM10V20%
C14161
2
0.1uF
402CERM10V20%
C1415 1
2
1/16W1%
402MF-LF
80.6R14101
2
1/16W1%
402MF-LF
80.6R14111
2
1/16W5%
402MF-LF
10KR14201
2
NB Misc InterfacesSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
051-7099 D
10414
TP_NB_XOR_FSB2_H7
TP_NB_XOR_LVDS_D27TP_NB_XOR_LVDS_D28TP_NB_XOR_LVDS_A34
MEM_VREF_NB_1MEM_VREF_NB_0
MEM_RCOMPMEM_RCOMP_L
=PP1V8_S3_MEM_NB
MEM_CKE<2>
MEM_CS_L<1>MEM_CS_L<2>MEM_CS_L<3>
MEM_ODT<1>MEM_ODT<2>
NB_CFG<12>
MEM_CS_L<0>
NB_BSEL<1>NB_BSEL<0>
NB_BSEL<2>NB_CFG<3>NB_CFG<4>
NB_CFG<6>NB_CFG<5>
NB_CFG<7>
NB_CFG<9>NB_CFG<10>
NB_CFG<14>
NB_CFG<17>NB_CFG<16>NB_CFG<15>
NB_CFG<19>NB_CFG<20>
PM_BMBUSY_L
PM_THRMTRIP_LVR_PWRGOOD_DELAY
SDVO_CTRLCLKSDVO_CTRLDATANB_SB_SYNC_L
MEM_CLK_P<0>MEM_CLK_P<1>MEM_CLK_P<2>
MEM_CLK_N<0>
MEM_CLK_P<3>
MEM_CLK_N<1>MEM_CLK_N<2>MEM_CLK_N<3>
MEM_CKE<0>MEM_CKE<1>
MEM_CKE<3>
MEM_ODT<0>
MEM_ODT<3>
NB_CLK100M_GCLKIN_NNB_CLK100M_GCLKIN_P
DMI_S2N_N<0>DMI_S2N_N<1>DMI_S2N_N<2>DMI_S2N_N<3>
DMI_S2N_P<0>DMI_S2N_P<1>DMI_S2N_P<2>DMI_S2N_P<3>
DMI_N2S_N<0>DMI_N2S_N<1>DMI_N2S_N<2>DMI_N2S_N<3>
DMI_N2S_P<0>
DMI_N2S_P<2>DMI_N2S_P<1>
DMI_N2S_P<3>
NB_RST_IN_L
NB_CFG<8>
NB_CFG<11>
NB_CFG<13>
NB_CFG<18>
=PP3V3_S0_NB
PM_DPRSLPVR
TP_NB_TESTIN_L
TP_NB_XOR_LVDS_A35
NB_TV_DCONSEL0NB_TV_DCONSEL1
=PP3V3_S0_NB
NB_CLK_DREFSSCLKIN_PNB_CLK_DREFSSCLKIN_NNB_CLK_DREFCLKIN_PNB_CLK_DREFCLKIN_N
CLK_NB_OE_L
NB_RST_IN_L_R
PM_EXTTS_L
63
63
63
20
79
20
19
30
30
30
30
30
30
30
57
30
30
30
30
30
22
22
22
22
19
57
19
48
19
19
19
32
32
16
29
28
29
29
28
29
6
28
34
34
34
6
6
6
20
20
20
6
6
6
20
6
20
20
23
26
19
19
22
28
28
29
28
29
28
29
29
28
28
29
28
29
34
34
22
22
22
22
22
22
22
22
5
5
22
22
5
22
5
22
26
6
6
6
20
14
23
19
14
19
19
19
19
33
47
SA_DQ1
SA_DQ0
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ12
SA_DQ11
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ29
SA_DQ28
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ35
SA_DQ34
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ46
SA_DQ45
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SA_BS1
SA_BS0
SA_BS2
SA_CAS*
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM5
SA_DM4
SA_DM7
SA_DM6
SA_DQS0
SA_DQS2
SA_DQS1
SA_DQS3
SA_DQS5
SA_DQS4
SA_DQS6
SA_DQS7
SA_DQS3*
SA_DQS2*
SA_DQS4*
SA_DQS5*
SA_DQS6*
SA_DQS7*
SA_MA1
SA_MA0
SA_MA2
SA_MA3
SA_MA5
SA_MA4
SA_MA6
SA_MA7
SA_MA9
SA_MA8
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_RAS*
SA_RCVENIN*
SA_RCVENOUT*
SA_WE*
SA_DQS1*
SA_DQS0*
(4 OF 10)
DDR SYSTEM MEMORY A
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
IO
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
SB_DQ1
SB_DQ0
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ12
SB_DQ11
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ29
SB_DQ28
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ35
SB_DQ34
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ46
SB_DQ45
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_BS1
SB_BS0
SB_BS2
SB_CAS*
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM5
SB_DM4
SB_DM7
SB_DM6
SB_DQS0
SB_DQS2
SB_DQS1
SB_DQS3
SB_DQS5
SB_DQS4
SB_DQS6
SB_DQS7
SB_DQS3*
SB_DQS2*
SB_DQS4*
SB_DQS5*
SB_DQS6*
SB_DQS7*
SB_MA1
SB_MA0
SB_MA2
SB_MA3
SB_MA5
SB_MA4
SB_MA6
SB_MA7
SB_MA9
SB_MA8
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_RAS*
SB_RCVENIN*
SB_RCVENOUT*
SB_WE*
SB_DQS1*
SB_DQS0*
(5 OF 10)
DDR SYSTEM MEMORY B
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NCNC
NCNC
BGA
945GMNB
OMIT
U1200AU12
AV14
BA20
AY13
AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4
AJ35
AJ34
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AM31
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AM33
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AJ36
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AK35
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AJ32
AG9
AH6
AF4
AF8
AH31
AN35
AP33
AK33
AK32
AT33
AU33
AN28
AN27
AM22
AM21
AN12
AM12
AN8
AL8
AP3
AN3
AG5
AH5
AY16
AU14
AU13
AT17
AV20
AV12
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AW14
AK23
AK24
AY14
BGA
945GMNB
OMIT
U1200AT24
AV23
AY28
AR24
AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4
AK39
AJ37
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
AP39
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AR41
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ38
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
AK38
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AN41
AT4
AK5
AJ5
AJ3
AP41
AT40
AV41
AM39
AM40
AT39
AU39
AU35
AT35
AR29
AP29
AR16
AP16
AR10
AT10
AR7
AT7
AN5
AP5
AY23
AW24
AV24
BA27
AY27
AR23
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AU23
AK16
AK18
AR27
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
NB DDR2 Interfaces
051-7099 D
10415
MEM_A_DQ<5>
MEM_A_DQS_N<0>MEM_A_DQS_N<1>
MEM_A_WE_L
MEM_A_RAS_L
MEM_A_A<13>MEM_A_A<12>MEM_A_A<11>MEM_A_A<10>
MEM_A_A<8>MEM_A_A<9>
MEM_A_A<7>MEM_A_A<6>
MEM_A_A<4>MEM_A_A<5>
MEM_A_A<3>MEM_A_A<2>
MEM_A_A<0>MEM_A_A<1>
MEM_A_DQS_N<7>MEM_A_DQS_N<6>MEM_A_DQS_N<5>MEM_A_DQS_N<4>
MEM_A_DQS_N<2>MEM_A_DQS_N<3>
MEM_A_DQS_P<7>MEM_A_DQS_P<6>
MEM_A_DQS_P<4>MEM_A_DQS_P<5>
MEM_A_DQS_P<3>
MEM_A_DQS_P<1>MEM_A_DQS_P<2>
MEM_A_DQS_P<0>
MEM_A_DM<6>MEM_A_DM<7>
MEM_A_DM<4>MEM_A_DM<5>
MEM_A_DM<3>MEM_A_DM<2>MEM_A_DM<1>MEM_A_DM<0>MEM_A_CAS_L
MEM_A_BS<2>
MEM_A_BS<0>MEM_A_BS<1>
MEM_A_DQ<63>MEM_A_DQ<62>MEM_A_DQ<61>MEM_A_DQ<60>MEM_A_DQ<59>MEM_A_DQ<58>MEM_A_DQ<57>MEM_A_DQ<56>MEM_A_DQ<55>MEM_A_DQ<54>MEM_A_DQ<53>MEM_A_DQ<52>MEM_A_DQ<51>MEM_A_DQ<50>MEM_A_DQ<49>MEM_A_DQ<48>MEM_A_DQ<47>
MEM_A_DQ<45>MEM_A_DQ<46>
MEM_A_DQ<44>MEM_A_DQ<43>MEM_A_DQ<42>MEM_A_DQ<41>MEM_A_DQ<40>MEM_A_DQ<39>MEM_A_DQ<38>MEM_A_DQ<37>MEM_A_DQ<36>
MEM_A_DQ<34>MEM_A_DQ<35>
MEM_A_DQ<33>MEM_A_DQ<32>MEM_A_DQ<31>MEM_A_DQ<30>
MEM_A_DQ<28>MEM_A_DQ<29>
MEM_A_DQ<27>MEM_A_DQ<26>MEM_A_DQ<25>MEM_A_DQ<24>MEM_A_DQ<23>MEM_A_DQ<22>MEM_A_DQ<21>MEM_A_DQ<20>MEM_A_DQ<19>MEM_A_DQ<18>MEM_A_DQ<17>MEM_A_DQ<16>MEM_A_DQ<15>MEM_A_DQ<14>MEM_A_DQ<13>
MEM_A_DQ<11>MEM_A_DQ<12>
MEM_A_DQ<10>MEM_A_DQ<9>MEM_A_DQ<8>MEM_A_DQ<7>MEM_A_DQ<6>
MEM_A_DQ<4>MEM_A_DQ<3>MEM_A_DQ<2>
MEM_A_DQ<0>MEM_A_DQ<1>
MEM_B_DQS_N<0>MEM_B_DQS_N<1>
MEM_B_WE_L
MEM_B_RAS_L
MEM_B_A<13>MEM_B_A<12>MEM_B_A<11>MEM_B_A<10>
MEM_B_A<8>MEM_B_A<9>
MEM_B_A<7>MEM_B_A<6>
MEM_B_A<4>MEM_B_A<5>
MEM_B_A<3>MEM_B_A<2>
MEM_B_A<0>MEM_B_A<1>
MEM_B_DQS_N<7>MEM_B_DQS_N<6>MEM_B_DQS_N<5>MEM_B_DQS_N<4>
MEM_B_DQS_N<2>MEM_B_DQS_N<3>
MEM_B_DQS_P<7>MEM_B_DQS_P<6>
MEM_B_DQS_P<4>MEM_B_DQS_P<5>
MEM_B_DQS_P<3>
MEM_B_DQS_P<1>MEM_B_DQS_P<2>
MEM_B_DQS_P<0>
MEM_B_DM<6>MEM_B_DM<7>
MEM_B_DM<4>MEM_B_DM<5>
MEM_B_DM<3>MEM_B_DM<2>MEM_B_DM<1>MEM_B_DM<0>MEM_B_CAS_L
MEM_B_BS<2>
MEM_B_BS<0>MEM_B_BS<1>
MEM_B_DQ<63>MEM_B_DQ<62>MEM_B_DQ<61>MEM_B_DQ<60>MEM_B_DQ<59>MEM_B_DQ<58>MEM_B_DQ<57>MEM_B_DQ<56>MEM_B_DQ<55>MEM_B_DQ<54>MEM_B_DQ<53>MEM_B_DQ<52>MEM_B_DQ<51>MEM_B_DQ<50>MEM_B_DQ<49>MEM_B_DQ<48>MEM_B_DQ<47>
MEM_B_DQ<45>MEM_B_DQ<46>
MEM_B_DQ<44>MEM_B_DQ<43>MEM_B_DQ<42>MEM_B_DQ<41>MEM_B_DQ<40>MEM_B_DQ<39>MEM_B_DQ<38>MEM_B_DQ<37>MEM_B_DQ<36>
MEM_B_DQ<34>MEM_B_DQ<35>
MEM_B_DQ<33>MEM_B_DQ<32>MEM_B_DQ<31>MEM_B_DQ<30>
MEM_B_DQ<28>MEM_B_DQ<29>
MEM_B_DQ<27>MEM_B_DQ<26>MEM_B_DQ<25>MEM_B_DQ<24>MEM_B_DQ<23>MEM_B_DQ<22>MEM_B_DQ<21>MEM_B_DQ<20>MEM_B_DQ<19>MEM_B_DQ<18>MEM_B_DQ<17>MEM_B_DQ<16>MEM_B_DQ<15>MEM_B_DQ<14>MEM_B_DQ<13>
MEM_B_DQ<11>MEM_B_DQ<12>
MEM_B_DQ<10>MEM_B_DQ<9>MEM_B_DQ<8>MEM_B_DQ<7>MEM_B_DQ<6>MEM_B_DQ<5>MEM_B_DQ<4>MEM_B_DQ<3>MEM_B_DQ<2>
MEM_B_DQ<0>MEM_B_DQ<1>
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
VCC_SM19
VCC_SM107
VCC_SM105
VCC_SM106
VCC_SM102
VCC_SM104
VCC_SM103
VCC_SM100
VCC_SM101
VCC_SM98
VCC_SM99
VCC_SM97
VCC_SM95
VCC_SM96
VCC_SM93
VCC_SM94
VCC_SM92
VCC_SM91
VCC_SM90
VCC_SM89
VCC_SM88
VCC_SM86
VCC_SM87
VCC_SM85
VCC_SM84
VCC_SM83
VCC_SM81
VCC_SM80
VCC_SM82
VCC_SM79
VCC_SM78
VCC_SM77
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM73
VCC_SM72
VCC_SM70
VCC_SM71
VCC_SM68
VCC_SM67
VCC_SM69
VCC_SM65
VCC_SM66
VCC_SM64
VCC_SM63
VCC_SM62
VCC_SM61
VCC_SM60
VCC_SM59
VCC_SM58
VCC_SM56
VCC_SM57
VCC_SM55
VCC_SM53
VCC_SM54
VCC_SM52
VCC_SM50
VCC_SM51
VCC_SM49
VCC_SM48
VCC_SM46
VCC_SM47
VCC_SM44
VCC_SM45
VCC_SM43
VCC_SM41
VCC_SM42
VCC_SM40
VCC_SM39
VCC_SM37
VCC_SM38
VCC_SM36
VCC_SM34
VCC_SM35
VCC_SM32
VCC_SM33
VCC_SM30
VCC_SM31
VCC_SM28
VCC_SM29
VCC_SM27
VCC_SM26
VCC_SM25
VCC_SM23
VCC_SM24
VCC_SM22
VCC_SM21
VCC_SM20
VCC_SM18
VCC_SM16
VCC_SM17
VCC_SM15
VCC_SM13
VCC_SM14
VCC_SM11
VCC_SM12
VCC_SM10
VCC_SM9
VCC_SM8
VCC_SM7
VCC_SM6
VCC_SM5
VCC_SM4
VCC_SM3
VCC_SM0
VCC_SM1
VCC_SM2
VCC_110
VCC_109
VCC_108
VCC_105
VCC_106
VCC_107
VCC_104
VCC_103
VCC_101
VCC_100
VCC_102
VCC_98
VCC_99
VCC_96
VCC_97
VCC_95
VCC_94
VCC_93
VCC_92
VCC_91
VCC_90
VCC_88
VCC_89
VCC_87
VCC_86
VCC_85
VCC_83
VCC_84
VCC_82
VCC_80
VCC_81
VCC_79
VCC_78
VCC_76
VCC_77
VCC_74
VCC_73
VCC_75
VCC_72
VCC_71
VCC_70
VCC_69
VCC_68
VCC_67
VCC_66
VCC_65
VCC_64
VCC_62
VCC_63
VCC_61
VCC_60
VCC_59
VCC_57
VCC_58
VCC_55
VCC_56
VCC_53
VCC_54
VCC_52
VCC_50
VCC_51
VCC_49
VCC_46
VCC_47
VCC_48
VCC_44
VCC_45
VCC_43
VCC_42
VCC_41
VCC_40
VCC_39
VCC_38
VCC_37
VCC_36
VCC_34
VCC_35
VCC_33
VCC_32
VCC_31
VCC_30
VCC_28
VCC_29
VCC_25
VCC_26
VCC_27
VCC_24
VCC_23
VCC_21
VCC_20
VCC_22
VCC_13
VCC_14
VCC_12
VCC_16
VCC_15
VCC_17
VCC_18
VCC_19
VCC_11
VCC_10
VCC_9
VCC_8
VCC_7
VCC_4
VCC_5
VCC_6
VCC_2
VCC_3
VCC_0
VCC_1
(6 OF 10)
VCC
VCCAUX_NCTF57
VCCAUX_NCTF56
VCCAUX_NCTF55
VCCAUX_NCTF54
VCCAUX_NCTF53
VCCAUX_NCTF52
VCCAUX_NCTF51
VCCAUX_NCTF50
VCCAUX_NCTF49
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF45
VCCAUX_NCTF44
VCCAUX_NCTF46
VCCAUX_NCTF40
VCCAUX_NCTF39
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF36
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF31
VCCAUX_NCTF30
VCCAUX_NCTF29
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF26
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF22
VCCAUX_NCTF21
VCCAUX_NCTF23
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF41
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF18
VCCAUX_NCTF17
VCCAUX_NCTF16
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF13
VCCAUX_NCTF12
VCCAUX_NCTF11
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF8
VCCAUX_NCTF7
VCCAUX_NCTF6
VCCAUX_NCTF5
VCCAUX_NCTF4
VCCAUX_NCTF3
VCCAUX_NCTF1
VCCAUX_NCTF0
VCCAUX_NCTF2
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF7
VSS_NCTF8
VSS_NCTF5
VSS_NCTF6
VSS_NCTF4
VSS_NCTF2
VSS_NCTF3
VSS_NCTF0
VSS_NCTF1
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70
VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF60
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF56
VCC_NCTF55
VCC_NCTF53
VCC_NCTF54
VCC_NCTF52
VCC_NCTF50
VCC_NCTF51
VCC_NCTF49
VCC_NCTF48
VCC_NCTF46
VCC_NCTF47
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF41
VCC_NCTF40
VCC_NCTF42
VCC_NCTF38
VCC_NCTF39
VCC_NCTF36
VCC_NCTF37
VCC_NCTF34
VCC_NCTF35
VCC_NCTF33
VCC_NCTF31
VCC_NCTF32
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF18
VCC_NCTF19
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF13
VCC_NCTF14
VCC_NCTF11
VCC_NCTF12
VCC_NCTF10
VCC_NCTF8
VCC_NCTF9
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF0
VCC_NCTF1
(7 OF 10)
NCTF
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
1.8V Max CurrentSpeed 1 Channel 2 Channel400MTs 1300mA 2400mA533MTs 1500mA 2800mA667MTs 1700mA 3200mA
1.05V, Internal Graphics: 3500mA Max
1.5V, Internal Graphics: 5500mA Max1.05V, External Graphics: 1500mA Max
1.05V or 1.5V
Place in cavityLayout Note:
Layout Note:Place near pin BA15
Place near pin BA23Layout Note:
impacting part performance.These connections can break without
NCTF balls are Not Critical To Function
BGA
NB
945GM
OMIT
U1200
AA33
W33
P32
M19
L19
N18
M18
L18
P17
N17
M17
N16
M16
N32
L16
M32
L32
J32
AA31
W31
V31
T31
R31
P33
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
N33
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
L33
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
J33
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
AA32
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
Y32
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
W32
M22
L22
AC21
AA21
W21
N21
M21
L21
AC20
AB20
V32
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19
AU41
AT41
AR34
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM41
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
AU40
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
BA34
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AY34
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AW34
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AV34
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AU34
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AT34
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
402
6.3VCERM-X5R
0.47uF20%
C16101
2603
20%
X5R6.3V
10uFC16211
2
10uF6.3VX5R
20%
603
C1620 1
2
945GMNBBGA
OMIT
U1200AD27
AC27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AB27
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AA27
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
Y27
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
W27
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
V27
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
U27
V18
U18
T18
T27
R27
AG27
AF27
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AG26
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
AF26
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
AG25
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AF25
AB15
AA15
Y15
W15
V15
U15
T15
R15
AG24
AF24
AG23
AF23
AE27
AE26
AC17
Y17
U17
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
402
6.3VCERM-X5R
0.47uF20%
C16111
2402
6.3VCERM-X5R
0.47uF20%
C1612 1
2402
6.3VCERM-X5R
20%0.47uFC16131
2402
6.3VCERM-X5R
20%0.47uFC1614 1
2
402
6.3VCERM-X5R
20%0.47uFC16151
2
NB Power 1SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
051-7099 D
10416
=PP1V5_S0_NB_VCCAUX
=PPVCORE_S0_NB
=PPVCORE_S0_NB
NB_VCCSM_LF4NB_VCCSM_LF5
NB_VCCSM_LF2NB_VCCSM_LF1
=PP1V8_S3_MEM_NB
63
63
63
63
19
19
19
19
17
16
16
14
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT15
VTT14
VTT16
VTT18
VTT17
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT27
VTT26
VTT28
VTT29
VTT31
VTT30
VTT32
VTT34
VTT33
VTT35
VTT36
VTT37
VTT39
VTT38
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT48
VTT46
VTT47
VTT49
VTT50
VTT52
VTT51
VTT53
VTT55
VTT54
VTT57
VTT56
VTT58
VTT59
VTT60
VTT61
VTT62
VTT64
VTT63
VTT65
VTT66
VTT67
VTT69
VTT68
VTT70
VTT71
VTT73
VTT72
VTT74
VTT76
VTT75
VCCSYNC
VCC_TXLVDS0
VCC_TXLVDS1
VCC_TXLVDS2
VCC3G0
VCC3G1
VCC3G3
VCC3G2
VCC3G4
VCC3G6
VCC3G5
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
VCCA_DPLLB
VCCA_DPLLA
VCCA_HPLL
VSSA_LVDS
VCCA_LVDS
VCCA_MPLL
VCCA_TVBG
VSSA_TVBG
VCCA_TVDACC0
VCCA_TVDACC1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACA0
VCCA_TVDACA1
VCCD_HMPLL0
VCCD_HMPLL1
VCCD_LVDS2
VCCD_LVDS0
VCCD_LVDS1
VCCD_TVDAC
VCC_HV1
VCC_HV2
VCC_HV0
VCCD_QTVDAC
VCCAUX19
VCCAUX18
VCCAUX17
VCCAUX16
VCCAUX14
VCCAUX15
VCCAUX13
VCCAUX12
VCCAUX11
VCCAUX10
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX6
VCCAUX5
VCCAUX9
VCCAUX8
VCCAUX7
VCCAUX21
VCCAUX20
VCCAUX23
VCCAUX24
VCCAUX22
VCCAUX25
VCCAUX26
VCCAUX29
VCCAUX28
VCCAUX27
VCCAUX30
VCCAUX31
VCCAUX33
VCCAUX32
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX38
VCCAUX37
VCCAUX39
VCCAUX40
POWER
(8 OF 10)
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
1500mA Max VCC3G/3GPLL
800mA Max
2mA Max
60mA Max
70mA Max VCCA_CRTDAC/VCCSYNC
20mA Max
24mA Max
10mA Max
50mA Max50mA Max45mA Max
45mA Max
120mA Max
150mA Max
See VCCSYNC
40mA Max
1900mA Max
OMIT
BGANB
945GMU1200
AJ41
AB41
Y41
V41
R41
N41
L41
A23
B23
B25
C30
B30
A30
G41
AC33
F21
E21
B26
C39
AF1
A38
AF2
H20
E19
F19
C20
D20
E20
F20
AK31
AF31
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE31
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
AC31
P15
AH14
AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AL30
AD12
AK30
AJ30
AH30
AG30
AF30
AH1
AH2
A28
B28
C28
H19
D21
H22
H41
G21
B39
G20
AC14
AB14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
W14
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
V14
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
T14
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
R14
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
P14
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
N14
M2
D2
AB1
R1
P1
N1
M1
M14
L14
402CERM-X5R
6.3V
0.47uF20%
C1711 1
220%0.22uF6.3V
402X5R
C17121
2
402
6.3VCERM-X5R
20%0.47uFC1713 1
2
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
NB Power 2
051-7099 D
10417
=PP1V5_S0_NB_VCCD_LVDS
PP1V5_S0_NB_VCCD_TVDAC
=PP1V05_S0_NB_VTT
NB_VTTLF_CAP3
NB_VTTLF_CAP2NB_VTTLF_CAP1
=PP2V5_S0_NB_VCCSYNC
=PP2V5_S0_NB_VCC_TXLVDS
PP1V5_S0_NB_VCC3G
PP1V5_S0_NB_VCCA_3GPLL=PP2V5_S0_NB_VCCA_3GBGGND_NB_VSSA_3GBG
GND_NB_VSSA_CRTDAC
PP1V5_S0_NB_VCCA_DPLLBPP1V5_S0_NB_VCCA_DPLLA
PP1V5_S0_NB_VCCA_HPLL
GND_NB_VSSA_LVDS=PP2V5_S0_NB_VCCA_LVDS
PP1V5_S0_NB_VCCA_MPLL
PP3V3_S0_NB_VCCA_TVBGGND_NB_VSSA_TVBG
PP3V3_S0_NB_VCCA_TVDACC
PP3V3_S0_NB_VCCA_TVDACB
PP3V3_S0_NB_VCCA_TVDACA
=PP1V5_S0_NB_VCCD_HMPLL
=PP3V3_S0_NB_VCC_HV
PP1V5_S0_NB_VCCD_QTVDAC
=PP1V5_S0_NB_VCCAUX
PP2V5_S0_NB_VCCA_CRTDAC
63
63
63
63
63
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
16
19
VSS_1
VSS_0
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_9
VSS_8
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_19
VSS_18
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_28
VSS_27
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_37
VSS_36
VSS_39
VSS_38
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_49
VSS_48
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_57
VSS_56
VSS_59
VSS_58
VSS_61
VSS_60
VSS_64
VSS_63
VSS_62
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_73
VSS_72
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_82
VSS_80
VSS_81
VSS_84
VSS_83
VSS_85
VSS_87
VSS_86
VSS_89
VSS_88
VSS_91
VSS_90
VSS_92
VSS_93
VSS_94
VSS_96
VSS_95
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_114
VSS_113
VSS_115
VSS_117
VSS_116
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_127
VSS_126
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_137
VSS_136
VSS_138
VSS_139
VSS_140
VSS_141
VSS_143
VSS_142
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_158
VSS_157
VSS_159
VSS_160
VSS_161
VSS_162
VSS_164
VSS_163
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_172
VSS_171
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS
(9 OF 10)
VSS_272
VSS_271
VSS_269
VSS_270
VSS_268
VSS_266
VSS_267
VSS_265
VSS_264
VSS_263
VSS_261
VSS_262
VSS_260
VSS_259
VSS_258
VSS_256
VSS_257
VSS_255
VSS_254
VSS_253
VSS_251
VSS_252
VSS_250
VSS_248
VSS_249
VSS_247
VSS_246
VSS_245
VSS_243
VSS_244
VSS_242
VSS_241
VSS_240
VSS_238
VSS_239
VSS_237
VSS_236
VSS_235
VSS_233
VSS_234
VSS_232
VSS_231
VSS_230
VSS_228
VSS_229
VSS_227
VSS_225
VSS_226
VSS_224
VSS_223
VSS_222
VSS_220
VSS_221
VSS_219
VSS_218
VSS_217
VSS_215
VSS_216
VSS_214
VSS_213
VSS_212
VSS_210
VSS_211
VSS_209
VSS_207
VSS_208
VSS_205
VSS_206
VSS_204
VSS_202
VSS_203
VSS_201
VSS_200
VSS_199
VSS_197
VSS_198
VSS_196
VSS_195
VSS_194
VSS_192
VSS_193
VSS_191
VSS_190
VSS_189
VSS_187
VSS_188
VSS_186
VSS_184
VSS_185
VSS_183
VSS_182
VSS_180
VSS_181
VSS_273
VSS_274
VSS_276
VSS_275
VSS_277
VSS_279
VSS_278
VSS_281
VSS_280
VSS_282
VSS_283
VSS_284
VSS_286
VSS_285
VSS_287
VSS_288
VSS_289
VSS_291
VSS_290
VSS_293
VSS_292
VSS_294
VSS_296
VSS_295
VSS_297
VSS_299
VSS_298
VSS_301
VSS_302
VSS_300
VSS_304
VSS_303
VSS_305
VSS_306
VSS_307
VSS_309
VSS_308
VSS_311
VSS_310
VSS_312
VSS_313
VSS_314
VSS_315
VSS_317
VSS_316
VSS_318
VSS_319
VSS_320
VSS_322
VSS_321
VSS_323
VSS_324
VSS_325
VSS_327
VSS_326
VSS_328
VSS_329
VSS_330
VSS_332
VSS_331
VSS_334
VSS_333
VSS_335
VSS_337
VSS_336
VSS_338
VSS_339
VSS_340
VSS_342
VSS_343
VSS_341
VSS_345
VSS_344
VSS_346
VSS_347
VSS_348
VSS_350
VSS_349
VSS_352
VSS_351
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS
(10 OF 10)
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NB945GM
BGA
OMIT
U1200AC41
AA41
AN40
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
AK40
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AJ40
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AH40
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
AG40
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AF40
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
AE40
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
B40
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AY39
AW39
W41
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
T41
T39
R39
P39
N39
M39
L39
J39
H39
G39
F39
P41
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
M41
AB37
AA37
Y37
W37
V37
T37
R37
P37
N37
M37
J41
L37
J37
H37
G37
F37
D37
AY36
AW36
AN36
AH36
F41
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AV40
AB35
AA35
Y35
W35
V35
T35
R35
P35
N35
M35
AP40
L35
J35
H35
G35
F35
D35
AN34
AK34
AG34
AF34
NB945GM
BGA
OMIT
U1200AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
J11
D11
B11
AV10
AP10
AL10
AJ10
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
NB Grounds
051-7099 D
10418
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(MCH DDR DLL&IO, FSB HSIO&IO PWR 1.5V)
GMCH CORE PWR 1.05V BYPASS1500mA Max
1500mA Max 10mA Max?
?mA Max
?mA Max
60mA Max 70mA Max
3200mA Max
24mA Max 100mA Max
?mA Max 800mA Max
3674mA Max
?mA Max 40mA Max
40mA Max?
1500mA Max
2mA Max
1900mA Max 150mA Max
2310mA Max?
Power InterfaceThese are the power signals that leave the NB "block"
132mA Max
3200mA Max
Rail Totals:
(MCH TVDAC DEDICATED PWR 1.5V)
(MCH TVDAC DIGITAL QUIET 1.5V PWR)
(MCH TV OUT CHANNEL A 3.3V PWR)
(MCH TV OUT CHANNEL B 3.3V PWR)
(MCH TV DAC BAND GAP 3.3V PWR)
(MCH TV OUT CHANNEL C 3.3V PWR)
(MCH LVDS DATA/CLK TX 2.5V PWR)
(MCH LVDS DIGITAL 1.5V PWR)
(MCH LVDS ANALOG 2.5V PWR)
(MCH CRTDAC ANALOG 2.5V PWR)
(MCH H/V SYNC 2.5V PWR)
(MCH DISPLAY A PLL 1.5V PWR)
(MCH DISPLAY B PLL 1.5V PWR)
1500mA Maxbe close to MCHon opposite side.
GMCH VCCA_3GPLL FILTER
(PCI-E/DMI ANALOG 1.5V PWR)
10uF caps should
Layout Note: Route to caps, then GND
(3GIO PLL 1.5V PWR)
GMCH VCC3G FILTER
Layout Note:
be placed in cavity3GPLL 10uF cap shouldLayout Note:
Place L and Cclose to MCH
Layout Note:
1500mA Max
GMCH VCCA_HPLL FILTER
45mA Max
(HOST PLL 1.5V PWR)
(MCH MEMORY PLL 1.5V PWR)GMCH VCCA_MPLL FILTER
45mA Max
100mA Max
GMCH VCCAUX FILTER
1900mA Max
(MCH PCIE/DMI BAND GAP 2.5V PWR)MCH VCCA_3GBG BYPASS
2mA Max
MCH VCC_HV BYPASS(MCH HV BUFFER 3.3V PWR)
40mA Max
Place on the edgeLayout Note:
(SHARE C0940 470UF)
MCH VTT BYPASS(MCH FSB 1.05V PWR)
Layout Note:Place in cavity
800mA Max
402
20%6.3VX5R
0.22uFC19071
2
10uF6.3V20%
603X5R
C19721
2
220UF20%2.5V
SMB2POLY
C19701
2
0.22uF
X5R402
20%6.3V
C19671
2CERM1
20%2.2uF
603
6.3V
C19661
2
4.7uF
CERM603
20%6.3V
C19651
2
20%2.5VTANTD2T
CRITICAL
470uFC19001
23
1210
91nHL1970
1 2
CERM10V20%
402
0.1uFC1916 1
2
0.22uF
X5R402
20%6.3V
C19061
2
0.1uF
CERM402
20%10V
C19151
2
10uF
X5R603
20%6.3V
C1914 1
2
0.22uF
X5R
20%
402
6.3V
C19051
2
0.1uF
CERM402
10V20%
C19351
2
0603
FERR-120-OHM-0.2AL1934
1 2
402
10V20%
CERM
0.1uFC19371
2
10%
CERM
1uF6.3V
402
C19041
2
0603
FERR-120-OHM-0.2AL1936
1 2
6.3V20%
805CERM
22UFC1934 1
2
6.3V20%
805CERM
22UFC1936 1
2
10uF
603
20%
X5R6.3V
C19031
2
10uF
X5R603
20%6.3V
C19021
2
CERM402
20%10V
0.1uFC1918 1
2
0.1uF
CERM402
20%10V
C19761
2
0805
1.0UH-220MA-0.12-OHML1975
1 2
10uF
X5R603
20%6.3V
C1975 1
2
1%1/16W
0.51
402MF-LF
R19751 2
6.3V20%
603X5R
10uFC19711
2
19 104
D051-7099
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
NB (GM) Decoupling
=PP1V05_S0_NB_VTT =PP3V3_S0_NB_VCC_HV=PP2V5_S0_NB_VCCA_3GBG =PP1V5_S0_NB_VCCAUX
=PP1V5_S0_NB_PLL
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mm
VOLTAGE=1.5V
PP1V5_S0_NB_VCCA_MPLL
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mm
VOLTAGE=1.5V
PP1V5_S0_NB_VCCA_HPLL
MIN_NECK_WIDTH=0.4 mmMIN_LINE_WIDTH=0.6 mm
VOLTAGE=1.5V
PP1V5_S0_NB_3GPLL_F
GND_NB_VSSA_3GBG
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
VOLTAGE=1.5V
PP1V5_S0_NB_VCCA_3GPLL=PP1V5_S0_NB_3GPLL
=PP1V5_S0_NB_3G
NB_CLK_DREFSSCLKIN_P
NB_CLK_DREFSSCLKIN_N
NB_CLK_DREFCLKIN_P
NB_CLK_DREFCLKIN_N
MAKE_BASE=TRUETP_NB_VCCA_DPLLB PP1V5_S0_NB_VCCA_DPLLB
TP_NB_VCCA_DPLLAMAKE_BASE=TRUE
PP1V5_S0_NB_VCCA_DPLLA
GND_NB_VSSA_TVBG
PP3V3_S0_NB_VCCA_TVBG
PP3V3_S0_NB_VCCA_TVDACC
PP3V3_S0_NB_VCCA_TVDACB
PP3V3_S0_NB_VCCA_TVDACA
PP1V5_S0_NB_VCCD_QTVDAC
PP1V5_S0_NB_VCCD_TVDAC
PP2V5_S0_NB_VCCA_CRTDAC
GND_NB_VSSA_CRTDAC
MAKE_BASE=TRUENC_GND_NB_VSSA_LVDS
NO_TEST=TRUEGND_NB_VSSA_LVDS
=PP2V5_S0_NB_VCCA_LVDS
=PP1V5_S0_NB_VCCD_LVDS
=PP2V5_S0_NB_VCC_TXLVDS
=PP1V5_S0_NB_TVDAC
=PPVCORE_S0_NB
=PPVCORE_S0_NB
=PP1V5_S0_NB
=PP1V05_S0_NB_VTT
=PP1V5_S0_NB_3G
=PP1V5_S0_NB_PCIE
=PP1V05_S0_FSB_NB
=PP3V3_S0_NB=PP3V3_S0_NB_VCC_HV
=PP2V5_S0_NB_VCCA_3GBG
=PP1V8_S3_MEM_NB
=PP1V5_S0_NB_VCCD_HMPLL=PP1V5_S0_NB_VCCAUX
=PP1V5_S0_NB_TVDAC=PP1V5_S0_NB_PLL
=PP1V5_S0_NB_3GPLL
=PP1V05_S0_NB_CRT
=PPVCORE_S0_NB
MAKE_BASE=TRUETP_CRT_DDC_CLK
CRT_DDC_DATAMAKE_BASE=TRUETP_CRT_DDC_DATA
CRT_DDC_CLK
CRT_IREFCRT_BLUE_LCRT_GREEN_LCRT_RED_LCRT_BLUECRT_GREENCRT_RED
=PP1V05_S0_NB_CRT
TV_DACB_OUTTV_DACC_OUT
TV_DACA_OUT
TV_IRTNATV_IREF
TV_IRTNCTV_IRTNB
LVDS_BKLTENMAKE_BASE=TRUETP_LVDS_BKLTEN
LVDS_BKLTCTLMAKE_BASE=TRUETP_LVDS_BKLTCTL
LVDS_CLKCTLAMAKE_BASE=TRUETP_LVDS_CLKCTLA
LVDS_CLKCTLBMAKE_BASE=TRUETP_LVDS_CLKCTLB
LVDS_DDC_CLKMAKE_BASE=TRUETP_LVDS_DDC_CLK
LVDS_IBGNO_TEST=TRUEMAKE_BASE=TRUE
NC_LVDS_IBG
LVDS_DDC_DATAMAKE_BASE=TRUETP_LVDS_DDC_DATA
LVDS_VREFLMAKE_BASE=TRUETP_LVDS_VREFL
LVDS_VDDENMAKE_BASE=TRUETP_LVDS_VDDEN
LVDS_VREFHNO_TEST=TRUEMAKE_BASE=TRUE
NC_LVDS_VREFH
LVDS_A_CLK_PMAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_A_CLKP
LVDS_A_CLK_NMAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_A_CLKN
LVDS_A_DATA_P<2..0>MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_A_DATAP<2..0>
LVDS_A_DATA_N<2..0>MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_A_DATAN<2..0>
LVDS_B_CLK_NNO_TEST=TRUEMAKE_BASE=TRUE
NC_LVDS_B_CLKN
LVDS_B_DATA_P<2..0>NO_TEST=TRUEMAKE_BASE=TRUE
NC_LVDS_B_DATAP<2..0>
LVDS_B_CLK_PNO_TEST=TRUEMAKE_BASE=TRUE
NC_LVDS_B_CLKP
MAKE_BASE=TRUE NO_TEST=TRUENC_NB_XOR_LVDS_A35
MAKE_BASE=TRUE NO_TEST=TRUENC_NB_XOR_LVDS_D27
TP_NB_XOR_LVDS_D28MAKE_BASE=TRUE NO_TEST=TRUENC_NB_XOR_LVDS_D28
TP_NB_XOR_LVDS_A35MAKE_BASE=TRUE NO_TEST=TRUENC_NB_XOR_LVDS_A34
SDVO_CTRLDATAMAKE_BASE=TRUETP_SDVO_CTRLDATA
SDVO_CTRLCLKMAKE_BASE=TRUETP_SDVO_CTRLCLK
TP_NB_XOR_LVDS_A34MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_B_DATAN<2..0>
=PP1V5_S0_NB_TVDAC
CRT_VSYNC_RCRT_HSYNC_R
=PP2V5_S0_NB_VCC_TXLVDS=PP2V5_S0_NB_VCCSYNC
LVDS_B_DATA_N<2..0>
TP_NB_XOR_LVDS_D27
=PP2V5_S0_NB_VCCSYNC
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPP1V5_S0_NB_VCC3G
VOLTAGE=1.5V
63
63
63 63
63 19
63
63
63
63
63
63
63
63
19
63
19 19
19 17
63
63
63
19
63
19
19
19
63
63
34
20
19
19
16
63
17
63
63
63
63
19
63
63
19
19
19
17 17
17 16
19
17
17
17
17 19
19
14
14
14
14
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
19
16
16
63
17
19
13
12
14
17
17
14
17
16
19
19
19
19
16
13
13
13
13
13
13
13
13
13
19
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
14
14
14
14
14
19
13
13
17
17
13
14
17
17
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Internal pull-ups
Internal pull-up
RESERVED
RESERVED
NB_CFG<11>
NB_CFG<10>
High = Mobile CPUNB_CFG<7>
RESERVED
Internal pull-up
DMI x2 Select
PROBABLY NOT NEEDED
PROBABLY NOT NEEDED
Lane Reversal
NB_CFG<4>
NB_CFG<3>
RESERVED
NB_CFG<13:12>
NB_CFG<14>
NB_CFG<5>NB_CFG<15>
NB_CFG<16>NB_CFG<6>
NB_CFG<17>
NB_CFG<18>NB_CFG<8>
NB_CFG<9> NB_CFG<19>
NB_CFG<20>
Low = DMIx2
High = DMIx4
Low = RESERVED
High = NormalPCIE Graphics
RESERVED
CPU Strap
RESERVED
Low = Reversed
Internal pull-up
11 = Normal Operation10 = All-Z Mode Enabled01 = XOR Mode Enabled00 = Partial Clock Gating Disable
RESERVED
Internal pull-up
RESERVED
High = Enabled
Low = Disabled
RESERVED
FSB DynamicODT
or PCIe x1Low = Only SDVO
High = Both active
945 External Design Spec says reserved
Internal pull-down
Internal pull-down
Internal pull-down
Low = 1.05V
High = 1.5V
Low = Normal
High = ReversedDMI LaneReversal
VCC Select
Interop. ModePCIe Backward
402
5%2.2K1/16WMF-LF
NBCFG_DMI_X2R20751
2
5%2.2K1/16WMF-LF402
NBCFG_DYN_ODT_DISABLE
R20851
2
402
1/16W5%2.2K
NBCFG_VCC_1V5
MF-LF
R20581
2
402MF-LF1/16W5%2.2K
NBCFG_DMI_REVERSE
R20591
2
NBCFG_SDVO_AND_PCIE
402MF-LF1/16W5%2.2KR20601
2
NO STUFF
2.2K5%1/16WMF-LF402
R20771
2
402MF-LF1/16W5%2.2K
NBCFG_PEG_REVERSE
R20791
2
20 104
D051-7099
NB Config StrapsSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
=PP3V3_S0_NB
=PP3V3_S0_NB
=PP3V3_S0_NB
NB_CFG<18>
NB_CFG<19>
NB_CFG<20>
NB_CFG<16>
NB_CFG<5>
NB_CFG<9>
NB_CFG<7>
63
63
63
20
20
20
19
19
19
14
14
14
14
14
14
14
14
14
14
IO
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IO
IO
IO
IO
IN
IO
DDACK*
SATARBIASN
SATARBIASP
SATA_CLKN
SATA_CLKP
SATA_2TXP
SATA_2TXN
SATA_2RXN
SATA_2RXP
SATA_0TXP
SATA_0TXN
SATA_0RXP
SATA_0RXN
SATALED*
ACZ_SDOUT
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDIN0
ACZ_SYNC
ACZ_BIT_CLK
LAN_TXD2
LAN_TXD0
LAN_TXD1
LAN_RXD1
LAN_RXD2
LAN_RSTSYNC
LAN_RXD0
LAN_CLK
EE_SHCLK
EE_CS
INTVRMEN
INTRUDER*
RTCRST*
RTCX2
RTCX1
THRMTRIP*
STPCLK*
NMI
SMI*
RCIN*
INTR
INIT*
INIT3_3V*
IGNNE*
GPIO49/CPUPWRGD
FERR*
TP1/DPRSTP*
TP2/DPSLP*
A20M*
CPUSPL*
A20GATE
LFRAME*
LDRQ1*/GPIO23
LDRQ0*
LAD3
LAD2
LAD0
LAD1
EE_DOUT
EE_DIN
ACZ_RST*
DIOR*
IDEIRQ
DIOW*
IORDY
DDREQ
DD0
DD1
DD3
DD2
DD5
DD4
DD6
DD7
DD8
DD11
DD9
DD10
DD12
DD13
DD14
DD15
DA0
DA1
DA2
DCS3*
DCS1*
AC-97/
AZALIA
RTC
LPC
LAN
CPU
IDE
SATA
(1 OF 6)
OUT
OUT
OUT
IN
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
IN
IN OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L
(INT PU)
(INT PU)
(WEAK INT PD)
NOTE: R2108=56 IN CV.
BOM CONSOLIDATIONCHANGED TO 54.9 FORNOTE: R2110=56 IN CV.
NOTE: PULLED UP PER INTEL
NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU
INTEL CONFIRMS OK TO LEAVE PINS AS NC
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
INTO RESET STATE TO SAVE PWR.
NOTE:POR IS SMC WILL PUT LAN INT’F
NOTE: KEYBOARD CONTROLLER RESET CPU
NOTE: RISING-EDGE TRIGGERED AT CPUBOM CONSOLIDATION
< 2 IN OF SBLAYOUT NOTE: R2107 TO BE
CHANGED TO 54.9 FOR
LAYOUT NOTE: R2108 TO BE< 2 IN OF R2107 W/O STUB
(DSTROBE)
20K PD
20K PD
20K PD
(STOP)(HSTROBE)
NOTE: DD<7> HAS INTERNAL 11.5K PD
NOTE: ENABLE INTERNAL 1.05V SUSPEND REG
INTERNAL 20K PD ONLY ENABLED IN S3COLD
INTERNAL 20K PD
NONE
- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR
INTERNAL 20K PD ENABLED WHEN
INTERNAL 20K PD
INTERNAL 20K PD ENABLED DURING RESET AND WHEN
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR
AC ’07
INTERNAL 20K PD
INTERNAL 20K PD ENABLED WHEN
ACZ_SDIN[0-2]
ACZ_RST#
ACZ_BIT_CLK
ACZ_SYNC
ACZ_SDOUT
INTEL HIGH DEFINITION AUDIO
NOTE: LAD<0-3> HAVE INTERNAL 20K PU
NOTE: DDREQ HAS INTERNAL 11.5K PD
LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE
NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S
(WEAK INT PU)
NOSTUFF
1/16WMF-LF
0
5%402
R21001 2
NOSTUFF
402
2.2K5%
1/16WMF-LF
R21011 2
MF-LF5%
394021/16W
R2195 1 2
39R2198 1 2
39R2197 1 2
39R2196 1 2
402
10K5%1/16WMF-LF
R21991
2
BGASB
ICH7-M
OMIT
U2100
AE22AH28
U1
R5T2T3T1
T4
R6
AG27
AH17AE17AF17
AE16AD16
AB15AE14
AB13AC14AF14AH13AH14AC15
AG13AF13AD14AC13AD12AC12AE12AF12
AF16
AE15
AF15AH15
W1
W3Y2Y1
AG26
AG24
AH16
AG22
AF22AG21
AF25
Y5W4
AG16
AA6AB5AC4Y6
V3
U3
U5V4T5
U7V6V7
AC3AA5
AB3
AH24
AG23
AA3
AB1AB2
AF3AE3AG2AH2
AF7AE7AG6AH6
AF1AE1
AF18
AH10AG10
AF23
AH22
AF26
AF24AH25
402
10K5%1/16WMF-LF
R21941
2
332K402
1%1/16WMF-LF
R2105
1
2
24.9MF-LF1/16W1%
402
R21071 2
402MF-LF1/16W1%54.9R2108
1
2
MF-LF1/16W
40254.9
1%
R2110
12
D
21 104
051-7099
SYNC_MASTER=M38 SYNC_DATE=11/16/2005
SB: 1 OF 4
IDE_PDD<3>IDE_PDD<2>
TP_SB_XOR_V3
TP_SB_XOR_W3
TP_SB_XOR_T5TP_SB_XOR_V4TP_SB_XOR_U5
TP_SB_XOR_U3
PP3V3_S5_SB_RTC
ACZ_RST_L
ACZ_BITCLK
SB_RTC_RST_L
SB_RTC_X2
LPC_FRAME_L
TP_SB_GPIO23TP_SB_DRQ0_L
LPC_AD<3>LPC_AD<2>LPC_AD<1>LPC_AD<0>
=PP3V3_S0_SB_GPIO
=PP3V3_S0_SB_GPIO
IDE_PDD<6>
ACZ_SDATAOUTPM_THRMTRIP_L
=PP1V05_S0_SB_CPU_IO
SMC_RCIN_LACZ_SYNC
IDE_PDCS1_LIDE_PDCS3_L
IDE_PDA<2>IDE_PDA<1>IDE_PDA<0>
IDE_PDD<15>IDE_PDD<14>IDE_PDD<13>IDE_PDD<12>
IDE_PDD<10>IDE_PDD<9>
IDE_PDD<11>
IDE_PDD<8>IDE_PDD<7>
IDE_PDD<4>IDE_PDD<5>
IDE_PDD<1>IDE_PDD<0>
IDE_PDDREQIDE_PDIORDY
IDE_PDIOW_L
IDE_IRQ14
IDE_PDIOR_L
SB_ACZ_RST_L
TP_CPU_CPUSLP_L
CPU_A20M_L
CPU_DPSLP_LCPU_DPRSTP_L
CPU_PWRGD
CPU_IGNNE_LFWH_INIT_LCPU_INIT_LCPU_INTR
CPU_SMI_LCPU_NMI
CPU_STPCLK_L
CPU_THERMTRIP_R
SB_RTC_X1
SB_SM_INTRUDER_L
SB_ACZ_BITCLKSB_ACZ_SYNC
ACZ_SDATAIN<0>
TP_SB_ACZ_SDIN2TP_SB_ACZ_SDIN1
SB_ACZ_SDATAOUT
TP_SB_SATALED_L
SATA_A_D2R_NSATA_A_D2R_PSATA_A_R2D_C_NSATA_A_R2D_C_P
SATA_C_D2R_N
SATA_C_R2D_C_NSATA_C_R2D_C_P
SB_CLK100M_SATA_PSB_CLK100M_SATA_N
SATA_RBIAS_PSATA_RBIAS_N
IDE_PDDACK_L
SATA_C_D2R_P
CPU_RCIN_L
SB_A20GATE
CPU_FERR_L
=PP1V05_S0_SB_CPU_IO
SB_INTVRMEN
TP_SB_XOR_W1TP_SB_XOR_Y1TP_SB_XOR_Y2
TP_SB_XOR_U7TP_SB_XOR_V6TP_SB_XOR_V7
56
56
56
56
56
63
63
26
79
79
49
49
49
49
49
63
63
79 48
25
79
49
79
25
25
45
45
47
47
47
47
47
23
23
45 14
24
45
79
79
57
79
79
48
79
79
79
79
79
45
34
34
24
36
36
6
6
6
6
24
5
5
26
26
5
5
5
5
5
21
21
36
5 7
21
47 5
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
79
7
7
7
7
7
5
7
7
7
7
7
26
26
79
79
5
79
36
36
36
36
76
76
76
5
5
36
36
36
76
7
21
IN
IO
IO
IO
IO
IO
IO
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
DMI_ZCOMP
DMI_CLKP
DMI_IRCOMP
USBRBIAS*
USBRBIAS
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3TXP
DMI3TXN
DMI3RXP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP4N
OC0*
OC1*
OC2*
OC3*
OC4*
OC6*/GPIO30
OC5*/GPIO29
SPI_CLK
SPI_CS*
SPI_MOSI
SPI_MISO
SPI_ARB
DMI_CLKN
DMI2RXP
DMI2RXN
DMI1TXP
DMI1TXN
DMI1RXN
DMI1RXP
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
PERN6
PERP6
PETN6
PETP6
OC7*/GPIO31
PCI-EXP
(3 OF 6)
DMI
SPI
USB
REQ4*/GPIO22
REQ0*
MCH_SYNC*
RSVD8
RSVD7
RSVD6
RSVD5
RSVD4
GPIO5/PIRQH*
GPIO4/PIRQG*
GPIO3/PIRQF*
GPIO2/PIRQE*
GPIO17/GNT5*
GPIO1/REQ5*
GNT4*/GPIO48
C/BE0*
C/BE1*
DEVSEL*
PERR*
STOP*
PCIRST*
PME*
PLTRST*
TRDY*
FRAME*
IRDY*
PCICLK
PAR
PLOCK*
SERR*
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE2*
C/BE3*
GNT0*
REQ1*
GNT1*
REQ2*
GNT2*
REQ3*
GNT3*
PIRQA*
PIRQB*
PIRQC*
PIRQD*
RSVD0
RSVD1
RSVD2
RSVD3
MISC
INT I/F
PCI
(2 OF 6)
IO
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IO
IO
IO
IO
OUT
IO
IO
IO
IO
IO
IO
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NO STUFF - DEFAULT
GNT[0-3]# HAVE INT 20K PU
(INT 20K PU)
(AKA TP3, INTERNAL 20K PU)
SB: 2 OF 4
ENABLED ONLY WHEN PCIRST#=0
R2211
NOTE: FWH_WP_L NOT USED
NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD
GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)
(INT PD)
(INT PD)
GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H
PLACE R2204 < 1/2 IN FROM SBLAYOUT NOTE:
PLACE R2203 < 1/2 IN FROM SBLAYOUT NOTE:
NOTE:
LPC (DEFAULT)
PCI
SPI UNSTUFF
STUFF
UNSTUFFUNSTUFF
UNSTUFF
STUFF01
10
11
STRAP R2210
NOTE: CHANGE SYMBOL TO RSVD[1-9]
GNT5# GNT4#
SB BOOT BIOS SELECT
TARGETING FWH BIOS SPACE)IE SB INVERTS A16 FOR ALL CYCLES(STRAPPED TO TOP-BLOCK SWAP MODE
STUFF - A16 SWAP OVERRIDE
NOTE:
EXTERNAL 0
EXTERNAL 1
EXTERNAL 2
AIRPORT (MINI-PCIE)
CAMERA
CF/SD
BT
IR
BOM NOTE FOR PD ON PCI_GNT3_L:
NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L
AND PWROK=H
1/16W 402
24.9MF-LF1%
R22031 2
10K1/16WMF-LF5%
402
USB_G_OC_PUR22221
2
402
22.61%
1/16WMF-LF
R22041 2
1/16W5%10KMF-LF402
R22231
2
10K5%1/16WMF-LF402
R22251
2402MF-LF1/16W10K5%
R22261
2
10K5%1/16WMF-LF402
R22991
2
OMIT
BGASB
ICH7-MU2100
V26V25U28U27
Y26Y25W28W27
AB26AB25AA28AA27
AD25AD24AC28AC27
AE28AE27
D25C25
D3C4D5D4E5C3A2B3
F26
H26
K26
M26
P26
T25
F25
H25
K25
M25
P25
T24
E28
G28
J28
L28
N28
R28
E27
G27
J27
L27
N27
R27
P1
R2P6
P2P5
F1F2G4G3H1H2J4J3K1K2L4L5M1M2N4N3
D1D2
SBBGA
ICH7-M
OMIT
U2100E18C18
E14D14B12C13G15G13E12C11D11A11
A16
A10F11F10E9D9B9A8A6C7B6
F18
E6D6
E16A18E17A17A15C14
B15C12D12C15
A12
F16
E7
D16
D17
F13
A14C8D8
G8F7F8G7
A7
AH20
E10A9
B18
C9
A3B4C5B5
E11
C26
B19
D7
C16
C17
E13
A13
AE5AD5AG4AH4AD9
AE9AG8AH8F21
B10F15F14
MF-LF1/16W5%10K
402
R22001
2 402MF-LF1/16W5%10K
USB_C_OC_PU
R22501
2
10K5%1/16WMF-LF402
USB_E_OC_PU
R22511
2
USB_D_OC_PU
MF-LF1/16W5%10K
402
R22551
2
MF-LF4021/16W5%10KR22981
2
MF-LF402 5%
10K1/16W
R2205
1
2
402
10KMF-LF
5%1/16W
NOSTUFF
R2206
1
2
MF-LF1/16W10K
402 5%
R2207
1
2
VOLTAGE=0V
1/16WMF-LF5%1K
402
R22111
2
051-7099
10422
D
TP_PCI_GNT4_L
PCI_GNT3_L
TP_PCI_GNT2_L
TP_PCI_GNT0_L
TP_PCI_GNT1_L
=PP3V3_S5_SB_USB
USB_D_OC_L
USB_B_OC_L
USB_E_OC_L
USB_A_OC_L
SB_GPIO31
NB_SB_SYNC_LTP_SB_RSVD9
ODD_PWR_EN_LSB_GPIO4SB_GPIO3SB_GPIO2
PCI_C_BE_L<0>PCI_C_BE_L<1>
PCI_DEVSEL_LPCI_PERR_L
PCI_RST_LTP_PCI_PME_L
PLT_RST_L
PCI_TRDY_L
PCI_FRAME_L
PCI_IRDY_L
PCI_CLK_SBPCI_PAR
PCI_LOCK_LPCI_SERR_L
PCI_AD<0>
PCI_AD<2>PCI_AD<3>PCI_AD<4>PCI_AD<5>
PCI_AD<7>PCI_AD<8>PCI_AD<9>PCI_AD<10>PCI_AD<11>PCI_AD<12>PCI_AD<13>PCI_AD<14>PCI_AD<15>PCI_AD<16>PCI_AD<17>PCI_AD<18>PCI_AD<19>PCI_AD<20>PCI_AD<21>PCI_AD<22>PCI_AD<23>PCI_AD<24>PCI_AD<25>PCI_AD<26>PCI_AD<27>PCI_AD<28>PCI_AD<29>PCI_AD<30>PCI_AD<31>
PCI_C_BE_L<3>
INT_PIRQA_LINT_PIRQB_LINT_PIRQC_L
DMI_IRCOMP_R
SB_CLK100M_DMI_P
USB_RBIAS_PN
DMI_N2S_N<0>DMI_N2S_P<0>DMI_S2N_N<0>DMI_S2N_P<0>
DMI_S2N_N<2>DMI_S2N_P<2>
DMI_N2S_N<3>
DMI_S2N_P<3>DMI_S2N_N<3>DMI_N2S_P<3>
USB_A_NUSB_A_PUSB_B_NUSB_B_PUSB_C_NUSB_C_PUSB_D_NUSB_D_P
USB_E_PUSB_F_NUSB_F_PUSB_G_NUSB_G_PUSB_H_N
USB_E_N
SB_GPIO30SB_GPIO29
SB_CLK100M_DMI_N
DMI_N2S_P<2>DMI_N2S_N<2>
DMI_S2N_P<1>DMI_S2N_N<1>
DMI_N2S_N<1>DMI_N2S_P<1>
PCIE_A_D2R_NPCIE_A_D2R_PPCIE_A_R2D_C_NPCIE_A_R2D_C_P
PCIE_B_D2R_NPCIE_B_D2R_PPCIE_B_R2D_C_NPCIE_B_R2D_C_P
PCIE_C_D2R_NPCIE_C_D2R_PPCIE_C_R2D_C_NPCIE_C_R2D_C_P
PCIE_D_D2R_NPCIE_D_D2R_PPCIE_D_R2D_C_NPCIE_D_R2D_C_P
PCIE_E_D2R_NPCIE_E_D2R_PPCIE_E_R2D_C_NPCIE_E_R2D_C_P
PCIE_F_D2R_NPCIE_F_D2R_PPCIE_F_R2D_C_NPCIE_F_R2D_C_P
SB_GPIO31
PP1V5_S0_SB_VCC1_5_B=PP3V3_S5_SB_IO
USB_C_OC_L
USB_A_OC_LUSB_B_OC_L
USB_D_OC_LUSB_C_OC_L
SPI_ARB
SPI_SO
USB_H_P
INT_PIRQD_L
TP_SB_XOR_AD5TP_SB_XOR_AG4TP_SB_XOR_AH4TP_SB_XOR_AD9
TP_SB_XOR_AE5
TP_SB_XOR_AH8
SB_CRT_TVOUT_MUX
TP_SB_XOR_AG8TP_SB_XOR_AE9
SB_GPIO29
USB_E_OC_L
PCI_AD<6>
PCI_AD<1>PCI_REQ0_L
PCI_REQ1_L
PCI_REQ3_L
PCI_STOP_L
SPI_SCLK
PCI_C_BE_L<2>
BOOT_LPC_SPI_L
PCI_REQ2_L
SB_GPIO30
SPI_CE_L
SPI_SI
=PP3V3_S0_SB
PCI_PME_FW_L49
22
22
22
22
40
40
40
40
40
40
14
14
22
14
14
25
22
22
22
22
22
52
40
22
40
40
52
47
22
52
52
63
40
63
6
6
6
6
22
14
36
26
26
26
40
40
26
26
40
26
26
26
26
34
40
26
26
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
26
26
26
34
5
5
14
14
14
14
14
14
14
14
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
22
34
14
14
14
14
5
5
37
37
37
37
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
22
24 63
6
6
6
6
6
47
47
6
26
22
6
40
40
26
26
26
26
47
40
5
26
6
47
47
25
40
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IO
IO
OUT
OUT
OUT
IN
IN
IO
IN
IN
IO
IN
IN
IN
IN
OUT
IO
IO
IN
OUT
IN
OUT
IN
OUT
GPIO19/SATA1GP
GPIO21/SATA0GP
GPIO36/SATA2GP
CLK48
GPIO37/SATA3GP
CLK14
SUSCLK
SLP_S3*
SLP_S4*
SLP_S5*
PWROK
TP0/BATLOW*
GPIO16/DPRSLPVR
PWRBTN*
LAN_RST*
RSMRST*
GPIO10
GPIO9
GPIO12
GPIO14
GPIO13
GPIO24
GPIO15
GPIO25
GPIO35
GPIO38
GPIO39
SMBCLK
SMBDATA
LINKALERT*
SMLINK1
SMLINK0
RI*
SYS_RST*
SPKR
SUS_STAT*
GPIO0/BM_BUSY*
GPIO18/STPPCI*
GPIO11/SMBALERT*
GPIO20/STPCPU*
GPIO26
GPIO28
GPIO27
GPIO32/CLKRUN*
GPIO33/AZ_DOCK_EN*
WAKE*
GPIO34/AZ_DOCK_RST*
SERIRQ
THRM*
GPIO7
GPIO6
VRMPWRGD
GPIO8
(4 OF 6)
SMB
GPIO
PWR MNGT
SYS GPIO
CLKS
SATA GPIO
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)
AZALIA DOCKING INT’FRESERVED FOR MOBILE
SYSTEM REBOOT FEATURE
STRAPPING @ PWROK RISING:SB WILL DISABLE TCO TIMER
NOTE FOR R2323 (DEF=NOSTUFF)
NOT USED
NOTE: RESERVED FOR FUTURE
(INT WEAK PD)
LAYOUT NOTE:PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE
NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN
NOTE FOR GPIO25:
(INT 20K PU)
OD
DEF=GPI
DEF=GPI
DEF=GPI
IN RESET STATE TO SAVE PWRSMC WILL DRIVE 0-1-0 TO KEEP LAN INT’FNOTE:
NOTE: SV_SET_UP IS LINDACARD DETECT
LO = NOT PRESENTHI = PRESENT
100 R23021 2
100 R23031 2
100 R23051 2
NOSTUFF
4025%MF-LF1/16W10KR23061
2
10K4025%MF-LF1/16W
R23071
2
4021/16WMF-LF5%
10KR23081
2
5%MF-LF1/16W0402
NOSTUFFR23091
2
4025%MF-LF1/16W10KR23101
2
1/16WMF-LF5%
NOSTUFF
40210KR23111
2
10K1/16WMF-LF5%402
R23131
2
402
NOSTUFF
01/16WMF-LF5%
R23141
2
40210K1/16WMF-LF5%
R23161
240210K1/16WMF-LF5%
R23171
2
10K4021/16WMF-LF5%
R23181
2
10K1/16WMF-LF5%402
R23191
2
4025%MF-LF1/16W10KR23201
2
1/16W5%10KSM-LF
RP2300
1 2 3 4
8 7 6 5
5%402MF-LF
1/16W
100KR23991 2
1/16WMF-LF5%4021KR23981
2
5%MF-LF1/16W8.2K402
R23971
2MF-LF5%
1/16W10K402
R23961
2
8.2K1/16WMF-LF4025%
R23951
2
OMIT
BGASB
ICH7-MU2100
AC1B2
AB18
A20
B23
F19E19R4E22
AC22AC20
AH18
AF21
AF19
R3D20
A21
B21E23
AG18
AC19U2
AD21
AH19AE19
AD20AE20
AC21AC18E21
E20
C19
A26
C23
AA4
A28
Y4
AH21
B24D23F22
C22B22
B25A25
A19A27
C20
A22
AF20
C21
AD22
F20
402
10K5%1/16WMF-LF
R23901
2
4021/16WMF-LF5%10KR23881
2
MF-LF4025%
1K1/16W
NO_REBOOT_MODER23231
2
NOSTUFF
10K1/16WMF-LF4025%
R23261
2
NOSTUFF
5%MF-LF1/16W40210KR23271
2
5%
402
8.2K1/16WMF-LF
R23431
2
SB: 3 OF 4SYNC_DATE=11/16/2005SYNC_MASTER=M38
051-7099
10423
D
SV_SET_UP
PM_RSMRST_L
SMB_CLK
SATA_C_DET_LSB_GPIO19SB_GPIO21
SB_CLK48M_USBCTLR
SB_GPIO37
SB_CLK14P3M_TIMER
SUS_CLK_SB
PM_SLP_S3_LPM_SLP_S4_LPM_SLP_S5_L
PM_SB_PWROK
PM_BATLOW_L
PM_DPRSLPVR
PM_PWRBTN_L
PM_LAN_ENABLE
SV_SET_UP
TP_SB_GPIO25_DO_NOT_USESB_CLK100M_SATA_OE_L
SATA_C_PWR_EN_L
SMB_LINK_ALERT_L
SMLINK<1>SMLINK<0>
PM_RI_L
PM_SYSRST_LPM_SUS_STAT_L
BIOS_REC
TP_AZ_DOCK_EN_L
VR_PWRGD_CK410
=PP3V3_S5_SB
=PP3V3_S5_SB_PM
=PP3V3_S5_SB
IDE_RESET_L
TP_SB_GPIO6TP_SB_GPIO38
CRB_SV_DET
=PP3V3_S5_SB
FWH_MFG_MODEBIOS_REC
=PP3V3_S0_SB_GPIO
SMC_SB_NMIPATA_PWR_EN_L
SMS_INT_L
SMC_WAKE_SCI_L
CRB_SV_DET
=PP3V3_S0_SB_GPIO
SATA_C_PWR_EN_L
=PP3V3_S5_SB
PATA_PWR_EN_L
PM_STPPCI_L
TP_AZ_DOCK_RST_L
FWH_MFG_MODE
PM_STPCPU_L
PM_BMBUSY_L
SB_SPKR
SMB_DATA
=PP3V3_S5_SB
INT_SERIRQPCIE_WAKE_L
PM_CLKRUN_L
SMB_ALERT_L
SB_GPIO26
PM_THRM_L
SMC_EXTSMI_LSMC_RUNTIME_SCI_L
56
56
49
56
49
49
62
62
79
49
47
48
63
63
63
63
63
63
63
63
49
45
47
23
47
47
48
57
23
26
47
25
26
25
25
23
48
23
25
25
47
37
40
5
47
27
36
34
34
6
41
39
47
26
47
14
47
47
5
33
23
5
5
23
26
23
11
23
36
23
23
23
23
21
47
23
47
47
23
21
23
23
23
33
23
33
14
27
23
5
5
5
47
47
47
(6 OF 6)
VSS
V5REF_SUS
VCC3_3
VCCDMIPLL
VCCSATAPLL
VCC3_3
VCCRTC
VCCUSBPLL
VCCSAUS1_5
VCC PAUX
USB COREVCC1_5_A
ARX
USB
PCI
IDE
VCCA3GP
CORE
ATX
VCC1_5_A
VCC3_3
VCC3_3
VCCSUS3_3
VCC1_5_A
VCCSUS3_3
VCCSUS3_3
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCCLAN1_5
V_CPU_IO
VCC3_3/VCCHDA
VCCSUS3_3/VCCSUSHDA
VCCLAN_3_3
VCC1_05
V5REF
VCC1_5_B
(5 OF 6)
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NOTE FOR VCCLAN_3_3:S3 IF INTERNAL LAN IS USEDS0 OR S3 IF NOT
CHANGE SYMBOL TO 1.05
CHANGE SYMBOL TO 1.05
SO NO CONNECT HEREVOLTAGE GENERATED INTERNALLY
SO NO CONNECT HEREVOLTAGE GENERATED INTERNALLY
NOTE:VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3VDEPENDING ON VIO OF AZALIA INTERFACECODEC IC’S CONSIDERED SO FAR ARE 3.3V
0 0
OMIT
BGA
ICH7-MSB
U2100A4
A23
B1
B8B11B14B17B20B26B28C2C6C27
D10
D13D18D21D24E1E2E4E8E15F3
F4
F5F12F27F28G1G2G5G6G9G14
G18
G21G24G25G26H3H4H5H24H27H28
J1
J2J5J24J25J26K24K27K28L13L15
L24
L25L26M3M4M5M12M13M14M15M16
M17
M24M27M28N1N2N5N6N11N12N13
N14
N15N16
AE24AE25AF2AF4AF8
AF11AF27AF28
N17
AG1AG3AG7
AG11AG14AG17AG20AG25AH1AH3
N18
AH7AH12AH23AH27
N24
N25N26P3P4
P12P13P14P15P16P17
P24
P27P28R1
R11R12R13R14R15R16R17
R18
T6T12T13T14T15T16T17U4
U12U13
U14
U15U16U17U24U25U26V2
V13V15V24
V27
V28W6
W24W25W26Y3
Y24Y27Y28AA1
AA24
AA25AA26AB4AB6
AB11AB14AB16AB19AB21AB24
AB27
AB28AC2AC5AC9
AC11AD1
AD3AD4AD7AD8
AD11
AD15AD19AD23AE2AE4AE8AE11AE13AE18AE21
OMIT
BGASB
ICH7-MU2100
G10AD17
F6
AE23AE26AH26
L11
P18T11T18U11U18V11V12V14V16V17
L12
V18
L14L16L17L18M11M18P11
AB7AC6
AB9AC10AD10AE10AF10AF9AG9AH9
AB17AC17
AC7
T7F17G17
AB8AC8
A1H6H7J6J7
AD6AE6AF5AF6AG5AH5
AB10
AA22AA23
AD28D26D27D28E24E25E26F23F24G22
AB22
G23H22H23J22J23K22K23L22L23M22
AB23
M23N22N23P22P23R22R23R24R25R26
AC23
T22T23T26T27T28U22U23V22V23W22
AC24
W23Y22Y23
AC25AC26AD26AD27
U6
B27
AH11
AG19
A5B13B16B7C10D15F9G11G12
AA7
G16
AB12AB20AC16AD13AD18AG12AG15
AG28
AA2Y7
V5V1W2W7
W5
AD2
K7
C28G20
R7
P7
A24
L1L2L3L6L7M6M7N7
E3
C24D19D22G19
K3K4K5K6
C1
SB: 4 OF 4SYNC_DATE=11/16/2005SYNC_MASTER=M38
D
24 104
051-7099
PP1V5_S0_SB_VCC1_5_B
PP5V_S0_SB_V5REF
PP5V_S5_SB_V5REF_SUS
=PPVCORE_S0_SB
=PP3V3_S0_SB_VCCLAN3_3
=PP3V3_S0_SB_3V3_1V5_VCCHDA=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA
=PP1V05_S0_SB_CPU_IO
=PP3V3_S0_SB_VCC3_3
PP1V5_S0_SB_VCCDMIPLL
=PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V5_S0_SB_VCCSATAPLL
=PP3V3_S0_SB_VCC3_3
=PP1V5_S0_SB_VCC1_5_A_ATX
=PP3V3_S5_SB_VCCSUS3_3
=PP3V3_S0_SB_VCC3_3_IDE
=PP3V3_S0_SB_VCC3_3_PCI
PP3V3_S5_SB_RTC
=PP3V3_S5_SB_VCCSUS3_3
=PP3V3_S5_SB_VCCSUS3_3_USB
=PP1V5_S0_SB_VCC1_5_A
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
=PP1V5_S0_SB_VCCUSBPLL
63
63
63
63
26
63
25
63
63
25
25
63
63
25
63
25
63
63
25
25
63
63
63
22
25
25
25
25
21
24
25
25
25
24
25
24
25
25
21
24
25
25
25
NC
NC
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(ICH IO,LOGIC 1.5V PWR)ICH VCCA3GP(VCC1_5_B BYPASS
PLACE < 2.54MM OF SB ON
PLACE < 2.54MM OF SB ON SECONDARY OR
PLACEMENT NOTE:PLACE CAPS AT EDGE OF SB
ICH VCC3_3/VCCHDA BYPASS(ICH INTEL HDA CORE 3.3V PWR)
PLACE NEAR PINS AE23, AE26 & AH26 OF SB
PLACE C2500 & C2505-07 < 2.54MM OF SBON SECONDARY SIDE OR 3.56MM ON PRIMARY
ICH VCCUSBPLL BYPASS(ICH USB PLL 1.5V PWR)
(ICH DMI PLL 1.5V PWR)
ICH PCI/VCC3_3 BYPASS
(ICH IDE I/O 3.3V PWR)
PLACEMENT NOTE:PLACE < 2.54MM OF SB ON SECONDARY OR
PLACEMENT NOTE:PLACE < 2.54MM OF SB ON SECONDARY OR3.56MM ON PRIMARY NEAR PIN AH11
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACEMENT NOTE:
ICH USB CORE/VCC1_5_A BYPASS
PLACE < 2.54MM OF SB ON SECONDARY OR3.56MM ON PRIMARY NEAR PINS A1 ... J7
(ICH USB CORE 1.5V PWR)
(ICH LOGIC&IO 1.5V PWR)ICH VCC1_5A BYPASS
PLACEMENT NOTE:
PLACEMENT NOTE:
ICH VCCSUS3_3 BYPASS(ICH SUSPEND 3.3V PWR)
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN U6
PLACE CAP UNDER SB NEAR PINS V1,PLACEMENT NOTE:
(ICH CORE 1.05V PWR)ICH CORE/VCC1_05 BYPASS
PLACEMENT NOTE:
ICH V5REF BYPASS
PLACE < 2.54MM OF SB ON SECONDARY OR
SB: 4 OF 4
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACE CAPS NEAR PIN W5 OF SB
PLACEMENT NOTE:PLACE CAPS NEAR PINS
FOR 270UFPLACEHOLDER
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN AG5
3.56MM ON PRIMARY NEAR PIN AG9
(ICH IO BUFFER 3.3V PWR)
NEAR PINS A5 ... G16 DISTRIBUTE IN PCI SECTION OF SB
A24 ... G19 AND P7 OF SB
(ICH PCI I/O 3.3V PWR)
PLACE < 2.54MM OF SB ON SECONDARY OR
ICH IDE/VCC3_3 BYPASS
(ICH CPU I/O 1.05V PWR)ICH V_CPU_IO BYPASS
PLACE < 2.54MM OF SB ON SECONDARY OR
(ICH SATA PLL 1.5V PWR)ICH VCCSATAPLL BYPASS
(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)
(ICH IO BUFFER 3.3V PWR)
ICH VCC1_5_A/ATX BYPASS
PLACEMENT NOTE:
NEAR PINS D28, T28, AD28
PLACE C2520 NEAR PIN C1 OF SB
K3 ... N7 OF SBPLACE CAPS NEAR PINS
(ICH SUSPEND USB 3.3V PWR)ICH USB/VCCSUS3_3 BYPASS
AB8 AND AC8 OF SBPLACE CAPS NEAR PINSPLACEMENT NOTE:
(ICH LAN I/F BUFFER 3.3V PWR)ICH VCC_PAUX/VCCLAN3_3 BYPASS
3.56MM ON PRIMARY NEAR PIN AD2
3.56MM ON PRIMARY NEAR PINS AA7 ... AG19
V5, W2, OR W7
ICH VCCRTC BYPASS(ICH RTC 3.3V PWR)
ICH VCC3_3 BYPASS
PLACEMENT NOTE:PLACE C2509 NEAR PIN B27 OF SB
ICH VCC3_3 BYPASS
ICH VCC1_5_A/ARX BYPASS(ICH LOGIC&IO[ARX] 1.5V PWR)
(ICH LOGIC&IO[ATX] 1.5V PWR)
ICH VCCSUS3_3 BYPASS(ICH SUSPEND 3.3V PWR)
ICH V5REF_SUS BYPASS(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)
PLACEMENT NOTE:PLACE C2504 < 2.54MM OF PIN F6 OF SBON SECONDARY SIDE OR 3.56MM ON PRIMARY
ON SECONDARY SIDE OR 3.56MM ON PRIMARYPLACE C2503 < 2.54MM OF PIN AD17 OF SBPLACEMENT NOTE:
PLACE C2520 NEAR PIN E3 OF SB
ICH VCCDMIPLL BYPASS
SECONDARY SIDE OR 3.56MM ON PRIMARY
20%220UFPOLY2.5VSMB2
C25001
2
X5R16V10%0.1UF
402
C25101
2
0
402
0.1UF10%16VX5R
C25121
2
0
15%1/10W
MF-LF603
R25001 2
4.7UF20%6.3VCERM603
C25241
2
0.1UF10%16VX5R402
C25221
2
BAT54DWSOT-363
D25021
6
5
BAT54DWSOT-363
D25024
3
2
1206
0.28-OHML25071 2
0.1UF
402
10%16VX5R
C25031
2
0
X5R16V10%0.1UF
402
C25041
2
0
5%MF-LF1/16W402
10R2501
12
100-OHM-EMISM-3
L2500
1 2
0
0.1UF10%16VX5R402
C25051
2 X5R16V10%0.1UF
402
C25061
2
0.1UF16V10%X5R402
C25071
2
0.01UF10%16VCERM402
C25011
2603
10UF20%6.3VX5R
C25081
2
0
10%16VX5R402
0.1UFC25091
2
0
X5R40216V10%0.1UFC25111
2
0
0.1UF
402X5R16V10%
C25171
2
0
0.1UF10%16VX5R402
C25131
2
0
0
4026.3VCERM10%1UFC25141
2
0
0.1UF10%16VX5R402
C25201
2
402X5R16V10%0.1UFC25151
2
0
0
CASE-C2POLY20%2.5V330UFC25161
25%
1/16W402MF-LF100R2502
1
2
1UF10%6.3VCERM402
C25021
2402
0.1UF10%16VX5R
C25181
2
0
X5R16V10%0.1UF
402
C25191
2
0
0.1UF10%16V402X5R
C25211
2
0
X5R16V10%0.1UF
402
C25231
2
0
0.1UFX5R16V10%
402
C25251
2
0
X5R16V10%0.1UF
402
C25261
2 X5R16V10%0.1UF
402
C25271
2 X5R16V10%0.1UF
402
C25281
2
402
0.1UF10%16VX5R
C25291
2
0
402
0.1UF10%16VX5R
C25301
2
402
0.1UF10%16VX5R
C25341
2
0
402
0.1UF10%16VX5R
C25311
2
402
0.1UF10%16VX5R
C25321
2
0
402
0.1UF10%16VX5R
C25331
2
051-7099
10425
D
PP5V_S0_SB_V5REFVOLTAGE=5V
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.25MM
PP5V_S5_SB_V5REF_SUS
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5VMIN_LINE_WIDTH=0.3MM
=PP5V_S0_SB
=PP3V3_S5_SB
=PP3V3_S0_SB
=PP5V_S5_SB
PP3V3_S5_SB_RTC
=PP3V3_S0_SB_VCCLAN3_3
=PP1V5_S0_SB_VCC1_5_A
=PP3V3_S5_SB_VCCSUS3_3_USB
=PP1V5_S0_SB_VCCSATAPLL
=PP3V3_S0_SB_VCC3_3
=PP3V3_S0_SB_VCC3_3_PCI
=PP1V5_S0_SB_VCC1_5_A_ARX
=PP3V3_S0_SB_VCC3_3
=PP3V3_S5_SB_VCCSUS3_3
=PP1V5_S0_SB
=PP3V3_S5_SB_VCCSUS3_3
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
=PP3V3_S0_SB_VCC3_3_IDE
PP1V5_S0_SB_VCCDMIPLL_FVOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MMVOLTAGE=1.5V
PP1V5_S0_SB_VCCDMIPLL
=PP1V5_S0_SB_VCCUSBPLL
=PP1V05_S0_SB_CPU_IO
=PP3V3_S0_SB_3V3_1V5_VCCHDA
=PPVCORE_S0_SB
=PP1V5_S0_SB_VCC1_5_A_ATX
=PP1V5_S0_SB
PP1V5_S0_SB_VCC1_5_BVOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
26
63
63
63
63
63
63
63
24
63
63
63
63
25
63
63
25
25
63
25
63
63
63
24
63
63
63
63
24
24
24
63
23
22
63
21
24
24
24
24
24
24
24
24
24
25
24
24
24
24
24
21
24
24
24
25
22
IO
IO
IN
IN
IN
IN
IO
IO
IO
IO
IO
IO
IO
OUT
OUT IN
IN
OUT
IN OUT
IN
SYM_1
NCNC
IN
OUT
OUT
IO
IO
IO
IO
IO
IO
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
fault protection for RTC battery.NOTE: R2607 and D2600 form the double-
NCNC
Silk: "SYS RST"
Unbuffered
518S0226
NC
NC
RTC Battery Connector
SB RTC Crystal Circuit
it provides a set of padson the board to short orto solder a reset button.
1G00 used as small & cheap inverter
100-ohm on NB page
Linda Card represents 3 loads
Buffered
LIO represents X loads (2?)
This part is never stuffed,
NCNC
Initial resistor values are based on CRB,but may change after characterization.
Platform Reset Connections
MF-LF
5%
402
1/16W
20KR26001 2
0.1UF
402CERM10V20%
C2611 1
2
402CERM6.3V10%1UFC26051
2
100K
MF-LF402
5%1/16W
OMITR26981
2
1M
402MF-LF1/16W5%
R26061
2
10K
MF-LF402
5%1/16W
R26971
2
402
5%
MF-LF1/16W
1KR26072 1
12pF
CERM402
5%50V
C26081 2
12pF
50V5%
402CERM
C26091 2
SM-2
CRITICAL
32.768KY2600
24
13
0
402MF-LF1/16W5%
R26101 2
10M
402MF-LF1/16W
5%
R26091
2
CERM
0.1UF20%10V
402
C26801
2
100K5%1/16WMF-LF402
R26801
2
402
0
MF-LF1/16W5%
R26811 2
100
402MF-LF1/16W5%
R26831 2
0
1/16W5%
MF-LF402
R26841 2
0
402MF-LF1/16W5%
R26851 2
0
5%1/16WMF-LF402
R26871 2
0
402MF-LF1/16W5%
R26821 2
CRITICAL
F-RT-SM88460-0201J2600
3
4
1
2
402
ITP
5%1/16WMF-LF
1KR26961 2
MC74VHC1G00SC70-5
U2603
3
2
1
4
5
MC74VHC1G08SC70
U2680
3
2
1
4
5
SC70MC74VHC1G08
U2601
3
2
1
4
5
BAT54DWSOT-363
D2600
1
4
6
3
5 2
402MF-LF1/16W5%1.8KR26111
2
0.1UF
402CERM10V20%
C2607 1
2
402MF-LF1/16W
5%10K
R26121
2
10K5%1/16WMF-LF402
R26221
2
8.2KR2623 1 2
8.2KR2624 1 2
8.2KR2625 1 2
8.2KR2626 1 2
8.2KR2627 1 2
8.2KR2628 1 2
8.2KR2629 1 28.2KR2630 1 2
8.2KR2631 1 28.2KR2632 1 2
8.2KR2633 1 2
8.2KR2634 1 2
8.2KR2636 1 28.2KR2637 1 2
8.2KR2638 1 2
8.2KR2639 1 2
8.2KR2640 1 2
8.2KR2641 1 28.2KR2642 1 2
402
6.3V10%
CERM
1UFC26101
2
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
26
051-7099 D
104
SB Misc
PLT_RST_BUF_L
TPM_LRESET_L
ENET_RST_L
MAKE_BASE=TRUEPLT_RST_L
MAKE_BASE=TRUEVOLTAGE=3.3V
PP3V3_G3C_SB_RTC_D
SB_GPIO4
SB_GPIO2SB_GPIO3
INT_PIRQD_L
INT_PIRQB_LINT_PIRQC_L
PCI_REQ3_L
INT_PIRQA_L
PCI_REQ2_LPCI_REQ1_LPCI_REQ0_L
PCI_LOCK_LPCI_PERR_LPCI_DEVSEL_LPCI_SERR_LPCI_STOP_LPCI_TRDY_LPCI_IRDY_LPCI_FRAME_L
=PP3V3_S0_SB_PCIPP3V3_S5_SB_RTC
=PP3V42_G3H_SB_RTC
PPVBATT_G3C_RTC_RVOLTAGE=3.3V
=PP3V3_S0_SB_PM
VR_PWRGOOD_DELAY
ALL_SYS_PWRGDPM_SB_PWROK
=PP3V3_S0_RSTBUF
VR_PWRGD_CK410_LMAKE_BASE=TRUE
=PP3V3_S0_SB_PM
MAKE_BASE=TRUEPM_SYSRST_LXDP_DBRESET_L
SB_SM_INTRUDER_L
LIO_PLT_RESET_LSB_RTC_X1
DEBUG_RST_L
SMC_LRESET_L
PEG_RESET_L
NB_RST_IN_L
=PP3V3_S5_SB_PM
VR_PWRGD_CK410
CK410_PD_VTT_PWRGD_L
SB_RTC_RST_L
PPVBATT_G3C_RTCVOLTAGE=3.3V
SB_RTC_X1_R
SB_RTC_X2
25
47
63
40
40
40
40
40
40
40
40
40
24
63
57
62
63
23
45
49
23
33
56
37
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
63
21
63
26
14
47
23
63
57
26
5
21
5 21
5
47
65
14
11
23
21
21
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(Write: 0x16 Read: 0x17)
ICH7-M SMBus Connections
Top-CaseTop-Case SMBus Connections:
Right Temp - TMP105
(Write: 0x90 Read: 0x91)
Battery
U5800(MASTER)
J4900Trackpad
J2900(Write: 0xA4 Read: 0xA5)
(See Table)J5500
Left I/O SMBus Connections: Left I/O Board
ICH7-M
(Write: 0x52 Read: 0x53)
Left Temp - TMP105 (See Table)
(Write: 0x98 Read: 0x99)
CPU TempADT7461: U1001
J5400(See Table)
SMC "B" SMBus Connections
U5800SMC
(MASTER)
LIO - TMP105(Write: 0x90 Read: 0x91)
SMC
(Write: 0x92 Read: 0x93)
Left ALS - TSL2561
(Write: 0x90 Read: 0x91)
J4900
(Write: 0x30 Read: 0x31)
(Write: 0x98 Read: 0x99)
MAX6695: U6100
(MASTER)U2100 CY28445-5: U3301
(Write: 0xD2 Read: 0xD3)
Clock Chip
J2800
U5800
TMP105: J4930
GPU Temp
ADT7461: U6150Right-Side Temp
Ambient Thermal
(MASTER)U5800
J8250
SMC "Battery B" SMBus Connections
SMC
NOTE: SMC RMT bus remains powered and may be active in S3 state
SMC "Battery A" SMBus Connections
U5800(MASTER)
SMC "A" SMBus Connections
(MASTER)
SMC "0" SMBus Connections
(See Table)
Left I/O Board
ExpressCard Slot(Address determined by ARP)
(Write: 0x92 Read: 0x93)
Left I/O SMBus Connections:
(Write: 0x72 Read: 0x73)
(Write: 0x70 Read: 0x71)
M35 - TMP105
Trackpad I2C Connections:
U1 - Trackpad Controller
U2 - Keyboard Controller
SMC
SO-DIMM "A"
SMC
(Write: 0xA0 Read: 0xA1)
SO-DIMM "B"
MF-LF402
1/16W5%
4.7KR27001
2MF-LF402
5%1/16W
4.7KR27011
2
1/16W5%
402MF-LF
4.7KR27801
2
1/16W5%
402MF-LF
4.7KR27811
2
100K5%1/16W
402MF-LF
R27911
2
100K1/16W
5%
402MF-LF
R27901
2
402MF-LF1/16W5%4.7KR27611
2
5%1/16W
402MF-LF
4.7KR27601
2
1/16WMF-LF402
5%4.7KR27711
2
1/16W
402MF-LF
5%4.7K
R27701
2
402MF-LF1/16W5%4.7KR27511
2MF-LF
402
5%1/16W
4.7KR27501
2
M1 SMBus ConnectionsSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
10427
D051-7099
=PP3V3_S0_SMBUS_SB
MAKE_BASE=TRUESMBUS_SB_SCL
MAKE_BASE=TRUESMBUS_SB_SDA
=PP3V3_S3_SMBUS_SMC_A_S3
SMBUS_SMC_A_S3_SDAMAKE_BASE=TRUE
MAKE_BASE=TRUESMBUS_SMC_A_S3_SCL
=PP3V3_S0_SMBUS_SMC_0_S0
MAKE_BASE=TRUESMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUESMBUS_SMC_0_S0_SDA
=PP3V42_G3H_SMBUS_SMC_BSA
SMBUS_SMC_BSA_SDAMAKE_BASE=TRUE
MAKE_BASE=TRUESMBUS_SMC_BSA_SCL
=PP3V3_S0_SMBUS_SMC_B_S0
SMBUS_SMC_B_S0_SDAMAKE_BASE=TRUE
SMBUS_SMC_B_S0_SCLMAKE_BASE=TRUE
=SMBUS_ATS_SCL
=I2C_SODIMMA_SDA
=PP3V3_S0_SMBUS_SMC_BSB
MAKE_BASE=TRUESMBUS_SMC_BSB_SCL
SMBUS_SMC_BSB_SDAMAKE_BASE=TRUE
=SMBUS_BATT_SCLSMB_BSA_CLK
SMB_BSA_DATA
SMB_BSB_CLK
=SMBUS_RSTHMSNS_SCL
=SMBUS_RSTHMSNS_SDA
=SMBUS_GPUTHMSNS_SCL
SMB_0_S0_CLK
SMB_0_S0_DATA
=SMBUS_ATS_SDA
SMB_CK410_CLK
SMB_CK410_DATA
=I2C_SODIMMA_SCL
SMB_DATA
SMB_CLK
=SMBUS_GPUTHMSNS_SDA
SMB_BSB_DATA
=SMBUS_TOPCASE_SDA
SMB_A_S3_CLK
SMB_A_S3_DATA
SMB_B_S0_CLK
SMB_B_S0_DATA
=SMBUS_LIO_SMC_SDA
SMB_THRM_CLK
=SMBUS_TOPCASE_SCL
=SMBUS_LIO_SMC_SCL
SMB_THRM_DATA
=SMBUS_LIO_SB_SDA
=SMBUS_LIO_SB_SCL
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
=I2C_TRACKPAD_SCL
=I2C_TRACKPAD_SDA
=SMBUS_BATT_SDA
43
64
43
45
45
45
45
64
63
63
63
63
63
5
28
63
5
47
47
50
50
50
47
47
5
33
33
28
23
23
50
47
43
47
47
47
47
5
10
43
5
10
5
5
29
29
43
43
5
VSS2
DQS0*
DQ5
VSS0
DQ4
VSS5
DQ6
VSS29
DM0
VSS7
DM1
DQ7
VDD1
DQ30
DQ23
VSS22
NC/ODT1
RAS*
SA1
SA0
VSS58
DQ63
DQ62
VSS56
DQS7
DQS7*
VSS54
DQ60
VSS52
DQ54
VSS50
VSS48
CK1*
CK1
VSS46
DQ53
DQ52
VSS44
VSS42
DQS5
DQS5*
VSS39
DQ45
DQ44
VSS37
DQ39
DQ38
VSS35
DM4
VSS34
DQ37
DQ36
VSS32
NC3
VDD11
NC/A13
ODT0
VDD9
S0*
BA1
VDD7
A0
A2
A4
VDD5
A6
A7
A11
VDD3
NC/A14
NC/A15
NC/CKE1
VSS30
DQ31
DQS3
DQ29
DQ28
VSS24
DQ22
DM2
NC0
VSS19
DQ21
DQ20
VSS17
VSS15
DQ15
DQ14
VSS13
CK0*
CK0
VSS11
DQ13
DQ12
DQ47
DQ46
DQ61
DQ55
DM6
VDDSPD
SCL
SDA
VSS57
DQ59
DQ58
VSS55
DM7
VSS53
DQ56
VSS51
DQ50
VSS49
DQS6*
VSS47
NC_TEST
VSS45
DQ49
DQ48
VSS43
VSS41
DM5
VSS40
DQ41
VSS38
DQ35
VSS36
DQS4
DQS4*
VSS33
DQ33
DQ32
VSS31
VDD10
NC/S1*
CAS*
VDD8
WE*
BA0
A10/AP
VDD6
A1
A3
A5
VDD4
A8
A9
A12
VDD2
BA2
NC2
VDD0
CKE0
DQ27
DQ26
VSS27
NC1
DM3
DQ25
DQ24
VSS23
DQ19
DQ18
VSS21
DQS2
DQS2*
VSS18
DQ17
DQ16
VSS16
VSS14
DQ11
DQ10
VSS12
DQS1
DQS1*
DQ9
DQ8
VSS8
DQ3
DQ2
VSS6
DQS0
VREF
DQ34
DQ40
DQ42
DQ43
DQS6
DQ51
DQ57
KEY
VSS9
DQ1
VSS4
DQ0
VSS1
DQS3*
VSS26
VSS28
VSS25
VSS10
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NC
DDR2 Bypass Caps(For return current)
ADDR=0xA0(WR)/0xA1(RD)
NC
NC
NC
NC
516S0382
- =PPSPD_S0_MEM (2.5V - 3.3V)- =PP1V8_S3_MEM
Signal aliases required by this page:
BOM options provided by this page:(NONE)
Power aliases required by this page:
NC
- =I2C_SODIMMA_SCL- =I2C_SODIMMA_SDA
Page Notes
NOTE: This page does not supply VREF.The reference voltage must be providedby another page.
"Lower" (surface-mount) slot
0.1uF
CERM402
20%10V
C28131
2
0.1uF
CERM402
20%10V
C28121
2
10UF
X5R603
20%6.3V
C28091
2
0.1uF
CERM402
20%10V
C28111
2
10UF
X5R603
20%6.3V
C28081
2
0.1uF
CERM402
20%10V
C28101
2
0.1uF
CERM402
20%10V
C28191
2
0.1uF
CERM402
20%10V
C28181
2
0.1uF
CERM402
20%10V
C28171
2
0.1uF
CERM402
20%10V
C28161
2
0.1uF
CERM402
20%10V
C28211
2
0.1uF
CERM402
20%10V
C28201
2
0.1uF
CERM402
20%10V
C28151
2
0.1uF
CERM402
20%10V
C28141
2
0.1uF
CERM402
20%10V
C28001
2
DDR2-SODIMM-DUAL
F-RT-SM
CRITICAL
J2800
102A
105A
90A89A
101A
100A99A
98A97A
94A
92A
93A
91A
107A
106A
85A
113A
30A
32A
164A
166A
79A
10A
26A
52A
67A
130A
147A
170A
185A
5A
35A
37A
20A
22A
36A
38A
43A
45A
55A
57A
7A
44A
46A
56A
58A
61A
63A
73A
75A
62A
64A
17A
74A
76A
123A
125A
135A
137A
124A
126A
134A
136A
19A
141A
143A
151A
153A
140A
142A
152A
154A
157A
159A
4A
173A
175A
158A
160A
174A
176A
179A
181A
189A
191A
6A
180A
182A
192A
194A
14A
16A
23A
25A
13A
11A
31A
29A
51A
49A
70A
68A
131A
129A
148A
146A
169A
167A
188A
186A
201
202
203
204
116A
86A
84A
80A
119A
115A
50A
69A
83A
120A
163A
114A
108A
110A
198A
200A
197A
195A
81A
117A 118A
82A
87A 88A
95A 96A
103A 104A
111A 112A
199A
1A 2A
27A 28A
33A 34A
39A 40A
41A 42A
47A 48A
3A
53A 54A
59A 60A
65A 66A
71A 72A
77A
8A
78A
121A 122A
127A 128A
132A
133A
138A
139A
144A
145A
149A 150A
155A 156A
161A 162A
165A
168A
171A
9A
172A
177A 178A
183A 184A
187A
190A
193A
196A
12A
15A
18A
21A
24A
109A
2.2uF20%
603CERM16.3V
C2801 1
2
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
DDR2 SO-DIMM Connector A
051-7099 D
10428
MEM_A_DQ<56>
MEM_A_DQS_N<7>
MEM_A_DQ<63>
MEM_A_DQS_P<7>
MEM_A_DQ<62>
MEM_A_DQ<57>MEM_A_DQ<60>
MEM_A_DQ<55>
MEM_A_DQ<45>MEM_A_DQ<43>
MEM_A_DQ<61>
MEM_A_DQ<59>
MEM_A_DQS_N<1>MEM_A_DQS_P<1>
MEM_A_DQ<10>
MEM_A_DM<1>
MEM_A_DQ<15>MEM_A_DQ<9>
MEM_A_DQ<3>
MEM_A_DQ<28>
MEM_A_DQ<26>
MEM_A_DQS_P<3>
MEM_A_DQ<44>
DIMM_OVERTEMP_L
MEM_A_DQ<49>MEM_A_DQ<52>
MEM_A_DQS_P<6>MEM_A_DQS_N<6>
MEM_A_DQ<54>
MEM_A_DQ<47>
MEM_A_DM<5>
MEM_CLK_N<1>
MEM_A_DQ<42>MEM_A_DQ<40>
MEM_A_DQ<36>MEM_A_DQ<32>
MEM_A_DM<4>
MEM_A_DQ<34>MEM_A_DQ<38>
MEM_A_A<13>
MEM_CS_L<0>
MEM_A_A<2>MEM_A_A<4>
MEM_A_A<6>MEM_A_A<7>
MEM_A_A<14>MEM_A_A<15>
MEM_A_DQ<21>
MEM_A_DQ<0>
MEM_CLK_N<0>MEM_CLK_P<0>
MEM_A_DQ<8>
=I2C_SODIMMA_SCL=I2C_SODIMMA_SDA
MEM_A_DQ<48>MEM_A_DQ<53>
MEM_A_DM<6>
MEM_A_DQ<50>MEM_A_DQ<51>
MEM_A_DQ<46>MEM_A_DQ<41>
MEM_A_DQS_P<5>MEM_A_DQS_N<5>
MEM_A_DQ<58>
MEM_A_DM<7>
MEM_A_DQ<33>MEM_A_DQ<37>
MEM_A_DQS_P<4>MEM_A_DQS_N<4>
MEM_A_DQ<39>MEM_A_DQ<35>
MEM_ODT<1>
MEM_A_DQ<7>
MEM_A_WE_LMEM_A_BS<0>MEM_A_A<10>
MEM_A_A<1>MEM_A_A<3>MEM_A_A<5>
MEM_A_A<8>MEM_A_A<9>MEM_A_A<12>
MEM_A_BS<2>
MEM_CKE<0>
MEM_A_DQ<30>MEM_A_DQ<27>
MEM_A_DM<3>
MEM_A_DQ<25>
MEM_A_DQ<16>MEM_A_DQ<20>
MEM_A_DQS_P<2>MEM_A_DQS_N<2>
MEM_A_DQ<18>MEM_A_DQ<19>
MEM_A_DQ<6>
MEM_A_DQS_P<0>MEM_A_DQS_N<0>
MEM_A_DQ<4>MEM_A_DQ<5>
MEM_A_DQ<11>
MEM_A_DQ<14>
MEM_CKE<1>
MEM_A_BS<1>
MEM_A_DQ<1>
MEM_A_DQ<22>
MEM_A_DM<2>
MEM_A_DQ<17>
MEM_A_DQ<29>MEM_A_DQ<24>
MEM_A_DQ<31>
MEM_A_A<11>
MEM_A_A<0>
MEM_A_RAS_L
MEM_ODT<0>MEM_CS_L<1>MEM_A_CAS_L
MEM_A_DQ<23>
MEM_A_DQS_N<3>
MEM_A_DQ<12>MEM_A_DQ<13>
MEM_A_DQ<2>
=PP1V8_S3_MEM
=PP1V8_S3_MEM
=PPSPD_S0_MEM
=PP1V8_S3_MEM
MEM_CLK_P<1>
MEM_A_DM<0>
MEM_VREF
63
63
63
48
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30 30
30
30
30
30
30
30
30
29
29
63
29
32
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
29
15
15
15
15
15
15
15
14
15
15
15
15
15
15
15
15
14
15
15
15
15
6
6
15
15
14
14
15
27
27
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
14
15
15
15
15
15
15
15
15
15
15
15
14
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
14
15
15
15
15
15
15
15
15
15
15
15
14
14
15
15
15
15
15
15
28
28
29
28
14
15
29
VSS7
VSS12
VSS9
KEY
DQ57
DQ51
DQS6
DQ43
DQ42
DQ40
DQ34
DQ1
DQ0
VSS1
DQS0*
DQS0
VSS6
DQ2
DQ3
DQ8
DQ9
VSS10
DQS1*
DQS1
DQ10
DQ11
VSS14
VSS16
DQ16
DQ17
VSS18
DQS2*
DQS2
VSS21
DQ18
DQ19
VSS23
DQ24
DQ25
VSS25
DM3
NC1
VSS27
DQ26
DQ27
VSS29
CKE0
VDD0
NC2
BA2
VDD2
A12
A9
A8
VDD4
A5
A3
A1
VDD6
A10/AP
BA0
WE*
VDD8
CAS*
NC/S1*
VDD10
NC/ODT1
VSS31
DQ32
DQ33
VSS33
DQS4*
DQS4
VSS36
DQ35
VSS38
DQ41
VSS40
DM5
VSS41
VSS43
DQ48
DQ49
VSS45
NC_TEST
VSS47
DQS6*
VSS49
DQ50
VSS51
DQ56
VSS53
DM7
VSS55
DQ58
DQ59
VSS57
SDA
SCL
VDDSPD
DM6
DQ55
DQ61
DQ46
DQ47
DQ12
DM1
DM0
DQ7
DQ13
VSS11
CK0
CK0*
VSS13
DQ14
DQ15
VSS15
VSS17
DQ20
DQ21
VSS19
NC0
DM2
VSS22
DQ22
DQ23
VSS24
DQ28
DQ29
VSS26
DQS3*
DQS3
VSS28
DQ30
DQ31
VSS30
NC/CKE1
VDD1
NC/A15
NC/A14
VDD3
A11
A7
A6
VDD5
A4
A2
A0
VDD7
BA1
RAS*
S0*
VDD9
ODT0
NC/A13
VDD11
NC3
VSS32
DQ36
DQ37
VSS34
DM4
VSS35
DQ38
DQ39
VSS37
DQ44
DQ45
VSS39
DQS5*
DQS5
VSS42
VSS44
DQ52
DQ53
VSS46
CK1
CK1*
VSS48
VSS50
DQ54
VSS52
DQ60
VSS54
DQS7*
DQS7
VSS56
DQ62
DQ63
VSS58
SA0
SA1
DQ5
VSS2
VREF
VSS4
VSS8
VSS0
DQ4
VSS5
DQ6
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONEADDR=0xA4(WR)/0xA5(RD)
Resistor prevents pwr-gnd short
(For return current)DDR2 Bypass Caps
NC
NC
NC
NC
NC
BOM options provided by this page:
- =PPSPD_S0_MEM (2.5V - 3.3V)- =PP1V8_S3_MEMPower aliases required by this page:
(NONE)
Signal aliases required by this page:
NC
Page Notes
- =I2C_SODIMMB_SCL- =I2C_SODIMMB_SDA
by another page.The reference voltage must be providedNOTE: This page does not supply VREF.
516-0140
"Upper" (thru-hole) slot
10V0.1uF
CERM402
20%
C29131
210V0.1uF
CERM402
20%
C29121
2
6.3V20%
603X5R
10UFC29091
2
10V0.1uF
CERM402
20%
C29111
2
6.3V20%
603X5R
10UFC29081
2
10V0.1uF
CERM402
20%
C29101
2
10V0.1uF
CERM402
20%
C29191
210V0.1uF
CERM402
20%
C29181
2
0.1uF
CERM402
20%10V
C29171
210V0.1uF
CERM402
20%
C29161
2
10V0.1uF
CERM402
20%
C29211
2
0.1uF10VCERM402
20%
C29201
2
10V0.1uF
CERM402
20%
C29151
210V0.1uF
CERM402
20%
C29141
2
402MF-LF1/16W5%10KR29001
2
CRITICAL
DDR2-SODIMM-DUAL
F-RT-TH1J2900
102B
105B
90B89B
101B
100B99B
98B97B
94B
92B
93B
91B
107B
106B
85B
113B
30B
32B
164B
166B
79B
10B
26B
52B
67B
130B
147B
170B
185B
5B
35B
37B
20B
22B
36B
38B
43B
45B
55B
57B
7B
44B
46B
56B
58B
61B
63B
73B
75B
62B
64B
17B
74B
76B
123B
125B
135B
137B
124B
126B
134B
136B
19B
141B
143B
151B
153B
140B
142B
152B
154B
157B
159B
4B
173B
175B
158B
160B
174B
176B
179B
181B
189B
191B
6B
180B
182B
192B
194B
14B
16B
23B
25B
13B
11B
31B
29B
51B
49B
70B
68B
131B
129B
148B
146B
169B
167B
188B
186B
201
202
116B
86B
84B
80B
119B
115B
50B
69B
83B
120B
163B
114B
108B
110B
198B
200B
197B
195B
81B
117B 118B
82B
87B 88B
95B 96B
103B 104B
111B 112B
199B
1B 2B
27B 28B
33B 34B
39B 40B
41B 42B
47B 48B
3B
53B 54B
59B 60B
65B 66B
71B 72B
77B
8B
78B
121B 122B
127B 128B
132B
133B
138B
139B
144B
145B
149B 150B
155B 156B
161B 162B
165B
168B
171B
9B
172B
177B 178B
183B 184B
187B
190B
193B
196B
12B
15B
18B
21B
24B
109B
0.1uF
CERM402
20%10V
C29001
2
2.2uF20%
603CERM16.3V
C2901 1
2
10429
051-7099 D
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
DDR2 SO-DIMM Connector B
MEM_B_DQ<1>
MEM_CLK_N<3>
MEM_B_DQ<0>
=PP1V8_S3_MEM
=PP1V8_S3_MEM
MEM_B_DQ<20>
=PP1V8_S3_MEM
MEM_B_DQ<27>
MEM_B_A<15>
MEM_B_DQ<31>MEM_B_DQ<30>
MEM_B_DQ<26>
MEM_B_DQ<7>
MEM_B_DQ<5>
MEM_B_DQ<2>
MEM_B_DQ<3>MEM_B_DQ<6>
MEM_B_DQ<4>
MEM_CLK_P<3>
MEM_B_DM<0>
MEM_B_DQ<10>MEM_B_DQ<13>
MEM_B_DQS_P<1>MEM_B_DQS_N<1>
MEM_B_DQ<18>MEM_B_DQ<22>
DIMM_OVERTEMP_L
MEM_B_DQS_P<0>
MEM_B_DQ<8>
MEM_B_DQ<59>MEM_B_DQ<58>MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_CLK_P<2>
MEM_B_DM<7>
MEM_B_DQ<56>MEM_B_DQ<60>MEM_B_DQ<57>MEM_B_DQ<61>
MEM_B_DQ<47>
MEM_B_DQS_N<7>
MEM_B_DQS_N<6>MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
MEM_B_A<5>
MEM_CKE<3>
MEM_B_A<14>
MEM_B_DM<3>
MEM_B_DQ<19>
MEM_B_DQ<11>MEM_B_DQ<9>
MEM_B_BS<1>
MEM_B_A<0>MEM_B_A<2>MEM_B_A<4>
MEM_B_A<6>MEM_B_A<7>MEM_B_A<11>
MEM_B_DQS_P<3>MEM_B_DQS_N<3>
MEM_B_DQ<28>
MEM_B_DQ<16>MEM_B_DQ<17>
MEM_B_DM<2>
MEM_B_DQ<12>
MEM_B_DQ<32>
MEM_B_DQ<55>
MEM_CLK_N<2>
MEM_B_DQ<46>
MEM_B_DQS_P<5>MEM_B_DQS_N<5>
MEM_B_DQ<45>MEM_B_DQ<44>
MEM_B_DQ<39>MEM_B_DQ<38>
MEM_B_DM<4>
MEM_B_DQ<37>
MEM_B_A<13>MEM_ODT<2>
MEM_CS_L<2>MEM_B_RAS_L
MEM_B_DQ<42>
MEM_B_DQ<49>MEM_B_DQ<52>
MEM_B_DM<6>
MEM_B_DQ<51>MEM_B_DQ<54>
MEM_B_DQ<43>
MEM_B_DM<5>
MEM_B_DQ<41>MEM_B_DQ<40>
MEM_B_DQ<35>MEM_B_DQ<34>
MEM_B_DQS_P<4>MEM_B_DQS_N<4>
MEM_B_DQ<33>MEM_B_DQ<36>
MEM_ODT<3>
MEM_CS_L<3>MEM_B_CAS_L
MEM_B_WE_LMEM_B_BS<0>MEM_B_A<10>
MEM_B_A<1>MEM_B_A<3>
MEM_B_A<8>MEM_B_A<9>MEM_B_A<12>
MEM_B_BS<2>
MEM_CKE<2>
MEM_B_DQ<25>
MEM_B_DQ<24>MEM_B_DQ<29>
MEM_B_DQ<23>
MEM_B_DQS_P<2>MEM_B_DQS_N<2>
MEM_B_DQ<21>
MEM_B_DQS_N<0>
MEM_B_DQ<14>MEM_B_DM<1>
MEM_B_DQ<15>
=PPSPD_S0_MEM
=I2C_SODIMMB_SCL=I2C_SODIMMB_SDA
MEM_B_DQ<48>MEM_B_DQ<53>
MEM_B_DQ<50>
SODIMM_A_SA1
=PPSPD_S0_MEM
MEM_VREF
63
63 63
63
63
29
29 29
48
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
29
29
32
15
14
15
28
28
15
28
15
6
15
15
15
15
15
15
15
15
15
14
15
15
15
15
15
15
15
28
15
15
15
15
15
15
14
15
15 15
15 15
15
15
15
15
15
15
14
6
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
14
15
15
15
15
15
15
15
15
15
15
14
14
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
14
14
15
15
15
15
15
15
15
15
15
15
14
15
15
15
15
15
15
15
15
15
15
15
28
27
27
15
15
15
28
28
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Ensure CS_L and ODT resistors are close to SO-DIMM connector
One cap for each side of every RPAK, one cap for every two discrete resistors
402
10V20%
CERM
0.1uFC30511
2
0.1uF
402CERM10V20%
C30531
2
0.1uF
CERM10V20%
402
C30521
2
CERM
0.1uF20%10V
402
C30501
2
20%10VCERM402
0.1uFC30551
2
0.1uF
402CERM10V20%
C30571
2
20%10VCERM402
0.1uFC30591
2
0.1uF20%
CERM402
10V
C30581
2
402CERM10V20%0.1uFC30561
2
0.1uF
402CERM10V20%
C30541
2
0
1
2
3
5
4
6
7
8
9
10
11
12
13
0
2
1
29 15
29 15
29 15
29 15
29 15
SM-LF1/16W5%56RP3058 3 6
56SM-LF1/16W5%
RP3058 4 5
56SM-LF1/16W5%
RP3032 2 7 5% SM-LF1/16W56RP3032 1 8
1/16W SM-LF5%56RP3052 2 7
565% 1/16W SM-LF
RP3050 1 8
565% 1/16W SM-LF
RP3054 1 8
1/16W5% SM-LF56RP3056 1 8 5% 1/16W SM-LF56RP3005 1 8 SM-LF1/16W5%56RP3056 4 5
SM-LF1/16W5%56RP3058 2 7 SM-LF1/16W5%56RP3058 1 8 SM-LF1/16W5%56RP3054 4 5 SM-LF1/16W5%56RP3054 3 6 SM-LF1/16W5%56RP3052 1 8 SM-LF1/16W5%56RP3054 2 7 SM-LF1/16W5%56RP3052 3 6 SM-LF1/16W5%56RP3050 4 5 SM-LF1/16W5%56RP3050 3 6 SM-LF1/16W5%56RP3005 2 7
SM-LF1/16W5%56RP3050 2 7
SM-LF1/16W5%56RP3056 3 6
1/16W5% SM-LF56RP3056 2 7
SM-LF1/16W5%56RP3052 4 5
1/16W5% MF-LF 40256R3000 1 2
402MF-LF5% 1/16W56R3002 1 2
5% MF-LF 4021/16W56R3001 1 2
5% MF-LF 4021/16W56R3003 1 2
565% 1/16W SM-LF
RP3005 4 5
56SM-LF1/16W5%
RP3030 4 5
565% 1/16W SM-LF
RP3030 3 6
56SM-LF1/16W5%
RP3010 1 8
56SM-LF1/16W5%
RP3010 2 7
5% 1/16W SM-LF56RP3034 2 7
5% 1/16W SM-LF56RP3030 1 8 5% 1/16W SM-LF56RP3032 3 6 5% 1/16W56
SM-LFRP3030 2 7
5% 1/16W56
SM-LFRP3005 3 6
5% 1/16W56
SM-LFRP3034 1 8 5% 1/16W SM-LF
56RP3034 4 5
5% 1/16W56
SM-LFRP3032 4 5
SM-LF5% 1/16W56RP3036 1 8
5% 1/16W56
SM-LFRP3034 3 6
5% 1/16W56
SM-LFRP3036 3 6
56SM-LF1/16W5%
RP3036 4 5
56SM-LF1/16W5%
RP3036 2 7
56SM-LF1/16W5%
RP3010 4 5
565% 1/16W SM-LF
RP3010 3 6
402MF-LF5% 1/16W56R3010 1 2
561/16W5% MF-LF 402
R3011 1 2
402MF-LF5% 1/16W56R3012 1 2
402MF-LF1/16W56
5%R3013 1 2
0
1
0
1
1
0
2
0
1
2
3
4
5
6
7
10
11
9
8
13
12
29 28 14
29 28 14
28 15
28 15
28 15
28 15
28 15
2
3
2
3
20%10VCERM402
0.1uFC30391
2
0.1uF20%
CERM402
10V
C30381
2
20%10VCERM402
0.1uFC30331
2402
20%10VCERM
0.1uFC30321
2
402CERM10V20%0.1uFC30311
2CERM
0.1uF20%10V
402
C30301
2
0.1uF10V20%
402CERM
C30111
2
0.1uF
402
20%10VCERM
C30101
2
20%
CERM402
0.1uF10V
C30071
2
0.1uF
402CERM10V20%
C30051
2
20%10VCERM402
0.1uFC30021
2402CERM10V20%0.1uFC30001
2
0.1uF
402CERM10V20%
C30371
2402CERM10V20%0.1uFC30361
2
20%10VCERM402
0.1uFC30351
2
0.1uF
402CERM10V20%
C30341
2
0
1
2
3
29 28 14
30 104
D051-7099
Memory Active TerminationSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
MEM_B_A<13..0>
MEM_B_BS<2..0>
MEM_CS_L<3..0>
MEM_CKE<3..0>
MEM_A_BS<2..0>
MEM_A_A<13..0>
MEM_ODT<3..0>
MEM_B_WE_L
MEM_A_WE_LMEM_A_CAS_LMEM_A_RAS_L
MEM_B_CAS_LMEM_B_RAS_L
=PP0V9_S0_MEM_TERM63
VREF
VTT
GND
VTT_IN
ENVTTS
VDDQ VCC
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(NONE)
(NONE)
Power aliases required by this page:
Signal aliases required by this page:
BOM options provided by this page:
- =PP5V_S0_MEMVTT- =PP1V8_S0_MEMVTT- =PP0V9_S0_MEMVTT_LDO
Page Notes
Okay to turn off 5V andleave 1.8V powered in S3.
DDR2 Vtt Regulator
If power inputs are not S0,MEMVTT_EN can be used todisable MEMVTT in sleep.
6.3V20%
X5R603
10uFC3101 1
2
CRITICAL
MSOP-8BD3533FVMU3100
2
1
65
4
8
7
3
MEMVTT_EN_PU
1K
402MF-LF1/16W5%
R31001
2
6.3V
SMC-LFPOLY
20%150UFC3105
603X5R
20%10uF6.3V
C31021
2
CERM1
20%6.3V
2.2uF
603
C3104 1
2
220
5%1/16WMF-LF402
R310412
10%16VX5R
0.1uF
402
C31031
2
6.3V10%1uF
CERM402
C31001
2
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
Memory Vtt Supply
051-7099 D
10431
=PP1V8_S0_MEMVTT
MEMVTT_EN
MEMVTT_VREF
=PP5V_S0_MEMVTT
VOLTAGE=1.8VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmPP1V8_S0_MEMVTT_VDDQ
=PP0V9_S0_MEMVTT_LDO
63
63
63
V+
V-
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
CRITICAL
MAX4236EUTTSOT23-6-LF
U3200
3
4
1
5
6
2
20%0.1UF
402
10VCERM
C3200 1
2
CERM402
220pF25V5%
C3205 1
2
10K1/16W
1%
402MF-LF
R32061
2
10K
MF-LF402
1%1/16W
R32051
2
100K
MEMVREF_S3
MF-LF402
5%1/16W
R32021
2
5%1/16WMF-LF402
0
MEMVREF_S0
R320312
32 104
D051-7099
DDR2 VRefSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
MEMVREF_SHDN_L
=PP3V3_S3_MEMVREF
=MEMVREF_EN
MEM_VREFMEM_VREF_NB_0MEM_VREF_NB_1
MEMVREF_UNBUFMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0.9V
=PP1V8_S3_MEMVREF
MIN_NECK_WIDTH=0.15 mmVOLTAGE=0.9V
MIN_LINE_WIDTH=0.2 mm
MAKE_BASE=TRUE
MEMVREF_OUT 29
63
62
28
14
14
63
VTT_PWRGD*/PD
DOT96T/27MHZ_NON-SPREAD
SRCT_0/LCD100MT
CPUC2_ITP/SRCC_10
VDD48
XIN
VDD_PCI1
VDD_SRC0
VDD_REF
VDD_SRC1
VDD_SRC2
VDD_SRC3
REF1/FCTSEL0
REF0/FSC
FSA/48M
DOT96C/27MHZ_SPREAD
CLKREQ_8*
SRCT_8
SRCC_8
SRCT_7
SRCC_7
CLKREQ_6*
CPUT2_ITP/SRCT_10
IREF
SDATA
SCLK
VSS_REF
VSS_PCI1
VSS_PCI0
VSS_CPU
VSS48
VSS_SRC
PCIF1
PCI1
SRCT_5
THRML_PAD
PCI4
PCI2
FSB
CLKREQ_4*
SRCC_5
SRCC_4
SRCT_4
SRCT_3
CLKREQ_3*
SRCC_3
SRCC_2
SRCT_2
SRCC_1
CLKREQ_1*
SRCT_1
SRCC_0/LCD100MC
CPUC1
CPUT1
CPUC0
CPUT0
PCI_STP*
CPU_STP*
SRCC_6
CLKREQ_5*
SRCT_6
PCIF0/ITP_SEL
PCI5/FCTSEL1
PCI3
XOUT
VDDA
VSSA
VDD_PCI0
VDD_CPU
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
IO
OUT
IN
IO
IO
OUT
OUT
IN
IN
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NEED TO CHECK CAP VALUE
(SMC LPC 33MHZ)
(PORT80 LPC 33MHZ)
(ICH7M PCI 33MHZ)(PULL UP PIN 68 TO ENABLE ITP HOST CLK)
(NO USED)
(ICH SM BUS)
0
(INT PU)
(ICH7M,SIO,LPC REF. 14.318MHZ)
(INT PD)
(GMCH G_CLKIN 100 MHZ )
(FROM ICH7 GPIO18 STPPCI* )(FROM ICH7 GPIO20 STPCPU* )
(GMCH HOST 133/167MHZ)
(ITP HOST 133/167MHZ)
(GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)
PROTO TO REMOVE 100M FROM SIGNAL NAME)(SIGNAL NAME WILL BE CHANGED POST(INT PU)
(CPU HOST 133/167MHZ)
(NOT USED )
(INT PD)
(INT PU)
(INT PD)
(INT PU)
(INT PU)
PIN 6
* FOR EXT. GRAPHIC SYSTEM
* FOR INT. GRAPHIC SYSTEM
SRCT0SRCT0
DOT96CDOT96TDOT96T
PIN 7 PIN 10 PIN 11100MC_SST
FCTSEL100
0 111 1 OFF LOW
27M NONSPREAD
27MSPREAD
TBD
DOT96C 100MT_SSTSRCT0
SRCC0SRCC0SRCC0
FCTSEL0
(INT PU)
(ICH SATA 100 MHZ)
(TPM LPC 33MHZ)
(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)(EACH POWER PIN PLACED ONE 0.1UF)
(INT PU)(INT PU)
(GPU PCI-E 100 MHZ )
NEED TO DECIDE THE CLKREQ CONNECTION,TO GPIO?(ICH7M DMI 100 MHZ )
(FROM ICH7 GPIO35)
(FROM GMCH CLK_REQ*)
(WIRELESS PCI-E 100 MHZ )
(GIGA LAN PCI-E 100 MHZ )
(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)
(FROM CPU VCORE PWR GOOD)(ICH7M USB 48MHZ)
(FOR PCI-E CARD)
(FW PCI 33MHZ)
603X5R
10UF20%6.3V
C33091
2
FERR-120-OHM-1.5A
0402
L33021 2
0.1UF10%X5R16V402
C33051
2 16VX5R402
10%0.1UFC33061
2
16VX5R
0.1UF10%
402
C33071
2
0.1UF10%
40216VX5R
C33081
2
CY284455
CRITICAL
QFN
OMIT
U3301
9
59
20
60
25
34
55
44
41
36
45
42
37
76
4
8
40
5758636465
56
681
5453
4748
11
14
16
19
22
24
27
30
32
10
13
15
18
21
23
26
29
33
69
3 43
61
67
49
12
17
28
35
38
5
46
6266
52
31
39
2
5150
50V402CERM5%18pFC33901
250V5%CERM402
18pFC33891
2
MF-LF1%475
4021/16W
R33001
2
20%10UF6.3VX5R603
C33121
2 16V0.1UF
402X5R10%
C33111
2
402
10%16VX5R
0.1UFC33041
2X5R16V402
0.1UF10%
C33031
2
0.1UF10%16VX5R402
C33021
2402X5R16V0.1UF10%
C33011
2
1UF6.3VCERM10%
402
C33101
2
10UF
6036.3V20%X5R
C33161
210%X5R16V402
0.1UFC33151
2
FERR-120-OHM-1.5A
0402
L33011 2
1UF10%CERM6.3V402
C33141
2
402MF-LF1/16W5%
2.2R33021 2
4021/16W5%
MF-LF
1R33031 2
6036.3V20%10UFX5R
C33171
2
MF-LF402
2.25%
1/16W
R33041 2
10K5%MF-LF4021/16W
R33011
2
CRITICAL
5X3.2-SM
14.31818Y3301
1 2
D051-7099
33 104
SYNC_DATE=10/12/2005CLOCKS
SYNC_MASTER=M42
CK410_XTAL_OUTCK410_XTAL_IN
CK410_SRC1_P
MIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm
VOLTAGE=3.3VPP3V3_S0_CK410_VDDA
CK410_PCI4_CLK
CK410_SRC8_PCK410_SRC_CLKREQ8_L
CK410_DOT96_27M_NCK410_DOT96_27M_PCK410_PD_VTT_PWRGD_LCK410_USB48_FSA
CK410_CPU2_ITP_SRC10_P
CK410_CPU0_NPM_STPCPU_LPM_STPPCI_L
CK410_CPU1_P
MIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm
VOLTAGE=3.3VPP3V3_S0_CK410_VDD_PCI
PP3V3_S0_CK410_VDD_REFVOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm
VOLTAGE=3.3VMIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm
PP3V3_S0_CK410_VDD_CPU_SRC
CK410_PCI5_FCTSEL1
CK410_PCIF1_CLK
CK410_IREFSMB_CK410_DATA
CK410_SRC5_PCLK_NB_OE_L
CK410_SRC_CLKREQ6_L
CK410_CPU0_P
=PP3V3_S0_CK410
CK410_CLK14P3M_TIMERCK410_REF1_FCTSEL0
CK410_PCI2_CLK
CK410_SRC_CLKREQ1_LCK410_SRC2_N
CK410_SRC3_P
CK410_CPU1_N
CK410_LVDS_PCK410_LVDS_N
CK410_CPU2_ITP_SRC10_N
SMB_CK410_CLK
CK410_SRC_CLKREQ3_L
SB_CLK100M_SATA_OE_LCK410_SRC5_N
CK410_SRC4_PCK410_SRC4_N
=PP3V3_S0_CK410
CK410_SRC8_NCK410_SRC7_PCK410_SRC7_N
CK410_SRC6_NCK410_SRC6_P
CK410_PCI3_CLK
CK410_SRC3_N
CK410_SRC2_P
=PP3V3_S0_CK410
MIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm
PP3V3_S0_CK410_VDD48VOLTAGE=3.3V
CK410_SRC1_N
CK410_FSB_TEST_MODE
CK410_PCI1_CLK
CK410_PCIF0_CLK
63
63
63
34
34
34
34 34
34
34
34
34
26
34
34
34
23
23
34
34
27
34
14
34
34
33
34
34
34
34
34
34
34
34
34
34
23
34
34
34
33
34
34
34
34
34
34
34
33
34
34
34
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUTIN
IN
OUTIN
OUT
OUT
OUTOUT
OUT
IO
IO
OUT
IN
OUT
OUT
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
IN
IN
IN
OUT
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUTIN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE# NAPA PLATFORM ONLY SUPPORT 133M/166M CPU SPEED
Yukon CLK OE*
(Yukon PCI-E 100MHZ)
(GPU 27MHz Spread / Non-Spread)
(GPU PCI-E Graphics 100MHz)
(TO MCH FS_B)
(FROM CPU FS_B)
(FROM CPU FS_C)
0FS_B
166M
CPUFS_C00 0
00
0 00
0
11 1
11 11 11 1 1
100M333M
0
01#
#
400M
133M
200M
266MFS_A
(CPU HOST 133/167MHZ)
(GMCH HOST 133/167MHZ)
(GMCH G_CLKIN 100MHZ)
(ICH7M DMI 100MHZ)
NOSTUFF R3450,R3451,R3453 FOR MANUAL CPU FREQUENCY
(ICH7M 14.318MHZ)
(TO MCH FS_C)
RESERVED
(FROM CPU FS_A)
(ICH7M SATA 100MHZ)
(PORT80 LPC 33MHZ)
(TO ICH7M PCI 33MHZ)
(TO ICH7M USB 48MHZ)
NEED TO CHECK THE BSEL PULLS
(TO MCH FS_A)
(WIRELESS PCI-E MINI 100MHZ)
GPU CLK OE*
(ITP HOST 133/167MHZ)(TO SMC PCI 33MHZ)
(TO TPM PCI 33MHZ)
(TO FIREWIRE PCI 33MHZ)
(ExpressCard Slot)
49.9
MF-LF402
1%1/16W
ITPR34411 2
402
1/16W1%
MF-LF
71.5R34021 2
MF-LF
1%
402
1/16W
121R34181 2
1%
402MF-LF1/16W
121R34191 2
402MF-LF1/16W5%
33R34221 2
33
5%1/16WMF-LF402
R34231 2
33
MF-LF402
5%1/16W
R34651 2
MF-LF402
1/16W
33
5%
R34261 2 37 34
37 34
34 22
33
MF-LF
5%1/16W
402
R34281 2
5%1/16W
33
MF-LF402
R34271 2
1/16W5%
402
33
MF-LF
R34291 2
33
MF-LF402
5%1/16W
R34301 2
1/16W5%
402MF-LF
33R34331 2
MF-LF
5%
402
1/16W
33R34321 2
40
56
47
22
5%
MF-LF402
1/16W
33R34351 2
5%
402MF-LF1/16W
33R34341 2
49.9
MF-LF402
1%1/16W
R34081 2
49.9
MF-LF402
1%1/16W
R34361 2
49.9
MF-LF402
1%1/16W
R34371 2
49 5
1/16W5%
MF-LF
33
402
R34631 2
34 22
10K
MF-LF402
5%1/16W
R34671
2
10K
MF-LF402
5%1/16W
R34661
2
49.9
MF-LF402
1%1/16W
R34311 2
1/16W5%
402MF-LF
1KR34691
2
1/16W5%
402MF-LF
1KR34681 2
1/16W5%
402MF-LF
1KR34721 2
1/16W5%
402MF-LF
1KR34701
2
1/16W5%
402MF-LF
1KR34711 2
1/16W5%
402MF-LF
1KR34731
2
1/16W5%
402MF-LF
1KR34751 2
1/16W5%
402MF-LF
1KR34741 2
23
49.9
MF-LF402
1%1/16W
R34061 2
34 21 5
34 21 5
33
MF-LF402
5%1/16W
R34781 2
MF-LF402
5%1/16W
33R34771 2
1/16W1%
402MF-LF
49.9R34391 2
1/16W5%
402MF-LF
1K
NOSTUFFR34801
2
1/16W1%
402MF-LF
49.9R34811 2
1/16W1%
402MF-LF
49.9R34821 2
1/16W5%
402MF-LF
33R34761 2
1/16W5%
402MF-LF
0R34501 2
1/16W5%
402MF-LF
0R34531 2
1/16W5%
402MF-LF
1K
NOSTUFFR34541
2
49.9
MF-LF402
1%1/16W
R34071 2
1/16W5%
402MF-LF
0R34511 2
1/16W5%
402
1K
NOSTUFF
MF-LF
R34521
2
45 34 5
45 34 5
1/16WMF-LF
5%
402
33R34991 2
5%
402
1/16W
33
MF-LF
R34981 2
34 12
49.9
MF-LF402
1%1/16W
R34951 2
49.9
MF-LF402
1%1/16W
R34961 2
MF-LF402
1/16W
33
5%
R34931 2
5%
33
402
1/16WMF-LF
R34941 2
49.9
MF-LF
1%1/16W
402
R34901 2
34 12
49.9
MF-LF402
1%1/16W
R34911 2
34 7
5%
1K
1/16W
402MF-LF
R34861 2
5%
1K
MF-LF1/16W
402
R34851 2
34 7
79 34 11
79 34 11
402
33
MF-LF1/16W5%
R34111 2
49.9
MF-LF402
1%1/16W
ITPR34401 2
33
MF-LF402
5%1/16W
R34131 2
402MF-LF1/16W5%
33
ITPR34151 2
1/16W1%
402MF-LF
49.9R34381 2
49.9
MF-LF402
1%1/16W
R34041 2
49.9
MF-LF402
1%1/16W
R34421 2
33
402
5%1/16WMF-LF
R34121 2
1/16W5%
402MF-LF
33R34141 2
49.9
MF-LF402
1%1/16W
R34031 2
1/16W1%
402MF-LF
71.5R34051 2
1/16W1%
402MF-LF
49.9R34001 2
1/16W
402MF-LF
5%
33
ITPR34161 2
1/16W5%
402MF-LF
33R34171 2
1/16W5%
402MF-LF
2.2KR34011 2
Clock TerminationSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
34 104
D051-7099
CK410_DOT96_27M_P
CK410_DOT96_27M_NCK410_27M_SPREAD
MAKE_BASE=TRUE
CK410_27M_NONSPREADMAKE_BASE=TRUE
CK410_SRC3_P
MAKE_BASE=TRUETP_CK410_SRC7N
PCI_CLK_PORT80_LPC
CK410_SRC6_P
CK410_CPU2_ITP_SRC10_N
CK410_SRC_CLKREQ3_L
CK410_SRC2_P
SB_CLK100M_DMI_N
PCIE_CLK100M_MINI_P
CK410_SRC5_P
CK410_SRC6_N
NB_CLK100M_GCLKIN_P
ENET_CLK100M_PCIE_P
PEG_CLK100M_GPU_P
CK410_SRC7_P
=PP3V3_S0_CK410
=PP1V05_S0_FSB_NB
CK410_PCI5_FCTSEL1
SB_CLK14P3M_TIMER
CK410_REF1_FCTSEL0
CPU_BSEL_R<2>MAKE_BASE=TRUETP_CK410_LVDSN
CK410_SRC1_P
PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_PPCIE_CLK100M_EXCARD_P
CK410_SRC4_P
CK410_SRC8_P
CK410_SRC8_N
SB_CLK100M_DMI_P
SB_CLK100M_SATA_N
CPU_BSEL<2>
ENET_CLK100M_PCIE_N
CK410_SRC3_N
CPU_BSEL<1>
NB_BSEL<1>
CPU_BSEL_R<1>
CK410_CLK14P3M_TIMER
CPU_BSEL<0>CPU_BSEL_R<0>
NB_BSEL<2>
CK410_USB48_FSA
CK410_FSB_TEST_MODE
NB_BSEL<0>
=PP1V05_S0_FSB_NB
=PP1V05_S0_FSB_NB
FSB_CLK_CPU_PCK410_CPU0_P
FSB_CLK_CPU_NCK410_CPU0_N
CK410_CPU1_P FSB_CLK_NB_P
FSB_CLK_NB_N
CK410_CPU2_ITP_SRC10_P
CPU_XDP_CLK_N
PCIE_CLK100M_MINI_N
NB_CLK100M_GCLKIN_N
SB_CLK100M_DMI_N
SB_CLK100M_DMI_P
CPU_XDP_CLK_N
CPU_XDP_CLK_P
FSB_CLK_NB_P
FSB_CLK_NB_N
FSB_CLK_CPU_P
FSB_CLK_CPU_N
ENET_CLK100M_PCIE_P
ENET_CLK100M_PCIE_N
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
NB_CLK100M_GCLKIN_P
NB_CLK100M_GCLKIN_N
SB_CLK100M_SATA_P
SB_CLK100M_SATA_N
PCIE_CLK100M_EXCARD_N
PEG_CLK100M_GPU_NCK410_SRC1_N
MAKE_BASE=TRUETP_CK410_LVDSPCK410_LVDS_P
MAKE_BASE=TRUETP_CK410_SRC7P
MAKE_BASE=TRUETP_CK410_PCI4_CLKCK410_PCI4_CLK
PCI_CLK_SB
CK410_PCIF0_CLK
CK410_PCI1_CLK PCI_CLK_FW
CK410_PCI2_CLK PCI_CLK_TPM
CK410_PCI3_CLK
SB_CLK48M_USBCTLR
PEG_CLK100M_GPU_N
PEG_CLK100M_GPU_P
CK410_LVDS_N
CK410_SRC_CLKREQ8_L
CK410_SRC_CLKREQ1_L
CK410_SRC7_N
MINI_CLKREQ_LMAKE_BASE=TRUE
EXCARD_CLKREQ_LMAKE_BASE=TRUE
CK410_SRC_CLKREQ6_L
CK410_SRC5_N
PCI_CLK_SMC
CK410_PCIF1_CLK
CK410_SRC4_N
CK410_SRC2_N
CK410_CPU1_N
CPU_XDP_CLK_P
SB_CLK100M_SATA_P
GPU_CLK27MSS_IN
GPU_CLK27MGPU_CLK27M
GPU_CLK27MSS_IN
63
63
63
45
34
45
45
34
34
45
79
79
45
45
34
34
34
34
65
33
63
19
34
34
19
19
34
34
34
34
34
34
34
34
34
34
37
37
34
34
34
34
21
21
65
33
33
65
65
33
33
45
45
69
69 69
69
33
33
33
33
33
33
33
5
33
33
14
34
33
12
33
33
33
5
5
33
33
33
7
33
7
14
33
7
14
33
33
14
12
12
33
33
33
33
5
14
22
22
11
11
12
12
7
7
34
34
5
5
14
14
5
5
34 33
33
33
33
33
23
34
34
33
33
5
5
33
33
33
33
33
33
34
34 34
34
NC7
NC6
NC5
NC4
NC2
NC3
OUT
VDD
NC0
NC1
VIO
GND
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NC
NC
NCNC
NC
NC
NCNC
SMC G3Hot Oscillator
TPM Crystal Circuit
NCNC
SM-2
CRITICAL
32.768KY3720
24
13
5%
402
0
1/16WMF-LF
R37211 2
1/16W5%
402MF-LF
NO STUFF
10MR37201
2
SG-3040LC-SM
CRITICAL
32.768KHZ-9-3.6VU3750
6
2
3
4
5
8
9
10
11
7
12
1
10VCERM402
20%0.1uF
C3751 1
2
SM
FERR-EMI-100-OHML3750
1 2
4.7uF20%
CERM603
6.3V
C37501
2
5%1/16WMF-LF
22
402
R37501 2
15pF
50VCERM402
5%
C37201 2
15pF
CERM402
5%50V
C37211 2
Mobile ClockingSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
051-7099 D
10437
TPM_XTALI
TPM_XTALO_R
SMC_CLK32K_SUSCLK_R
=PP3V42_G3H_SMC_CLK
TPM_XTALO
VOLTAGE=3.425V
PP3V42_G3H_SMC_CLK_FMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm
SMC_CLK32K_SUSCLKMAKE_BASE=TRUE
SMC_SUS_CLK
56
63
56
47
IN
IO
IO
IO
IO
IO
IN
IO
IO
IO
IN
IN
IN
IN
OUT
G
DS
IN
IO
IO
IO
IO
IO
IO
IO
IO
IN
OUT
OUT
INOUT
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
ODD to keep SB GPIO <= 3.3VCounters 10K pull-up to 5V in
(UATA_CS0*)
(UATA_HSTROBE)(UATA_DSTROBE)
NC
(UATA_CS1*)
from ball of SBPlace within 12.7mmPlacement note
(UATA_STOP)
IDE (ODD) Connector
516S0335
Indicates disk presence
1/16W
100
402MF-LF
5%
R38501
2
M-ST-SM1-LF
CRITICALJ3800
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25 26
27
28
29
3
30
31
32
33
34
35
36
37
38
39
4
40
41
42
43
44
45
46
47
48
49
5
50
6
7
8
9
1%24.91/16WMF-LF402
R38601
2
1/16W
402MF-LF
NO STUFF
4.7K5%
R38011
2
402
4.7K
MF-LF
5%1/16W
R38021
2
6.2K
MF-LF402
5%1/16W
R38031
2
33K
MF-LF402
5%1/16W
R38101
2
BGA
CRITICAL
FDZ293PQ3820
C1
C2
C3
A1
A2
A3
B1
B2
B3
1/16W5%
402MF-LF
10KR38201
2 0.22uF
402X5R6.3V20%
C38211 2
10K
MF-LF402
5%1/16W
R38211
2
1/16WMF-LF
402
5%15K
R38111
2
SYNC_MASTER=(MASTER)
10438
D051-7099
PATA ConnectorSYNC_DATE=(MASTER)
=PP3V3_S0_IDE
IDE_PDIOW_L
SMC_ODD_DETECT
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.4 mmVOLTAGE=5V
PP5V_S0_IDE_ODD
IDE_PDDREQIDE_PDIOR_LIDE_PDIORDY
IDE_PDD<3>
IDE_IRQ14
ODD_PWR_EN_L_RC
IDE_PDD<0>
=PP5V_S0_IDE
IDE_PDD<13>
ODD_PWR_EN_L
SATA_RBIASMAKE_BASE=TRUE
TP_SATA_A_R2DNMAKE_BASE=TRUE
TP_SATA_A_D2RNMAKE_BASE=TRUE
SATA_A_D2R_N
TP_SATA_A_D2RPMAKE_BASE=TRUE
SATA_A_D2R_P
TP_SATA_A_R2DPMAKE_BASE=TRUE
SATA_A_R2D_C_P
SATA_C_DET_L
SATA_A_R2D_C_N
IDE_PDD<4>
IDE_PDCS3_L
IDE_PDA<1>
IDE_PDDACK_L
IDE_PDD<15>IDE_PDD<14>
IDE_PDD<11>IDE_PDD<10>IDE_PDD<9>IDE_PDD<8>
IDE_PDD<1>IDE_PDD<2>
IDE_PDD<5>IDE_PDD<6>IDE_PDD<7>
IDE_PDA<0>IDE_PDCS1_LIDE_PDA<2>
SATA_RBIAS_PSATA_RBIAS_N
IDE_PDD<12>
IDE_RESET_L
63
21
47
21
21
21
21
21
21
63
21
22
21
21
21
23
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
23
OUT
OUT
AVDDL0
AVDDL4
AVDD
THRML_PAD
VDDO_TTL0
AVDDL6
VDDO_TTL1
RX_N
TESTMODE
TSTPT
LINK*
LED_LINK10/100*
LED_LINK1000*
LED_ACT*
RSET
CTRL25
CTRL12
HSDACN
HSDACP
SWITCH_VAUX
SWITCH_VCC
VMAIN_AVLBL
VAUX_AVLBL
LOM_DISABLE*
XTALO
XTALI
SPI_DO
SPI_CLK
SPI_CS
SPI_DI
VPD_CLK
VPD_DATA
MDIP3
MDIN3
MDIN2
MDIP2
MDIN1
MDIP1
MDIN0
MDIP0
WAKE*
REFCLKN
TX_N
VDDO_TTL3
VDDO_TTL2
VDDO_TTL4
VDD0
VDD1
VDD3
VDD2
VDD6
VDD5
VDD4
VDD7
AVDDL1
AVDDL2
AVDDL5
VDD25
PERST*
REFCLKP
RX_P
AVDDL3
TX_P
PU_VDDO_TTL0
PU_VDDO_TTL1TEST
TESTTWSI
SPI
MAIN CLK
PCI EXPRESSANALOG
MEDIALED
E2
WC*
NC0NC1
VCC
VSS
SCL
SDA
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IN
OUT
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TRACE LENGTH <12MIL
PLACE C4135-C4139 NEAR VDDO_TTL0-VDD_TTL4 ON U4101
NO PULL-UP NEEDED
PLACE C4113 AND C4112 WITHIN
PLACE C4100-C4106 NEAR PINS AVDLL0-AVDLL6.SCHEME MATCHES DOC MVL100258-01
PLACE C4110 AND C4111 WITHIN12 MIL OF U4101 PIN 49 AND 50
PLACE C4107 NEAR U4101 AVDD
PLACE C4140 NEAR U4102 VCC
SCHEME MATCHES DOC MVL100258-01PLACE C4127-C4134 NEAR PINS VDD0-VDD7 ON U4101
SCHEME MATCHES DOC MVL100258-01
NC
NC
2. DO NOT ROUTE UNDER CRYSTAL
NC
NC
NC
NC
NC
NC
NC
1. KEEP ENET_XTALI AND ENET_XTALO
ASF IS UNAVAILABLE ON 8053
PLACE RESISTORS CLOSE TO U4101
OPTIONAL EXTERNAL LDO NC
NC
INTERNAL PULL-UP
NC
12 MIL OF U2100 E27 AND E28
27pF50VCERM
5%
402
C41511
2
5%
4.7K
1/16W
MF-LF
402
R4122
12
4.7K
MF-LF
5%
402
1/16W
R4123
12
402
16VX5R
10%0.1UFC41011
2
CRITICALOMIT
QFN88E8053U4101
23
19
22
28
32
51
52
57
3
4
25
24
59
60
62
63
10
18
21
27
31
17
20
26
30
5
42
43
56
55
16
53
54
37
36
35
34
9
11
46
65
29
50
49
12
27
13
64
33
39
44
48
58 18
40
45
61
47
38
41
6
15
14
16V10%0.1UF
402X5R
C41401
2
SO8
CRITICAL
M24C08
OMIT
U41023
1
2
6
5
8
4
7
1/16W
1%
4.87K
MF-LF
402
R4102
12
0.1UF
X5R402
10%16V
C41071
2
402
10%16VX5R0.1UF
C4110
1 2
16V10%
0.1UF402
X5RC4111
1 2
10%0.1UF402
16V
X5RC4112
1 2
402X5R16V10%
0.1UFC4113
1 2
402MF-LF
1%49.91/16W
R41061
2 402
1%1/16WMF-LF
49.9R41171
2402MF-LF1/16W
49.91%
R41181
2
1%49.91/16WMF-LF402
R41191
2402
1/16W1%
MF-LF
49.9R41201
2MF-LF
49.9
402
1%1/16W
R41031
2402MF-LF1/16W1%49.9R41041
2402MF-LF1/16W1%49.9R41051
2
50V10%
402CERM
0.001UFC41161
2402
10%0.001UF50VCERM
C41181
2
0.001UF
CERM
10%
402
50V
C41171
2402
50V10%
CERM
0.001UFC41151
2
402CERM6.3V10%1UFC41001
2
FERR-120-OHM-1.5A
0402
L4100
1 2
4.7K5%1/16WMF-LF402
R41311
2402MF-LF1/16W5%4.7KR41301
2
4.7K
1/16W
402
5%
MF-LF
R4101
12
0.001UF
CERM
10%50V
402
C41051
2X5R
10%0.1UF
402
16V
C41041
2402
0.1UF
X5R
10%16V
C41031
210%0.1UF
X5R402
16V
C41021
2
0.001UF
402CERM50V10%
C41061
2
402
16V
0.1UF
X5R
10%
C41281
2
0.001UF10%
402
50VCERM
C41331
2 50V
402CERM
0.001UF10%
C41341
2402CERM
0.001UF10%50V
C41311
210%0.001UF
CERM402
50V
C41321
216V10%
X5R402
0.1UFC41271
210%
X5R402
16V
0.1UFC41261
2 16V
402X5R
0.1UF10%
C41291
2 16V10%
402X5R
0.1UFC41301
2 402CERM
10%50V
0.001UFC41391
20.001UF50VCERM402
10%
C41381
216V
0.1UF
X5R402
10%
C41371
2402
10%
X5R
0.1UF16V
C41361
2402X5R
0.1UF10%16V
C41351
2
25.0000MSM-3.2X2.5MM
CRITICAL
Y410124
13
27pF
402CERM50V5%
C41501
2
D051-7099
104
SYNC_MASTER=M42 SYNC_DATE=10/12/2005
ETHERNET CONTROLLER
41
ENET_XTALOENET_XTALI
=PP1V2_S3_ENET
ENET_MDI_P<2>ENET_MDI_N<2>ENET_MDI_P<3>ENET_MDI_N<3>
ENET_MDI_P<1>
PCIE_A_R2D_N
=PP3V3_S3_ENET
ENET_MDI_P<0>
MIN_NECK_WIDTH=0.22MMMIN_LINE_WIDTH=0.4MM
VOLTAGE=2.5VPP2V5_S3_ENET_AVDD
ENET_VPD_DATA
ENET_PU_VDD_TTL0
=ENET_VMAIN_AVLBL
ENET_MDI_N<0>
ENET_VPD_CLK
ENET_VPD_DATA
=PP3V3_S3_ENET
ENET_RST_L
ENET_CLK100M_PCIE_NENET_CLK100M_PCIE_P
ENET_PU_VDD_TTL1
PCIE_A_D2R_C_P
=PP2V5_S3_ENET
PCIE_WAKE_L
ENET_PU_VDD_TTL1
=PP3V3_S3_ENET
ENET_RSET
ENET_LOM_DIS_L
PCIE_A_R2D_P
ENET_PU_VDD_TTL0
ENET_MDI1
PCIE_A_R2D_C_N
ENET_MDI0
PCIE_A_R2D_C_P
ENET_MDI3
=PP3V3_S3_ENET
PCIE_A_D2R_C_N PCIE_A_D2R_NPCIE_A_D2R_P
=PP3V3_S3_ENET
ENET_VPD_CLK
ENET_CTRL25ENET_CTRL12
=PP1V2_S3_ENET
ENET_MDI_N<1>
ENET_MDI2
45
63 63
63
23
63
63
63 63
37
38
38
38
38
38
37
38
38
37
37
62
38
37
37
37
26
34
34
37
63
5
37
37
6
37
22
22
37
22
22
37
37
6
6
37
38
SYM_VER2
NC2 NC3NC4
LINE
SIDE
CHIP
SIDENC1
SYM_VER2
NC2 NC3NC4
LINE
SIDE
CHIP
SIDENC1
IN
IO
IO
IO
IO
IO
IO
IO
IO
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
BOM options provided by this page:
Place close to connector
514-0277Short shielded RJ-45
PHYSICAL
PROVIDED
ELECTRICAL_CONSTRAINT_SET
Place one cap at each pin of transformer
NET_TYPE
SPACING
Page NotesPower aliases required by this page:
(NONE)Signal aliases required by this page:
(NONE)
- =PP2V5_ENET
BY
ETHERNET
PHY
Transformers should be
sides of the board
- =GND_CHASSIS_ENET
mirrored on opposite
1/16W
NO STUFF
5%
MF-LF
0
402
R42101 2
1uF6.3V10%
CERM402
C42031
2
1uF6.3V10%
CERM402
C42021
2
100pF
CERM1808
10%3KV
C420421
1/16W5%
402MF-LF
75R42031
2
1/16W5%
402MF-LF
75R42021
2
1/16W5%
402MF-LF
75R42011
2
1/16W5%
402MF-LF
75R42001
2
6.3V
402
1uF10%
CERM
C42011
2
1uF
CERM6.3V10%
402
C42001
2
XFR-SM
CRITICAL1000BT-824-00275
T42001
10
11
14
15
16
2
3
6
7
8 9
4
5 12
13
XFR-SM
1000BT-824-00275CRITICALT4201
1
10
11
14
15
16
2
3
6
7
8 9
4
5 12
13
CRITICAL
JM36113-P2054-7FF-RT-TH-RJ45
J4200
9
10
11
12
1
2
3
4
5
6
7
8
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
Ethernet Connector
104
051-7099
42
D
ENETCONN_P<3>
ENET_100DENETCONN ENETCONN_P<2>
ENET_MDI_P<0>
ENET_MDI_P<3>
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
ENET_CTAP_COMMON
ENET_MDI_N<3>
ENET_MDI_N<2>
ENET_MDI_P<2>
ENET_MDI_P<1>
ENET_MDI_N<0>
ENET_100DENETCONN ENETCONN_N<2>ENET_100DENETCONN ENETCONN_P<3>
ENET_100DENETCONN ENETCONN_P<0>ENET_100DENETCONN ENETCONN_N<0>
ENET_100DENETCONN ENETCONN_N<1>
ENET_100DENETCONN ENETCONN_N<3>
ENET_100DENETCONN ENETCONN_P<1>
ENET_CTAP1
ENET_CTAP3
ENET_CTAP2
ENETCONN_N<3>
ENETCONN_N<1>
ENETCONN_N<2>
ENETCONN_P<2>
ENETCONN_N<0>
=GND_CHASSIS_ENET
ENET_MDI_N<1>
PP2V5_S3_ENET_AVDD
ENETCONN_P<0>
ENETCONN_P<1>
ENET_CTAP0
38
38
37
37
37
37
37
37
37
38
38
38
38
38
38
38
38
38
38
38
38
6
37
37
38
38
G
D
S
N-CHN
S
D
G
P-CHN
G
DS
G
D
S
G
D
S
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
S0 AC 0V 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)
Allows powering Yukon down during battery sleep to save power
1.2V enable has pull-up to 3.3V
When ENETPWR_S3 BOMOPTION is active:
When ENETPWR_S3AC BOMOPTION is active:
State PM_SLP_S4_L PM_SLP_S3BATT PM_SLP_S3BATT_L P2V5S3_EN_L P1V2S3_RUNSS
State FWPWR_EN_L PM_SLP_S4_L PM_SLP_S3BATT PM_SLP_S3BATT_L P2V5S3_EN_L P1V2S3_RUNSS
S0 Batt 0V 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)
S3 AC 0V 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)
S3 Batt PBUS 3.3V PBUS (3.3V OFF) 0V 3.3V (2.5V OFF) 0V (1.2V OFF)
S5 AC 0V 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)
S5 Batt PBUS 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)
G3H Batt PBUS 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)
S0 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)
S3 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)
S5 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)
G3H 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)
Yukon Power Control
5%1/16WMF-LF402
470KR43021
2
2N7002DW-X-FSOT-363
Q43043
5
4
MF-LF
100K1/16W5%
402
R43041
2
0
ENETPWR_S3AC
402MF-LF1/16W5%
R43001 2
0
402MF-LF1/16W5%
ENETPWR_S3
R43011
2
SC70-6FDG6332C_NLQ4300
6
2
1
FDG6332C_NLSC70-6
Q4300
3
5
4
2N7002SOT23-LF
Q43023
1
2
SOT-3632N7002DW-X-FQ4304
6
2
1
402
5%1/16WMF-LF
100KR43051
2
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
Yukon Power Control
051-7099 D
10443
P1V2S3_RUNSS
PM_SLP_S3BATT
FWPWR_EN_L_OR_GND
PM_SLP_S4_L
=PP3V3_S3AC_FET=PP3V3_S3_P3V3S3AC
PPVIN_S3_P2V5S3_SVIN
PM_SLP_S3BATT_L =P2V5S3_EN_LMAKE_BASE=TRUEP2V5S3_EN_L
=PPBUS_G3H_S3AC
FWPWR_EN_L
62
59
47
5
23
63 63
59
59
63
41
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
IN
IN
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
MPCI_ACTN_323
TPB0_P
TPBIAS0
PCI_AD12
RESET*
TPBIAS2
PCI_RST*
PCI_INTA*
PCI_PME*
PCI_AD21
PCI_AD31
XO
XI
R1
R0
TPA0_N
TPA0_P
TPB0_N
TPBIAS1
TPA1_P
TPB1_P
TPA1_N
TPA2_P
TPA2_N
TPB2_P
TPB2_N
MODE_A
MODE_420
TEST0
TEST1
PTEST
SE
SM
VSS21
VSS22
VSS20
VSS18
VSS19
VSS16
VSS15
VSS17
VSS13
VSS14
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0
VSSA0
VSSA1
VSSA3
VSSA4
VSSA2
VDDA4
VDDA5
VDDA3
VDDA2
VDDA1
VDDA0
VDD0
VDD2
VDD1
VDD3
VDD4
VDD7
VDD9
PCI_VIOS
PCI_AD0
PCI_AD2
PCI_AD4
PCI_AD5
PCI_AD3
PCI_AD6
PCI_AD9
PCI_AD10
PCI_AD8
PCI_AD11
PCI_AD14
PCI_AD15
PCI_AD13
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD23
PCI_AD22
PCI_AD25
PCI_AD28
PCI_AD26
PCI_AD29
PCI_AD30
PCI_CBE2*
PCI_CBE1*
PCI_CBE0*
PCI_CBE3*
PCI_PAR
PCI_FRAME*
PCI_IRDY*
PCI_TRDY*
PCI_DEVSEL*
PCI_STOP*
PCI_IDSEL
PCI_REQ*
PCI_GNT*
PCI_PERR*
PCI_SERR*
PCI_CLK
CLKRUN*
VDD5
PCI_AD27
PCI_AD24
VDD6
PCI_AD1
TPB1_N
PC0
PC2
CONTENDER
CARDBUSN
PCI_AD7
PC1
IO
IO
IO
IO
IO
IO
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NEED TO CHECK CRYSTAL LOAD CAPACITANCE
6/22/2005 - ADDED 510K PULL-DOWN ON RST* AND REMOVED CONNECTION TO PLT_RST_L
6/20/2005 - BGA VERSION OF FW323-06 ADDED
PAGE HISTORY
6/22/2005 - BRING OUT PC0 CONNECTION TO BE CONNECTED ON PORT PAGE
FW_B_TPA_P/N, FW_B_TPB_P/N, FW_B_TPBIAS - PORT 1 FIREWIRE DIFF PAIRS
INPUT
PAGE NOTES
6/22/2005 - CHANGED CLK,PME,DIFF PAIR NAMES TO BE RE-USE COMPLIANT
OUTPUT
6/22/2005 - REMOVED C4421 - REDUNDANT
FW_C_TPA_P/N, FW_C_TPB_P/N, FW_C_TPBIAS - PORT 2 FIREWIRE DIFF PAIRS
INPUT/OUTPUT
PCI_CLK_FW - NEED TO REFERENCE TO ALIAS PAGE
PM_CLKRUN_L - CLOCK-RUN PCI PROTOCOLPCI_REQ3_L - PCI REQUEST TO SB
PCI_RST_L - PCI RESET FROM SBFW_PC0 - FIREWIRE POWER CLASS IDENTIFIER
PCI_PME_FW_L - DEDICATED PME FOR FIREWIRE (SB GPIO1)INT_PIRQD_L - INTERRUPT TO SB
6/22/2005 - REMOVED CONSTRAINT SETS AS THEY WILL BE MANAGED ON BOARD SIDE
6/21/2005 - CHANGED REQ/GNT TO REQ3/GNT3 (PER ARCHITECTURAL DEFINITION)6/21/2005 - CHANGED PCI_ID TO AD19 (PER ARCHITECTURAL DEFINITION)
PCI_AD<0..31>,PCI_C_BE_L<0..3>,PCI_FRAME_L,PCI_IRDY_L,PCI_TRDY_L,PCI_DEVSEL_L, PCI_STOP_L, PCI_PAR, PCI_PERR_L, PCI_SERR_LFW_A_TPA_P/N, FW_A_TPB_P/N, FW_A_TPBIAS - PORT 0 FIREWIRE DIFF PAIRS
6/21/2005 - CHANGED INT* TO INT_PIRQD_L (PER ARCHITECTURAL DEFINITION)5/19/2005 - FIRST REVISION OF PAGE
7/26/2005 - CONNECTED PIN E10 TO GND
=PP3V3_S0_FW - 3.3V POWER FOR FIREWIRE (MOBILE: OFF DURING SLEEP)=PP3V3_S0_PCI - 3.3V POWER FOR PCI FIREWIRE (MOBILE: OFF DURING SLEEP)PCI_GNT3_L - PCI GRANT FROM SB
DUAL PORT DEVICES ARE POWER CLASS 4 (’100’)SINGLE PORT DEVICES ARE POWER CLASS 0 (’000’)
PLACE ONE CAP PER TWO PINS STARTING WITH C4424 ON VDD0
PLACE ONE CAP PER TWO PINS STARTING WITH C4416 ON VDDA0
0.001A DURING SLEEP
MODE FOR EXTERNAL LINK
LOW = PCI OPERATIONLOW = NOT BUS MANAGER
MANUFACTURING TEST PINS
CONNECT TO VDD FOR 3.3V OPERATION
THIS IS FROM ICH-7M
SPEC RECOMMENDS 2.49K
197S0178 3.2MMX2.5MM
6.3V20%
603X5R
10UFC44161
2
1/16W1%
402MF-LF
2.49KR44521
2
10V20%
402CERM
0.1UFC44281
210V20%
402CERM
0.1UFC44261
210V20%
402CERM
0.1UFC44221
210V20%
402CERM
0.1UFC44181
2
16V10%
402X5R
0.1UFC44291
2 16V10%
402X5R
0.1UFC44251
216V10%
402X5R
0.1UFC44171
2
16V10%
402X5R
0.1UFC44201
2
1/16W5%
402MF-LF
390R44001 2
6.3V20%
603X5R
10UFC44241
2
0402
600-OHM-300MAL4400
1 2
CRITICAL
OMITBGA
FW32306U4400
B1
D1
G12
M5
B6
E10
E12
F13
F12
F10
G10
L11
M12
M11
N12
M10
N11
M4
N5
N4
M3
H10
M2
N3
K4
M1
K2
J4
K1
J2
J1
H2
H12
H4
H1
J13
J12
K13
K10
L12
M13
K12
M9
L3
L1
G2
N8
N6
E1
L2
D2
M6
N10
M8
F2
E2
F1
N9
M7
N7
G13
A4
B7
A6
B4
A3
B3
C2
C1
B9
A9
B11
A11
C12
C11
A10
B10
A12
B12
D12
D13
B8
D8
C13
G4
N1
N2
K5
K6
K7
L13
H13
A2
D10
A13
B13
A7
A8
D6
A1
B2
G1
G6
G7
G8
H6
H7
H8
J5
J9
J10
C3
K8
K9
N13
D4
E4
E5
F4
F6
F7
F8
E13
E9
D9
D7
D5
A5
B5
1/16W5%
402MF-LF
510KR44201
2
1/16W5%
402MF-LF
100R44321 2
SMXW44001 2
1/16W5%
402MF-LF
22R44311
2
24.576MHZ
CRITICAL
SM-3.2X2.5MMY4403
2 4
1 3
CERM50V
402
5%22pF
C4411 1
25%
402CERM50V
22pFC44121
2
10V20%
402CERM
0.1UFC44301
2 10V20%
402CERM
0.1UFC44321
2
SYNC_MASTER=(M42) SYNC_DATE=08/29/2005
FIREWIRE CONTROLLER
051-7099 D
10444
FW_XO
FW_XI
FW_A_TPA_P
FW_A_TPB_P
PCI_IRDY_L
VOLTAGE=0V
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.5MM
GND_FW_VSSA
GND_FW_VSSA
PCI_RST_L FW_PCI_RST_LINT_PIRQD_L
PCI_CLK_FWPM_CLKRUN_L
PCI_PERR_LPCI_SERR_L
PCI_GNT3_LPCI_REQ3_L
PCI_STOP_LPCI_DEVSEL_LPCI_TRDY_L
PCI_FRAME_L
PCI_C_BE_L<3>
PCI_PAR
PCI_C_BE_L<1>PCI_C_BE_L<0>
PCI_AD<31>
PCI_AD<28>PCI_AD<29>PCI_AD<30>
PCI_AD<26>PCI_AD<27>
PCI_AD<25>
PCI_AD<23>PCI_AD<24>
PCI_AD<22>PCI_AD<21>PCI_AD<20>
PCI_AD<18>
PCI_AD<15>
PCI_AD<17>PCI_AD<16>
PCI_AD<13>PCI_AD<14>
PCI_AD<10>PCI_AD<11>PCI_AD<12>
PCI_AD<8>PCI_AD<9>
PCI_AD<6>PCI_AD<7>
PCI_AD<5>
PCI_AD<3>PCI_AD<4>
PCI_AD<2>PCI_AD<1>PCI_AD<0>
FW_PC0
FW_C_TPB_NFW_C_TPB_P
FW_C_TPA_PFW_C_TPA_N
FW_C_TPBIASFW_B_TPB_NFW_B_TPB_P
FW_B_TPA_PFW_B_TPA_N
FW_B_TPBIASFW_A_TPB_N
FW_A_TPBIAS
FW_A_TPA_N
FW_PCI_IDSEL
PCI_AD<19>
=PP3V3_S3_FW
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.5MMVOLTAGE=3.3VPP3V3_S3_FW_AVDD
FW_PWRON_RST_L
=PP3V3_S3_PCI
FW_R1
FW_R0
FW_XO_R
PCI_C_BE_L<2>
PCI_PME_FW_L
26
26
26
26
26
26
26
26
26
42
42
22
40
40
22
22
34
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
42
42
42
42
42
42
42
42
42
42
42
42
42
42
22
63
63
22
22
OUT
GND
OUT
VIN+ VIN-
V+
G
D
S
G
D
S
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
is running or on AC.Enables port power when machine
Port Power Switch
- =PPBUS_S0_FWPWRSW (system supply for bus power)
50V/V1A = 1V
- =PP3V3_S0_FWPORTPWRSW
BOM options provided by this page:(NONE)
Power aliases required by this page:
Signal aliases required by this page:- =FWPWR_PWRON (see related text note below)
Page Notes
FireWire Port Current Sense
402MF-LF
330K5%1/16W
R45661
2
16V20%
402
0.01uF
CERM
C4565 1
21/16W5%
402
470K
MF-LF
R45651
2
CRITICAL
SMB
B340XF
D45651 2
NDS9407
CRITICAL
SOI-LF
Q4565
5
6
7
8
4
1
2
3
1uF
CERM402
10%6.3V
C4595 1
2
SOT23-5INA194
CRITICAL
U4595
2
15
3 4
0.5%1W
0612MF
0.02R45701 2
2N7002DW-X-FSOT-363
Q45603
5
4
SOT-3632N7002DW-X-FQ4560
6
2
1
MINISMDC
1.1A-24V
CRITICALF4565
1 2
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
FireWire Port Power
D051-7099
45 104
FWPWR_IOUT=PP3V3_S0_FWISENS
=PPBUS_S5_FW_FET
VOLTAGE=12.6V
PPBUS_S5_FW_FET_D_RMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPPBUS_S5_FW_FET_D
PPBUS_S5_FWPWRSW_F
VOLTAGE=12.6VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
PM_SLP_S3_L
SMC_ADAPTER_EN
MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm
FWPWR_EN_L_DIV
=PPBUS_S5_FWPWRSW
FWPWR_EN_LMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm
48
62
47
47
45
51
63
63
23
5
63
39
TPO#
TPI
TPO
TPI#
VGND
VP
SYM_VER-2
SYM_VER-2
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
PORT 11394A
constrained on this page. It is
3rd TPA/TPB pair unused
Late-VG Protection Power
2nd TPA/TPB pair unused
assumed that FireWire PHY page will
Place close to FireWire PHY
FW Power Class Strap
(GND_FW_PORT1_VG)
Single-port system sets PC=0
Cable Power
Termination
provide the appropriate constraints
Page NotesPower aliases required by this page:
- =GND_CHASSIS_FW_PORT1- =PP3V3_S5_FWLATEVG
ELECTRICAL_CONSTRAINT_SET
PROVIDEDPHYSICAL
NET_TYPE
SPACING
PHYPAGE
BY
appropriate connectors and/or to
FireWire Design Guide (FWDG 0.6, 5/14/03)
(NONE)
(NONE)
BOM options provided by this page:
FireWire TPA/TPB pairs to their
Signal aliases required by this page:
1394b implementation based on Apple
(PPFW_PORT1_VP)
(TPA-)
(TPA+)
(TPB+)
the necessary aliases to map the
514-0255
NOTE: FireWire TPA/TPB pairs are NOT
- =PPFW_PORT1
(TPB-)
"Snapback" & "Late VG" Protection
to apply to entire TPA/TPB XNets.
properly terminate unused signals.
NOTE: This page is expected to contain
SM-1
400-OHM-EMIL4690
1 2330
5%1/16W
402MF-LF
R46901 2
FERR-250-OHM
SM
L4620
1 2
0.001uF
CERM
20%50V
402
C46241
2
SOT-363BAV99DW-X-FDP4620
4
5
3
0.001uF
CERM402
50V20%
C4621 1
2
603
50V20%
CERM
0.01uFC46251
2402
16V
0.01uF
CERM
20%
C4626 1
2
SOT-363BAV99DW-X-FDP4621
4
5
3
0.001uF
CERM
20%50V
402
C4623 1
2
BAV99DW-X-FSOT-363
DP4620
1
2
6
0.001uF
402
20%
CERM50V
C4620 1
2
BAV99DW-X-FSOT-363
DP4621
1
2
6
CERM402
20%50V
0.001uFC4622 1
2
6.3V10%
402
0.33uF
CERM-X5R
C46501
2
1/16W
56.2
MF-LF402
1%
R46511
2
56.2
MF-LF402
1%1/16W
R46501
2
56.2
MF-LF402
1%1/16W
R46531
2MF-LF402
1%1/16W
56.2R46521
2
MF-LF
1%1/16W
4.99K
402
R46541
2
220pF25V5%
402CERM
C46541
2
F-RT-TH-LF1394A
CRITICALJ4620
7 8 9 10
4
3
6
5
2
1
260-OHM-330MASM1
CRITICALFL4620
4
1 2
3
260-OHM-330MASM1
CRITICALFL4621
4
1 2
3
0.001uF
CERM402
10%50V
C4692 1
2MMBZ5227BSOT23
CRITICAL
D4690
1
3
10V
0.1uF
CERM402
20%
C4691 1
2
1/16W5%
402MF-LF
0R46991 2
051-7099 D
46 104
FireWire PortsSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
VOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmPP3V3_S5_FWLATEVG_R_F
FW_TPA0_C
=GND_CHASSIS_FW_PORT1
FW_PORT1_TPB_P
FW_PORT1_TPB_N FW_PORT1_TPB_FL_N
FW_PORT1_TPB_FL_P
FW_PORT1_TPA_P
FW_PORT1_TPA_N
FW_PORT1_TPA_FL_N
FW_PORT1_TPA_FL_P
=PPFW_PORT1PPFW_PORT1_VP
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=33V
FW_A_TPB_P
FW_A_TPB_N
FW_C_TPBIASMAKE_BASE=TRUENO_TEST=YES
NC_FW_C_TPBIAS
NC_FW_C_TPANNO_TEST=YESMAKE_BASE=TRUE
NC_FW_B_TPAPMAKE_BASE=TRUENO_TEST=YES
FW_B_TPB_P NC_FW_C_TPBPNO_TEST=YESMAKE_BASE=TRUE
NC_FW_C_TPBNNO_TEST=YESMAKE_BASE=TRUE
NC_FW_B_TPBNNO_TEST=YESMAKE_BASE=TRUE
NO_TEST=YESMAKE_BASE=TRUENC_FW_B_TPBP
NC_FW_B_TPANNO_TEST=YESMAKE_BASE=TRUE
MAKE_BASE=TRUEFW_PORT1_TPB_P
=GND_CHASSIS_FW_EMI
FW_C_TPA_NFW_B_TPA_N
FW_B_TPBIAS
FW_B_TPA_P
MAKE_BASE=TRUEFW_PORT1_TPA_P
FW_PORT1_TPA_NMAKE_BASE=TRUE
FW_PORT1_TPB_FL_PFW_110DFW
FW_PORT1_TPA_FL_PFW FW_110D
FW_B_TPB_N
FW_C_TPA_P
FW_PORT1_TPB_FL_NFW FW_110D
FW_PORT1_TPB_NMAKE_BASE=TRUE
FW_A_TPA_N
FW_A_TPA_P
NO_TEST=YESMAKE_BASE=TRUENC_FW_C_TPAP
FW_C_TPB_P
FW_C_TPB_N
FW_PC0
=PP3V3_S5_FWLATEVG
VOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmPP3V3_S5_FWLATEVG_R
FW_A_TPBIAS
FW_PORT1_TPA_FL_NFW FW_110D
MAKE_BASE=TRUENC_FW_B_TPBIASNO_TEST=YES
PP3V3_S5_FWLATEVG_R_F
42
6
42
42 42
42
42
42
42
42
63
40
40
40
40
42
6
40 40
40
40
42
42
42
42
40
40
42
42
40
40
40
40
40
63
40
42
42
IO IO
IO
OUT
OUT
IO IO
IO
IN
OUT
SYM_VER-2
SYM_VER-2IO
IO
IO
IO
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Top-Case Connector
516S0350
Connector shield
(40 AWG)
(28 AWG)
Twin-Ax Pair 2
Standard wires
Connector shield
(40 AWG)
518S0371
Camera Connector
Twin-Ax Pair 1
M-ST-SMQT500166-L020
CRITICALJ4900
1
10
11 12
13 14
15 16
2
3 4
5 6
7 8
9
F-RT-SMCAMERA-M1-CUS
CRITICAL
J4931
7
8
1
2
3
4
5
6
SC-75
RCLAMP0502B
CRITICALD4900
3
1
2
0402
FERR-220-OHML4931
1 2
0402
FERR-220-OHML4930
1 2
SM165-OHM
CRITICALFL4936
1
2 3
4
SM165-OHM
CRITICALFL4935
1
2 3
4
SC-75
RCLAMP0502B
CRITICAL
NO STUFFD4930
3
12
50V20%
402CERM
0.001uF
NO STUFF
PLACEMENT_NOTE=Place next to J4931 pin 7
C4931 1
2
50V20%
402CERM
0.001uF
NO STUFF
PLACEMENT_NOTE=Place next to J4931 pin 8
C4930 1
2
051-7099 D
10449
Internal USB ConnectionsSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
SMBUS_ATS_SCL_F
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.25 mmVOLTAGE=0VGND_CAMERA
VOLTAGE=5V
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.25 mm
PP5V_S3_CAMERA_F
USB2_CAMERA_N_FUSB2_CAMERA_P_FSMBUS_ATS_SDA_F
=SMBUS_ATS_SDA
=PP5V_S3_CAMERA
=USB2_CAMERA_N
=USB2_CAMERA_P
=SMBUS_ATS_SCL
=USB_TRACKPAD_N
SMC_LID
KBDLED_ANODE
=I2C_TRACKPAD_SCL=SMBUS_TOPCASE_SCL=SMBUS_TOPCASE_SDA
=I2C_TRACKPAD_SDA
SMC_ONOFF_L
=USB_TRACKPAD_P
KBDLED_RETURN
=PP3V3_S3_TOPCASE=PP3V42_G3H_LIDSWITCH=PP5V_S3_TOPCASE
63
6
6
48
5
5
5
6
47
53
27
27
27
27
6
53
63
63
63
SYM_VER-2IO
IO
OUT
VBUS
D-
D+
GND
PADTHRML
GND
OUT_2
OUT_1
OUT_0
OC*EN*
IN_0
IN_1
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Right USB Port
Place L5200, L5205 and L5206 across moat
514S0115
Port Power Switch
CRITICAL
165-OHMSM
L5200
1
2 3
4
FERR-250-OHM
SM
L5205
1 2
6.3V20%
B2POLY
100UFC52961
2
10uF
CERM805-1
6.3V20%
C5295 1
2CERM
20%6.3V
10uF
805-1
C5290 1
2 10V20%
402CERM
0.1UFC52911
2
402
16VCERM
20%0.01uFC5205 1
2
0.01uF20%
402
16VCERM
C5206 1
2
SM
FERR-250-OHML5206
1 2
F-RT-SM-USB-RGT1UAR2X
CRITICALJ5200
1
2
3
4
5
6
7
8
CRITICAL
RTUSB_ESD
SC-75
RCLAMP0502BD5200
3
12
TPS2051
CRITICAL
MSOP
U5290
4
1
2
3
5
8
7
6
9
0
402MF-LF1/16W5%
R52921 2
402CERM-X5R6.3V20%
NO STUFF
0.47uFC52921
2
External USB ConnectorSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
051-7099 D
10452
=RTUSB_OC_LRTUSB_OC_L_RC
MIN_NECK_WIDTH=0.5 mmVOLTAGE=5V
PP5V_S3_RTUSB_ILIMMIN_LINE_WIDTH=0.5 mm
VOLTAGE=0VMIN_NECK_WIDTH=0.5 mmMIN_LINE_WIDTH=0.5 mmGND_RTUSB
=GND_CHASSIS_RTUSB
USB2_RT_F_NUSB2_RT_F_P
=USB2_RT_N
=USB2_RT_P
=RTUSB_EN
=PP5V_S3_RTUSBPP5V_S3_RTUSB_F
VOLTAGE=5VMIN_NECK_WIDTH=0.5 mmMIN_LINE_WIDTH=0.5 mm
6
6
6
6
62
63
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
516S0361
NCPlace XW5515 at 5V switcher
Left I/O Board Connector
(Input from LIO)
Place XW5500 at 5V switcher
Place XW5505 at 5V switcher
(2 Amps)
(500 mA)
Place XW5510 at 5V switcher
NCNC
(2 Amps)
(500 mA)
NC
CRITICAL
F-ST-SMQT510806-L111-7F
J5500
1
10
11 12
13 14
15 16
17 18
19
2
20
21 22
23 24
25 26
27 28
29
3
30
31 32
33 34
35 36
37 38
39
4
40
41 42
43 44
45 46
47 48
49
5
50
51 52
53 54
55 56
57 58
59
6
60
61 62
63 64
65 66
67 68
69
7
70
71 72
73 74
75 76
77 78
79
8
80
81
82 83
84
9
SMXW55001 2
SMXW55051 2
SMXW55101 2
SMXW55151 2
55 104
D051-7099
Left I/O Board ConnectorSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
=SMBUS_LIO_SB_SDA
=USB2_LT_P=USB2_LT_N
LIO_PLT_RESET_L
LIO_P3V3S3_EN
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm
VOLTAGE=5V
PP5V_S0_AUDIO
EXCARD_OC_L
SMC_BATT_TRICKLE_EN_L
LIO_DCIN_ISENSE
=PCIE_MINI_R2D_P=PCIE_MINI_R2D_N
=PCIE_MINI_D2R_N
PCIE_CLK100M_MINI_PPCIE_CLK100M_MINI_N
=SMBUS_LIO_SB_SCL
=USB2_EXCARD_N
=SMBUS_LIO_SMC_SCL=SMBUS_LIO_SMC_SDAPCIE_WAKE_L
ACZ_SYNCACZ_SDATAIN<0>
ACZ_SDATAOUT
SMC_BC_ACOK
SMC_SYS_ISET
LIO_BATT_ISENSE
MINI_CLKREQ_LEXCARD_CLKREQ_L
SMC_BATT_CHG_ENSMC_ADAPTER_ENSYS_ONEWIRE
=PP5V_S0_AUDIO_XW
SMC_BATT_ISET
LIO_P3V3S0_EN_L
SMC_EXCARD_CP
LTUSB_OC_L
=PPDCIN_G3H_LIO=PP3V42_G3H_LIO=PP1V5_S0_LIO
=USB2_EXCARD_P
=PCIE_MINI_D2R_P
ACZ_BITCLK
=PP5V_S5_LIO
PCIE_CLK100M_EXCARD_PPCIE_CLK100M_EXCARD_N
=PCIE_EXCARD_D2R_N
=PCIE_EXCARD_R2D_P
ACZ_RST_L
=PCIE_EXCARD_R2D_N
=PCIE_EXCARD_D2R_P
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mmGND_AUDIO
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.4 mmVOLTAGE=5V
PP5V_S0_AUDIO_PWR
GND_AUDIO_PWRMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.4 mmVOLTAGE=0V
SMC_EXCARD_PWR_EN
48
48
48
37
79
79
79
48
48
47
48
48
79
79
27
6
6
26
62
6
47
51
46
46
46
34
34
27
6
27
27
23
21
21
21
47
47
51
34
34
47
41
47
47
62
47
6
63
63
63
6
46
21
63
34
34
46
46
21
46
46
47
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
63
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
PCI-E x1 Port "F" = Unused
PCI-E x1 Port "E" = Unused
PCI-E x1 Port "D" = Unused
PCI-E x1 Port "C" = ExpressCard
PCI-E x1 Port "B" = PCI-E Mini Card
PCI-E x1 Port "A" = Ethernet (Yukon)
Place caps close to SB
Place caps close to SB
402X5R16V10%
0.1uFC5710
1 2
402X5R16V10%
0.1uFC5711
1 2
402X5R16V10%
0.1uFC5721
1 2402X5R16V10%
0.1uFC5720
1 2
57 104
D051-7099
PCI-E ConnectionsSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
PCIE_F_R2D_C_P
PCIE_B_R2D_C_P
PCIE_B_D2R_N
MAKE_BASE=TRUETP_PCIE_F_R2DN
=PCIE_MINI_D2R_P
=PCIE_MINI_D2R_N
=PCIE_MINI_R2D_N
=PCIE_MINI_R2D_P
PCIE_B_R2D_C_NPCIE_MINI_R2D_C_NMAKE_BASE=TRUE
MAKE_BASE=TRUEPCIE_MINI_D2R_N
PCIE_B_D2R_PMAKE_BASE=TRUEPCIE_MINI_D2R_P
MAKE_BASE=TRUEPCIE_MINI_R2D_C_P
=PCIE_EXCARD_R2D_P
=PCIE_EXCARD_R2D_N
=PCIE_EXCARD_D2R_P
=PCIE_EXCARD_D2R_N
MAKE_BASE=TRUEPCIE_EXCARD_R2D_C_P
MAKE_BASE=TRUEPCIE_EXCARD_R2D_C_N
MAKE_BASE=TRUEPCIE_EXCARD_D2R_P
MAKE_BASE=TRUEPCIE_EXCARD_D2R_N
PCIE_C_R2D_C_P
PCIE_C_R2D_C_N
PCIE_C_D2R_N
PCIE_C_D2R_P
TP_PCIE_D_D2RPMAKE_BASE=TRUETP_PCIE_D_D2RNMAKE_BASE=TRUE
MAKE_BASE=TRUETP_PCIE_D_R2DNMAKE_BASE=TRUETP_PCIE_D_R2DP
PCIE_D_D2R_P
PCIE_D_D2R_N
PCIE_D_R2D_C_N
PCIE_D_R2D_C_P
PCIE_E_R2D_C_P
PCIE_E_R2D_C_N
PCIE_E_D2R_N
PCIE_E_D2R_P
MAKE_BASE=TRUETP_PCIE_E_R2DP
MAKE_BASE=TRUETP_PCIE_E_R2DN
TP_PCIE_E_D2RNMAKE_BASE=TRUE
TP_PCIE_E_D2RPMAKE_BASE=TRUE
PCIE_F_R2D_C_N
PCIE_F_D2R_N
PCIE_F_D2R_P
MAKE_BASE=TRUETP_PCIE_F_R2DP
TP_PCIE_F_D2RNMAKE_BASE=TRUE
TP_PCIE_F_D2RPMAKE_BASE=TRUE
45
45
45
45
45
45
45
45
22
22
22
5
5
5
5
22
22
5
5
5
5
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
OUT
P16
P51
P50
P42/SDA1
P97/IRQ15*/SDA0
P95/IRQ14*
P94/IRQ13*
P93/IRQ12*
P92/IRQ0*
P91/IRQ1*
P86/IRQ5*/SCK1/SCL1
P83/LPCPD*
P82/CLKRUN*
P80/PME*
P35/LRESET*
P34/LFRAME*
P10
P12
P13
P14
P15
P17
P31/LAD1
P30/LAD0
P32/LAD2
P33/LAD3
P36/LCLK
P37/SERIRQ
P44/TMO1
P77/AN7
P76/AN6
P81/GA20
P96/EXCL
P11
P47/PWX1/PWM1
P45
P46/PWX0/PWM0
P40/TMIO
P43/TMI1/EXSCK1
P27
P26
P25
P24
P23
P22
P21
P20
P41/TMO0
P52/SCL0
P60/KIN0*
P61/KIN1*
P62/KIN2*
P63/KIN3*
P64/KIN4*
P65/KIN5*
P66/IRQ6*/KIN6*
P67/IRQ7*/KIN7*
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P84/IRQ3*/TXD1
P85/IRQ4*/RXD1
P90/IRQ2*
(1 OF 4)
PA2/KIN10*/PS2AC
PA3/KIN11*/PS2AD
PA5/KIN13*/PS2BD
PA4/KIN12*/PS2BC
PB2
PB3
PB4
PE0
PG6/EXIRQ14*/EXSDAB
PG5/EXIRQ13*/EXSCLA
PH1/EXIRQ7*
PH0/EXIRQ6*
PG7/EXIRQ15*/EXSCLB
PG4/EXIRQ12*/EXSDAA
PH3/EXEXCL
PH2/FWE
PB5
PF4/PWM4
PF2/IRQ10*/TMOY
PG2/EXIRQ10*/SDA2
PG0/EXIRQ8*/TMIX
PF7/PWM7
PC3/TIOCD0/TCLKB/WUE11*
PH5
PB7
PB6
PH4
PF5/PWM5
PF6/PWM6
PG1/EXIRQ9*/TMIY
PA6/KIN14*/PS2CC
PA7/KIN15*/PS2CD
PD0/AN8
PD1/AN9
PD2/AN10
PD3/AN11
PD4/AN12
PD5/AN13
PD6/AN14
PD7/AN15
PF0/IRQ8*/PWM2
PF1/IRQ9*/PWM3
PB0/LSMI*
PB1/LSCI
PC0/TIOCA0/WUE8*
PC1/TIOCB0/WUE9*
PC2/TIOCC0/TCLKA/WUE10*
PC4/TIOCA1/WUE12*
PC5/TIOCB1/TCLKC/WUE13*
PC6/TIOCA2/WUE14*
PC7/TIOCB2/TCLKD/WUE15*
PG3/EXIRQ11*/SCL2
PF3/IRQ11*/TMOX
PA1/KIN9*/PA2DD
PA0/KIN8*/PA2DC
PE1*/ETCK
PE2*/ETDI
PE3*/ETDO
PE4*/ETMS
(2 OF 4)
VCL
AVREF
VCC
VCC
VCC
AVCC
XTAL
EXTAL
AVCC
VCC
MD1
MD2
NMI
RES*
ETRST*
AVREF
AVSSVSS
(3 OF 4)
NC22
NC21
NC20
NC19
NC18
NC17
NC16
NC15
NC14
NC13
NC12
NC9
NC6
NC11
NC10
NC8
NC7
NC5
NC4
NC3
NC2
NC1
NC0
(4 OF 4)
OUT
OUT
IO
OUT
IN
IN
IN
OUT
IN
IO
IN
IO
OUT
OUT
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
IN
OUT
OUT
ININ
OUT
OUT
IO
IO
IO
IO
IN
IN
IN
OUT
OUT
OUT
IO
IN
IN
IN
IN
IO
IO
IN
IN
IO
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
THEY ARE SET BY SOFTWARE TO BEDRIVEN OUTPUTS ALWAYS SO THEY
LAYOUT NOTE:PLACE C5807 NEAR PIN F1
VCL IS INTERNAL RAILPLACE R5899 AND C5820 NEAR SMC PIN N14,N15
SMC
LAYOUT NOTE:
UNUSED PINS HAVE THE FORMAT
CAN BE LEFT NO-CONNECTED.
SMC_XXX WHERE XXX IS THE PORT NUMBER.
805
20%6.3VCERM
22UFC58021
2
402
0.47UF20%6.3VCERM-X5R
C58071
2
10V0.1UF20%CERM402
C58031
2
0.1UF20%CERM10V402
C58201
2
5%1/16W
4.7
402MF-LF
R58991 2
0.1UF20%10VCERM402
C58041
2
SMXW5800
1 2
40210V20%0.1UFCERM
C58051
220%10VCERM402
0.1UFC58061
2BGA
OMIT
SMC_H8S2116U5800B12
C13A15B14B15C14D12C15
D13D14D15E12E14E15E13F14
D9C9A9B9D8C8A8D7
A5B5D5C3B1C2D3C1
G1G4F2
L13L14L15K12K13K14J12J13
N12R13P13R14P14R15N13P15
C7A7B7D6C6A6B6
K4J2J1J3J4H2H1G2
OMIT
SMC_H8S2116BGA
U5800R3P3R2N3R1N2M4N1
B10A10D10A11B11C11A12D11
G14G15G13G12H14H15H13H12
M11P11R11N11P10R10N10M10
M3M2M1L4L2
M7P6R6N6M6R5P5N5
P9R9N9P8R8M8P7R7
E1F3K2C4D4B3
BGASMC_H8S2116
OMITU5800
N14
N15
M14
M15
P12R12
L1
B2
E2K1
F4
E3
P2
P1J15
A1
F1
D1P4R4
F12
F13
B13
A13A4B4D2
A2
BGASMC_H8S2116
OMIT
U5800
G3H3
K15J14
F15A14C12C10C5A3B8E4
K3
H4M9N8
L3N4M5N7
M12M13L12
MF-LF5%
4021/16W10KR58091
2MF-LF402
5%10K1/16W
R58011
2
1/16W5%10KMF-LF402
R58021
2
NOSTUFF
402MF-LF1/16W5%0R58031
2
10KMF-LF5%1/16W402
R58981
2
051-7099 D
58 104
SMC_SYS_VSET
SMC_BATT_ISET
SMC_LIDSMC_PF1
SMS_ONOFF_L
SMS_X_AXIS
SMS_Z_AXISSMC_ANALOG_IDSMC_NB_ISENSESMC_MEM_ISENSE
SMC_BS_ALRT_L
SMS_INT_L
SMC_CPU_ISENSE
SPI_SI
SMC_FAN_2_CTL
SMC_EXCARD_OC_L
SMC_PM_G2_EN
SMC_P22
SMC_XTALSMC_EXTAL
PP3V3_AVCC_SMCMIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.20 MM =PP3V3_S5_SMC
KBC_MDE
ALS_LEFT
SMC_MD1
PP3V3_AVREF_SMC
SMC_PROCHOT
SMC_TRST_L
SMC_NMI
GND_SMC_AVSS
SPI_ARB
SMC_XDP_TDO_3_3
SMC_SYS_LED_16B
GND_SMC_AVSS
=PP3V3_S5_SMC
SMC_CPU_INIT_3_3_L
SMC_P23
SMC_BC_ACOK
SMC_FWE
ALS_RIGHT
SMS_Y_AXIS
SMC_FAN_3_TACH
SMC_FAN_1_CTLSMC_FAN_0_CTL
SMC_P21
SMC_BATT_TRICKLE_EN_L
SMC_P20
SMC_BATT_CHG_ENSMC_P26
SMC_CASE_OPENSMC_TCKSMC_TDISMC_TDOSMC_TMS
SMC_SYS_ISETSMC_BATT_VSETSMC_ODD_DETECT
SMC_RUNTIME_SCI_L
SMB_0_S0_DATA
SMC_CPU_VSENSE
SMC_ADAPTER_EN
SMC_PF0
SPI_CE_LSMC_XDP_TCK_3_3
SMC_CPU_RESET_3_3_L
SMC_GPU_ISENSE
SMC_DCIN_ISENSE
SMC_EXCARD_CP
SMC_VCL
=PP3V3_S5_SMC
PM_SLP_S5_LPM_SLP_S4_LPM_SLP_S3_L SMC_RST_L
ALS_GAIN
SMC_THRMTRIP
SMC_XDP_TRST_L
PM_SYSRST_L
SMC_SUS_CLK
SPI_SCLK
SPI_SOSMC_PROCHOT_3_3_L
SMC_GPU_VSENSE
SMC_PBUS_VSENSESMC_BATT_ISENSESMC_FWIRE_ISENSE
SMC_EXCARD_PWR_EN
ISENSE_CAL_EN
SMC_EXTSMI_L
SMC_RX_L
SMC_XDP_TCK
SMC_XDP_TMS
SMB_BSB_DATASMC_TPM_PP
SMC_FAN_3_CTL
SMC_FAN_2_TACHSMC_FAN_1_TACHSMC_FAN_0_TACH
PM_BATLOW_LSYS_ONEWIREPM_THRM_LPM_EXTTS_LSMC_TPM_RESET_L
BOOT_LPC_SPI_LSMC_RCIN_L
SMC_P27
LPC_AD<0>LPC_AD<1>LPC_AD<2>LPC_AD<3>LPC_FRAME_LSMC_LRESET_LPCI_CLK_SMCINT_SERIRQ
SMC_TPM_GPIOPM_CLKRUN_LPM_SUS_STAT_LSC_TX_LSC_RX_L
SMC_ONOFF_L
SMB_BSB_CLK
SMC_WAKE_SCI_L
PM_PWRBTN_LIMVP_VR_ONPM_RSMRST_LSMC_SB_NMIRSMRST_PWRGDALL_SYS_PWRGD
PM_LAN_ENABLESMC_RSTGATE_L
SMB_0_S0_CLK
SMB_BSA_DATASMB_BSA_CLKSMB_A_S3_DATASMB_A_S3_CLKSMB_B_S0_DATASMB_B_S0_CLK
SMC_SYS_KBDLEDSMC_SYS_LED
SMC_TX_L
56
56
53
53
48
56
56
56
56
56
56
49
49
51
64
63
51
51
63
48
48
48
49
49
49
49
45
48
63
62
62 49
76
26
49
48
49
49
49
49
49
49
49
40
48
48
49
45
48
48
48
52
48
49
48
48
48
45
45
45
48
48
48
48
45
41
52
45
48
48
39
41 48
6
23
52
52
45
51
48
45
48
56
22
21
21
21
21
21
23
23
23
43
62
48
48
5
43
48
55
55
55
48
48
48
5
23
51
22
48
48
62
48
48
48
47
53
5
48
48
47
22
48
48
47
47
48
48
5
48
53
55
48
54
54
48
5
48
5
48
48
5
5
5
5
5
48 36
23
27
51
5
48
22
48
48
51
51
5
47
23
23
23 5
5
48
48
5
35
22
22
48
51
51
51
51
5
5
23
5
48
48
27
48
48
48
54
54
23
5
23
14
48
5
21
48
5
5
5
5
5
26
34
5
48
5
5
48
48
5
27
23
23
57
23
23
48
26
23
6
27
27
27
27
27
27
27
53
48
5
G
D
S
G
D
S
IN OUT
GND
IN OUT
V-
V+
V-
V+OUT
NCCD
GND
OUT
VDD
OUT
OUT
G
D
SIN
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
SMC 1.05V to 3.3V Level Shifting
1.05V Mid-Reference
Silk: "SMC RST"
SMC Reset Button / Brownout Detect
NC
System (Sleep) LED Circuit
NOTE: R5965 acts as 10K pull-up for PGOOD signal
1.71V Reference
Silk: "PWR BTN"
Debug Power ButtonSMC 3.3V to 1.05V Level Shifting
SMC AVREF Supply
ISL6269 undervoltage threshold 81-87% (2.67 - 2.87V)
5V Comp threshold set to 4.480V (89.6%)
SMC Crystal Circuit
SMC PWRGD CircuitReports when 5V S5 and 3.3V S5 are in regulation
10V20%
402CERM
0.1uFC5900 1
2
402MF-LF
5%
0
SMC_TPM_GPIO1
1/16W
R59901 2
402MF-LF1/16W5%
SMC_TPM_GPIO2
0R59911 2
SOT-3632N7002DW-X-FQ5995
6
2
1
SOT-3632N7002DW-X-FQ5995
3
5
4
5%
0
MF-LF1/16W
402
R59921 2
402
5%
0
MF-LF1/16W
R59931 2
10V20%
402CERM
0.1uFC5977 1
2
1/16W5%
402MF-LF
1KR59711
2
MF-LF1/16W
6.2K
402
5%
R59701
2
402CERM-X5R
20%6.3V
0.47uFC59651
2
402CERM16V20%0.01uFC59671
2
603
10uF
X5R
20%6.3V
C5966 1
2
CRITICAL
REF3133SOT23-3
VR5965
3
1 2
CERM402
20%10V
0.1uFC5960 1
2
1/16W1%
402MF-LF
10KR59611
2
10K1/16W
1%
402MF-LF
R59621
2
1/16W
10K
MF-LF402
5%
R59651
2
SM-LFLMC7211U5977
4
3
1
5
2
LMC7211SM-LF
U59604
3
1
5
2
402MF-LF
5%1/16W
0R59941 2
0
402
5%
SMC_TPM_PP
MF-LF1/16W
R59951 2
10K1/16W5% MF-LF 402
R5931 1 2
MF-LF5% 1/16W10K
402R5932 1 2
1/16W5% MF-LF 402100KR5933 1 2
402MF-LF5% 1/16W10KR5934 1 2
10K1/16W5% MF-LF 402
R5935 1 2
1/16W 402MF-LF5%100KR5936 1 2
1/16W5% MF-LF 4022.0K
ONEWIRE_PUR5937 1 2
100K1/16W5% MF-LF 402
R5938 1 2
10K1/16W5% MF-LF 402
R5939 1 2
MF-LF 4025% 1/16W10KR5940 1 2
MF-LF1/16W5% 40210KR5941 1 2
MF-LF 4025% 1/16W10KR5942 1 2
402MF-LF5% 1/16W10KR5943 1 2
402MF-LF5% 1/16W10KR5944 1 2
10K1/16W5% MF-LF 402
R5945 1 2
10K402MF-LF5% 1/16W
R5946 1 2
1/16W5% MF-LF 402470KR5947 1 2
402MF-LF5% 1/16W10KR5948 1 2
10K1/16W5% MF-LF 402
R5930 1 2
CRITICAL
5X3.2-SM20.00MHZY5920 1
2
CRITICAL
RN5VD30A-FSOT23-5
U5900
5
3
4
1
2
MF-LF402
1%1/16W
10KR59641
2
1/16W1%
402MF-LF
16.2KR59631
2
50V10%0.0022uF
402CERM
C59691
2
10K1/16W5% MF-LF 402
R5980 1 2
402MF-LF1/16W10K
5%R5981 1 2
402MF-LF5%10K
1/16WR5982 1 2
100K1/16W5% MF-LF 402
R5983 1 2
100K1/16W5% MF-LF 402
R5984 1 2
1K
MF-LF402
5%1/16W
R59001
2
1/10W5%
603MF-LF
0
OMITR59011
2
1/10W
0
OMIT
5%
603MF-LF
R59101
2
SOT23-LF2N7002Q5952
3
1
2
SOT23-LF2N3906Q59501
3
2
1/16W5%
402MF-LF
100R59501
2
1/16W5%
402MF-LF
2.2KR59511
2
1/16W5%
402MF-LF
4.7KR59521
2
50V5%
402CERM
15pFC59201 2
5%50VCERM402
15pFC59211 2
402
0.01UF16V10%
CERM
C5901 1
2
SMC Support
104
D051-7099
59
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
TPM_GPIO2
SMC_TPM_GPIO
SMS_INT_LSMC_TPM_RESET_L
SMC_LIDSMC_ONOFF_L
SMC_FWESMC_TX_LSMC_RX_L
=PP3V3_S5_SMC
=PP3V3_S3_SMS=PP3V3_S3_TPM
SYS_ONEWIRE
SMC_EXTAL
SMC_XTAL
SMC_TMSSMC_BS_ALRT_L
SMC_TDOSMC_TDI
SMC_XDP_TCK_3_3
SMC_TCKSMC_CPU_RESET_3_3_L
SMC_XDP_TDO_3_3
SMC_BATT_CHG_ENSMC_ADAPTER_ENSMC_CASE_OPENSMC_BC_ACOK
VOLTAGE=0V
MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mm
GND_SMC_AVSS
EXCARD_OC_L
PM_SLP_S5_LPM_SUS_STAT_LSMC_EXCARD_CP
SMC_BATT_TRICKLE_EN_L
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 mmPP3V3_AVREF_SMCMIN_NECK_WIDTH=0.2 mm
=PP3V42_G3H_SMCVREF
CPU_PROCHOT_L
PM_THRMTRIP_L
SMC_PROCHOT
SMC_THRMTRIP
SMC_ONOFF_L
PP5V_S5=PP3V42_G3H_SMC_PWRGD
RSMRST_PWRGDMAKE_BASE=TRUE
P5VS5_PGOOD
P1V71_SMC_REF
P5VS5_COMP_POS
=P3V3S5_PGOOD
SYS_LED_ILIM
=PP5V_S3_SYSLED
SYS_LED_L
SYS_LED_ANODE
SYS_LED_L_VDIV
SMC_SYS_LED_16B
=PP3V3_S5_SMC
SMC_MANUAL_RST_L SMC_RST_L
FWH_INIT_LMAKE_BASE=TRUE
SMC_CPU_INIT_3_3_L
MAKE_BASE=TRUESMC_P1V05S0_ISENSESMC_NB_ISENSE
DIMM_OVERTEMP_LPM_EXTTS_LMAKE_BASE=TRUE
MAKE_BASE=TRUESMC_P1V8S3_ISENSESMC_MEM_ISENSE
MAKE_BASE=TRUETP_SMC_ANALOG_IDSMC_ANALOG_ID
TP_SMC_SYS_LEDMAKE_BASE=TRUE
SMC_SYS_LED
TP_SMC_BATT_VSETMAKE_BASE=TRUE
SMC_BATT_VSET
TP_SMC_SYS_VSETMAKE_BASE=TRUE
SMC_SYS_VSET
MAKE_BASE=TRUETP_SMC_FAN_2_CTLSMC_FAN_2_CTL
MAKE_BASE=TRUETP_SMC_FAN_2_TACHSMC_FAN_2_TACH
MAKE_BASE=TRUETP_SMC_FAN_3_TACHSMC_FAN_3_TACH
TP_SMC_FAN_3_CTLMAKE_BASE=TRUE
SMC_FAN_3_CTL
TP_SMC_XDP_TCKMAKE_BASE=TRUE
SMC_XDP_TCK
TP_SMC_XDP_TMSMAKE_BASE=TRUE
SMC_XDP_TMSMAKE_BASE=TRUETP_SMC_XDP_TDO_LSMC_XDP_TDO_L
TP_SMC_XDP_TRST_LMAKE_BASE=TRUE
SMC_XDP_TRST_L
TP_SMC_P20MAKE_BASE=TRUE
SMC_P20
TP_SMC_P21MAKE_BASE=TRUE
SMC_P21
MAKE_BASE=TRUETP_SMC_P22SMC_P22
MAKE_BASE=TRUETP_SMC_P23SMC_P23
MAKE_BASE=TRUETP_SMC_P26SMC_P26
MAKE_BASE=TRUETP_SMC_P27SMC_P27
MAKE_BASE=TRUETP_SMC_PF0SMC_PF0
TP_SMC_PF1MAKE_BASE=TRUE
SMC_PF1
P0V46_SMC_LSREFVOLTAGE=0.46V
=PP3V3_S0_SMC_LS
CPU_PROCHOT_L
SMC_PROCHOT_3_3_L
SC_TX_L
SMC_EXCARD_OC_L
SMC_TPM_PP
SC_RX_L
TPM_PP
SMC_RX_L
TPM_GPIO1
SMC_TX_L 51
56
51
48
49
49
47
49
48
49
49 47
48
48
63
47
49
64
49
49
49
47
45
47
53
45
47
47
47
21
47
63
49
48
48
47
56
47
43
47
47
48
63
63
45
47
47
47
47
47
45
41
45
51
6
47
23
45
45
48
14
43
61
48
21
29 47
48
47
47
56
47
23
47
43
5
47
5
5
47
55
56
5
47
47
5
5
5
5
47
5
47
47
5
5
47
5
47
5
23
5
5
5
47 63
7
7
47
47
5
63
63
47
62
63
76
47
47
5
51 47
28 14
51 47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
63
7
47
47
47
47
47
56
5
56
5
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(GPIO15)
NC
516S0384NC
NCNC
QT500306-L021-9FM-ST-SM
LPCPLUSCRITICAL
J6000
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
4
56
78
9
LPC+ Debug ConnectorSYNC_DATE=07/20/2005SYNC_MASTER=M42
051-7099 D
10460
=PP3V3_S5_LPCPLUS=PP5V_S0_LPCPLUS
FWH_INIT_LPCI_CLK_PORT80_LPC
LPC_AD<2>LPC_AD<3>
INT_SERIRQPM_SUS_STAT_LSMC_TDISMC_TCKSMC_RST_LSMC_NMISMC_RX_L
SV_SET_UP
LPC_AD<0>LPC_AD<1>
BOOT_LPC_SPI_L
LPC_FRAME_LPM_CLKRUN_L
SMC_TMSDEBUG_RST_LSMC_TRST_LSMC_TDOSMC_MD1SMC_TX_L
56
56
56
56
56
48
56
56
56
47
48
47
47
47
47
48
48
48
48
47
47
47
47
40
48
48
48
63
63
21
34
21
21
23
23
47
47
47
47
47
23
21
21
22
21
23
47
26
47
47
47
47
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
SMBDATA
SMBCLK
ALERT*
OT2*
DXP2
OT1*
DXN
DXP1
GND
VCC
IO
IO
D+
D-
ALERT*/
THM*
SCLK
SDATA
VDD
GND
THM2*
SYM_1
SYM_1
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Right-Side/Fin Stack Thermal Sensor
Place near speaker holePlacement note:
518S0226
NC
NC
Placement note:Place in between VRAM
518S0226
NC
NC
Placement note:Place near GPU center
Minimize stubsLayout note:
Place U6150 below and to thePlacement note:
GPU / Heat Pipe Thermal Sensor
left of the speaker hole.
NC
NCNC
these R’s and R1001 & R1002Minimize stubs betweenLayout note:
programatically unstuff those parts to stuff these.
Placement note:Place near CPU center
CPU Back-Up Thermal Diode
R1001 / R1002 are not currently BOMOPTIONed. Can not
to U6100 as possibleKeep all 4 XWs as closePlacement note:
UMAXMAX6695AUB
CRITICAL
U6100
8
3
2
4
6
5
10
7
9
1
HSTHMSNS_HAS
402CERM50V10%
0.0022uFC6120 1
2
SMXW61201 2
SMXW61211 2
SMXW61111 2
GPUTHM_A_GPU
402MF-LF1/16W5%0R61101
2
GPUTHM_A_GPU
402MF-LF1/16W
5%0
R61111
2
1/16W
GPUTHM_A_DIODE
MF-LF
5%
402
0R61151 2
0
5%1/16WMF-LF402
GPUTHM_A_DIODE
R61161 2
SOT232N3904LFQ6115 1
3
2
SMXW61101 2
5%1/16WMF-LF402
0
CPUTHM_DIODE
R61901 2
CPUTHM_DIODE
402
0
5%1/16WMF-LF
R61911 2
SOT232N3904LFQ6190 1
3
2
10K
MF-LF402
5%1/16W
R61521
2
1/16W5%
402MF-LF
10KR61511
2
MSOP
ADT7461
CRITICAL
U61506
2
3
5
8
7
4
1
0.1UF
X5R402
10%16V
C6150 1
2
0.001UF
CERM402
20%50V
C61601
2
1%
499
402MF-LF1/16W
R61601 2
1%
499
MF-LF402
1/16W
R61611 2
10V20%
402CERM
0.1uFC61001
2
CRITICAL
88460-0201F-RT-SM
J6120
3
4
1
2
88460-0201F-RT-SM
CRITICALJ6160
3
4
1
2
1/16W5%
402MF-LF
47R61001 2
50V
0.0022uF
CERM402
10%
C6110 1
2
116S0004 1 RES,0,1/16W,0402 C6120 HSTHMSNS_NOT
Thermal Sensors
61 104
D051-7099
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
GPUTHMSNS_DX_A_N
CPUTHMSNS_DIO_N THRM_CPU_DX_N
THRM_CPU_DX_PCPUTHMSNS_DIO_P
GPUTHMSNS_DXP1
GPUTHMSNS_DXP2
PP3V3_S0_GPUTHMSNS_R
GPUTHMSNS_DXN=SMBUS_GPUTHMSNS_SDA=SMBUS_GPUTHMSNS_SCL
=PP3V3_S0_RSTHMSNS
RSTHMSNS_THM_L
RSTHMSNS_ALERT_L
=SMBUS_RSTHMSNS_SCL=SMBUS_RSTHMSNS_SDA
=PP3V3_S0_GPUTHMSNS
HSTHMSNS_DX_P
ATI_TDIODE_NATI_TDIODE_P
GPUTHMSNS_DX_A_PGPUTHMSNS_DX_A_DIO_P
GPUTHMSNS_DX_A_DIO_N
HSTHMSNS_DX_N
RSFSTHMSNS_D_P
RSFSTHMSNS_D_N
RSFSTHMSNS_D_R_PRSFSTHMSNS_D_R_N
10
10
27
27
63
27
27
63
5
72
72
5
5
5
IN
OUT
G
S D
D S
G
N-CHN
S
D
G
P-CHN
G
DS
N-CHN
S
D
G
P-CHN
G
DS
OUT
OUTIN OUTIN
OUTIN IN OUT
OUTINOUTIN
OUTIN
OUT
G
D
S
G
D
S
G
D
S
G
D
S
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Place RC close to SMC
Rthevanin = 4573 ohms
PBUS Voltage Sense Enable & Filter
Place RC close to SMC
SMC_ONOFF_L is low (power buttonEnables PBUS VSense divider when
Enables PBUS VSense divider when high.
1.8V S3 (Memory) Current Sense Filter
Switches in fixed load on power supplies to calibrate current sense circuits
Place short near U0700 center
1.0A / 1.8W
CPU Voltage Sense / Filter
Place RC close to SMC Place RC close to SMC
Place RC close to SMC Place RC close to SMC
1.05V S0 (NB) Current Sense Filter
Place RC close to SMC
Place RC close to SMC
1.2A / 1.44W 1.05A / 1.1W
FireWire Current Sense Filter
GPU Current Sense Filter
Place RC close to SMC
Battery Current Sense Filter
Place RC close to SMC
Current Sense Calibration Circuit
Place short near U8400 center
CPU Current Sense Filter
This half of Q6216 acts as adiode to keep Q6215 frompulling SMC_ONOFF_L low.
DCIN Current Sense Filter
GPU Voltage Sense / Filterpressed or driven low by SMC)
between PBUS and 3.42Vas a level-shifterThis half of Q6216 acts
R5808 is pull-up
470K5%1/16WMF-LF402
R62281
2
402MF-LF1/16W
5%100K
R62271
2
1%1/16WMF-LF
402
100KR62151
2
27.4K1%
1/16WMF-LF
402
R62851
2
6.3V
0.22UF
402X5R
20%
C62851
2
5.49K
402MF-LF1/16W
1%
R62861
2
2N7002DW-X-FSOT-363
Q6216
3
5
4
2N7002DW-X-FSOT-363
Q62166
2
1
FDG6332C_NLSC70-6
Q6229
6
2
1
FDG6332C_NLSC70-6
Q6229
3
5
4
FDG6332C_NLSC70-6
Q6215
6
2
1
FDG6332C_NLSC70-6
Q6215
3
5
4
0.22UF20%6.3VX5R402
C62591
2
1%1/16WMF-LF402
4.53KR62591 2
1/16W
4.53K
402MF-LF
1%
R62701 2
6.3V
0.22UF
402X5R
20%
C62701
220%
X5R402
0.22UF6.3V
C62751
2
1%1/16WMF-LF402
4.53KR62751 2
6.3V
0.22UF
402X5R
20%
C62801
2
4.53K
402MF-LF1/16W1%
R62801 2
1%1/16WMF-LF402
4.53KR62901 2
20%
X5R402
0.22UF6.3V
C62901
2
20%
X5R402
0.22UF6.3V
C62401
2
1%1/16WMF-LF402
4.53KR62401 2
6.3V
0.22UF
402X5R
20%
C62351
2
4.53K
402MF-LF
1%1/16W
R62351 2
20%
X5R402
0.22UF6.3V
C62301
2
1%1/16WMF-LF402
4.53KR62301 2
SMXW62591 2
4.53K
402MF-LF1/16W1%
R62091 2
402X5R6.3V20%0.22UFC62091
2
SMXW62091 2
1206MF-LF1/4W
1%1.00
R62201
2470K
5%1/16WMF-LF
402
R62291
2
CRITICAL
FDC796NSUPERSOT-6
Q6220
7
4
1 2 3 5 6
1206MF-LF1/4W
1%1.00
R62211
2
SUPERSOT-6
CRITICAL
FDC796NQ6221
7
4
1 2 3 5 6
1.821%
1/4WMF-LF1206
R62221
2
FDC796N
CRITICAL
SUPERSOT-6
Q6222
7
4
1 2 3 5 6
1.001%
1/4WMF-LF1206
R62231
2
SUPERSOT-6
CRITICAL
FDC796NQ6223
7
4
1 2 3 5 6
Current & Voltage Sensing
62 104
D051-7099
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
=PP3V42_G3H_PBUSVSENS
SMC_ONOFF_L PBUSVSENS_PWRBTN_L
SMC_FWIRE_ISENSE
P1V05S0_IOUT
CPUVCORE_ISENSE_CALMIN_LINE_WIDTH=0.50 mmMIN_NECK_WIDTH=0.20 mm
=PP1V05_S0_REG
P1V05S0_ISENSE_CALMIN_LINE_WIDTH=0.50 mmMIN_NECK_WIDTH=0.20 mm
=PPVCORE_S0_GPU
GPUVCORE_ISENSE_CALMIN_LINE_WIDTH=0.50 mmMIN_NECK_WIDTH=0.20 mm
=PPVCORE_S0_CPU
GND_SMC_AVSS
=PPVCORE_S0_GPU
GND_SMC_AVSS
SMC_CPU_VSENSE
SMC_GPU_VSENSE
CPUVSENSE_IN
GPUVSENSE_IN
GND_SMC_AVSSGND_SMC_AVSSGND_SMC_AVSS
SMC_P1V05S0_ISENSESMC_P1V8S3_ISENSEP1V8S3_IOUTSMC_GPU_ISENSEGPUVCORE_IOUTSMC_CPU_ISENSECPUVCORE_IOUT
GND_SMC_AVSS
SMC_BATT_ISENSELIO_BATT_ISENSE
GND_SMC_AVSS
SMC_DCIN_ISENSEFWPWR_IOUT
=PPVCORE_S0_CPU
GND_SMC_AVSS
LIO_DCIN_ISENSE
P1V8S3_ISENSE_CALMIN_LINE_WIDTH=0.50 mmMIN_NECK_WIDTH=0.20 mm
=PP1V8_S3_REG
GND_SMC_AVSS
ISENSE_CAL_EN_LS5V
ISENSE_CAL_EN_L
=PP5V_S0_ISENSECAL
ISENSE_CAL_EN
=PBUSVSENS_EN
PPBUS_G3H
PBUSVSENS_EN_L
VOLTAGE=12.6VPPBUS_G3H_VSENSE
SMC_PBUS_VSENSE
GND_SMC_AVSS
48
72 63
53
72
53
53 53 53
53 53
63
53
53
53
47
63 67 51
51
67
51
51 51 51
51 51
51
51
63
51
51
43
61 63 9
48
63
48
48 48 48
48
45
48
9
48
45
60
48
63
47
48
63
5
47
61
5 51 8
47
51
47
47
47
47 47 47
48 48 60 47 66 47 57
47
47 5
47
47 41
8
47
5
5
47
5
5
62
63
47
47
SCK
SOWP*
SI
VDD
CE*
HOLD*VSS
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
R6307 AND R6306 SHOULD BE PLACED LESS THAN 100 MILS FORM ICH7M
R6303 SHOULD BE PLACED LESS THAN 100 MILS FORM FLASH ROM ICH7M AND TEKOA(LAN CHIP) R6309 IS NOT NEEDED WHEN SHARING SPI FLASH WITH
402CERM10V20%0.1UFC63121
21/16W402
5%MF-LF
3.3KR63011
2402
3.3K5%
1/16WMF-LF
R63021
2
22pF
402CERM5%50V
C63011
2
MF-LF402
5%1/16W
47R63071 2
402
22pF50V5%CERM
C63081
2
5%CERM50V402
22pFC63091
2
402MF-LF
475%
1/16W
R63031 2
47
1/16WMF-LF5%
402
R63061 2
22pF
402CERM5%50V
C63111
2
OMITCRITICAL
16MBIT
SST25VF016B
SOI
U6301
1
7
6 5
2
8
4
3
402
5%10K1/16WMF-LF
R6308
12
NOSTUFF
10K5%1/16WMF-LF402
R6309
12
63
SPI BOOTROM
051-7099 D
104
SYNC_MASTER=M42SYNC_DATE=11/16/2005
=PP3V3_S5_ROM
SPI_SO_R
SPI_SI_RSPI_SCLK SPI_SCLK_R SPI_SI
SPI_SOSPI_CE_L
SPI_HOLD_LSPI_WP_L
47 47
47 47
63
22 22
22 22
V+
V-
G
D
SIN
OUT
NC
CNTRL
THRML_PAD
VDD SW
AGNDPGND
FB
VOUT
ININ
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Left ALS circuit has 1K series-R
Left ALS Filter
Keyboard LED Driver
NC
NC
Right ALS Circuit
RTALS_OP_IN and RTALS_OP_COMP need to be matchedMAX4236EUTTSOT23-6-LF
CRITICALU6405
3
4
1
5
6
2
CERM402
20%10V
0.1UFC6405 1
2
120K
MF-LF402
5%1/16W
R64061
2
0.22UF
X5R402
20%6.3V
C6406 1
2
15.0K
MF-LF402
1%1/16W
R64071
2
1K
MF-LF402
1%1/16W
R64081
2
MF-LF402
1%1/16W
1KR64011 2
BS520EOFTH
CRITICALPD6400
1
2
5.1M
MF-LF402
5%1/16W
R64001
2
0.01UF
CERM
20%16V
402
C64001
2
2N7002SOT23-LF
Q64083
1
2
4.53K
MF-LF402
1%1/16W
R64101 2
0.22UF
X5R
20%6.3V
402
C64101
2
MM3120LLP
CRITICAL
U6450
2
3
46
5
7
9
1
8
22uH
3.8x3.8x1.5MM
CRITICALL6450
1 2
1uF
CERM402
10%6.3V
C6450 1
2
KBDLED_NOT
10K
MF-LF402
5%1/16W
R64511
2
MF-LF
5%1/16W
KBDLED_HAS
10K
402
R64521
2
0.22uF20%25VX5R603
C64551
2
25.5
805
1%1/8WMF-LF
R64551
2
6.3V20%
402X5R
0.22UFC64301
2
1/16W1%
402MF-LF
3.48KR64301 2
ALS Support
64 104
051-7099 D
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
=RTALS_GAIN
RTALS_OP_COMP
=PP3V3_S3_RTALS
ALS_RT_OUT ALS_RIGHT
GND_SMC_AVSS
RTALS_OP_INRTALS_PHOTODIODE
RTALS_GAIN_L
SMC_SYS_KBDLED
=PP3V3_S0_KBDLED
KBDLED_RETURN
KBDLED_ANODE
KBDLED_SW=PP5V_S0_KBDLED
GND_SMC_AVSS
LTALS_OUT ALS_LEFT
53
53
51
51
48
48
76
6
63
47
47
47
63
43
43
63
47
5 47
G
S D
G
S D
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Left Fan
518S0293518S0293
NC
NC
NC
NC
Right Fan
1/16W
47K
402MF-LF
5%
R65501
2
5%1/16WMF-LF402
47KR65551 2
402MF-LF1/16W
5%47K
R65601
247K
402MF-LF1/16W5%
R65651 2
402MF-LF
5%1/16W
100KR65511
2
CRITICAL
SM-2MT-LFJ65505
6
1
2
3
4
SM-2MT-LF
CRITICAL
J65605
6
1
2
3
4
2N7002DW-X-FSOT-363
Q6560
3
5
4
100K1/16W
5%
MF-LF402
R65611
2 SOT-3632N7002DW-X-FQ6560
6
2
1
Fan Connectors
D051-7099
10465
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
FAN_RT_TACHFAN_LT_TACH
=PP5V_S0_FAN_LT
SMC_FAN_0_TACH
SMC_FAN_0_CTL
=PP3V3_S0_FAN_LT
FAN_LT_PWM SMC_FAN_1_CTL FAN_RT_PWM
SMC_FAN_1_TACH
=PP3V3_S0_FAN_RT=PP5V_S0_FAN_RT63
5 5
5
47
47
63
5 47 5
47
63
63
OUTPUTY
OUTPUTZ
DNC
RSVD
TESTSELF
PS
PARITY
RSVD
RSVD
RSVD
GND PADTHRML
OUTPUTX
VDD
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
M1 placement: Bottom-side
placed on board bottom-side:placed on board top-side:
1
Desired orientation when Desired orientation when
+X
+Z (dn)
+Y
Top-through ViewPackage Top
1+Y
+Z (up)
+X
NC
NC
0.1uF
CERM402
20%10V
C66201
2
QFNKXM52-2050
CRITICAL
U6620
1
3 12
2
13
145
9
4
6
7
11
10
15
8
402
1/16W5%
MF-LF
10KR66212
1
10K
MF-LF402
5%1/16W
R66201
2
0.033UF
X7R402
20%10V
C66051
2 10V20%
402X7R
0.033UFC66061
210V20%
402X7R
0.033UFC66041
2
66 104
D051-7099
Sudden Motion Sensor (SMS)SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
SMS_Z_AXIS
=PP3V3_S3_SMS
SMS_X_AXIS
SMS_Y_AXISSMS_ONOFF_L
SMS_ACC_SELFTEST
63
47
48
47
47 47
IN
IO
IO
IO LAD1
LAD2
LCLK
LFRAME*
LRESET*
LPCPD*
SERRIRQ
LAD0
CLKRUN/GPIO*
PP/GPIO
GPIO_EXPRESS_00
GPIO/SM_DAT
GPIO/SM_CLK
XTALI/32K_IN
TESTBI/BADD/GPIO
TESTI
3V0
3V1
3V2
3VSB
VNC
VBAT
XTALO
GND2
GND3
GND0
GND1
LAD3
IO
IO
IN
IN
IO
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
BASE ADDR = 0X4E/4F
GPIO2TESTBI/BADD
1/8W (R6704/R6705) IS USED FOR NOWSINCE CURRENT OF VSB IS NOT YET ON SPEC,NOTE:
PLACE R6702-03 WHERE ACCESSIBLELAYOUT NOTE:
PLACE WHERE ACCESSIBLELAYOUT NOTE:
BASE ADDR = 0X2E/2F
NC
NC
NC
CLKRUN*
GPIO
PP
NC
VDD
VDD
VDD
VSB
NC
NC
GND
(INT PD)
402X5R16V10%0.1UFC67001
2
0.1UF
402X5R16V10%
C67011
2
0.1UF10%16VX5R402
C67021
2
0.1UF10%16VX5R402
C67031
2
NOSTUFF
05%1/16WMF-LF402
R67001
2
OMIT
TSSOPTPM
U6700 101924
5
15
4111825
216
26232017
2122
2816
7
27
98
12
3
1314
MF-LF1/16W5%10K
402
R67021
2
NOSTUFF
5%1/16WMF-LF
10K
402
R67031
2
805MF-LF1/8W5%
0R67041 2
NOSTUFF
805MF-LF1/8W5%0R67051
2
05%
MF-LF1/16W402
R67981 2
MF-LF5%
0
NOSTUFF
1/16W402
R67991 2
TPMSYNC_DATE=11/16/2005SYNC_MASTER=M38
051-7099 D
67 104
SMC_TPM_RESET_L
TPM_LRESET_L
TPM_RST_L
TPM_BADD
LPC_AD<0>LPC_AD<1>LPC_AD<2>
PCI_CLK_TPMLPC_FRAME_L
PM_SUS_STAT_LINT_SERIRQ
=PP3V3_S0_TPM
TPM_XTALOTPM_XTALI
PM_CLKRUN_L
=PP3V3_S3_TPM
=PP3V3_S0_TPM
LPC_AD<3>
TPM_GPIO2
TPM_GPIO1TPM_PP
MIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.6MMVOLTAGE=3.3VPP3V3_TPM_3VSB
49
49
49
49
49
49
48
49
47
49
47
47
47
47
47
47
40
47
48
21
21
21
21
23
23
63
23
63
63
21
47
26
5
5
5
34
5
5
5
56
35
35
5
48
56
5
48
48
48
TPADVSS
BOOT2
BOOT1
PHASE1
UGATE1
LGATE1
PGND1
ISEN1
UGATE2
PHASE2
LGATE2
PVCCVDDVIN
PGND2
VID6
VID5
VID4
VID2
VID3
VID1
VID0
ISEN2
VSUM
OCSET
VO
DROOP
DFB
VSEN
RTN
DPRSTP*
DPRSLPVR
PSI*
PGD_IN
3V3
CLK_EN*
PGOOD
VR_ON
NTC
VR_TT*
SOFT
RBIAS
VDIFF
FB2
FB
COMP
VW
NC
IN
IN
IN
IN
OUT
IN
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
0 1 0 1-Phase CCM
DPRSLPVR DPRSTP* PSI* Operation Mode
1 0 1 1-Phase DCM
(GND)
(IMVP6_COMP)
(GND_IMVP6_SGND)
(GND_IMVP6_SGND)
(GND)
(IMVP6_VW)
These caps for Q7550
(Inductors limit)
Vout = Variable36A max output
These caps for Q7500
(IMVP6_PHASE2)
(IMVP6_ISEN1)
(IMVP6_PHASE2)
<Rb>
(IMVP6_ISEN2)
<Ra>
(IMVP6_VSUM)
(IMVP6_VO)
<Rc>Voffset = (Vdrp_offset * Kdroop) + Vamp_offset
Voffset worst-case ~2.3mV (+/- ~1A offset)
Gain = Rc / (Ra + Rb)
Vout @ 36A = 2.44V-2.60V
1 1 0 1-Phase DCM
0 1 1 2-Phase CCM
(IMVP6_VO)
(IMVP6_FB)
Vout = Gain * ((2.1 mV/A * Iload) + Voffset)
<Rc>
<Ra + Rb>
CPU VCore Current Sense
(IMVP6_NTC)2
1 C7501
402CERM
NO STUFF
10%0.0022UF50V 2
1 C7502
402CERM
10%50V
NO STUFF
0.0022UF
21
R7505
402
10K
MF-LF1/16W1%
21
C7505
20%
402X5R6.3V
0.22UF
2
1R75063.65K
MF-LF
1%
603
1/10W
2
1R7532147K1%1/16W
402MF-LF2
1C7532
402
0.015uF10%16VX7R
2
1C7531
402
0.1uF
X5R
10%16V
9
19
21
14
5
44
18
20
43
42
41
40
39
38
37
13
22
27
35
49
7
15
4
31
2
28
34
129
33
3
8
6
25
30
32
23
24
12
11
16
46
45
17
10
47
26
36
48
U7530QFN
OMIT
ISL6262
2
1R7535
MF-LF402
1.82K1%
1/16W
2
1R75374.42K
402
1%
MF-LF1/16W
2
1C7537
CERM50V5%
47pF
4022
1R75341%
MF-LF402
1/16W
182K
2
1C7535
50V10%
402CERM
330pF
2
1 C7500
25VX5R603
0.22uF20%
2
1C7550
603X5R25V
0.22uF20%
2
1R7542
MF-LF
1%1/16W
402
9.31K
21
R75403.01K
1/16W1%
402MF-LF
2
1R7541
402MF-LF
1K1%1/16W
2
1C7540180pF
50V5%
402CERM
21
R7545499
1%1/16W
402MF-LF
7 21
14 23 79
7
62
26
47
14 26
321
4
5
Q7501LFPAKHAT2165H
CRITICAL
321
4
5
Q7502HAT2165H
CRITICAL
LFPAK
321
4
5
Q7500HAT2168H
CRITICAL
LFPAK
2
1C751022UF
X5R1210
20%16V 2
1C7511
1210
16VX5R
20%22UF
2
1C751220%
22UF
1210X5R16V
21
R7555
402
10K
1/16WMF-LF
1%
321
4
5
Q7550CRITICAL
LFPAKHAT2168H
21
C75550.22UF
20%
402X5R6.3V
2
1R7556
MF-LF
1%
603
1/10W
3.65K321
4
5
Q7552HAT2165H
CRITICAL
LFPAK
2
1 C75520.0022UF
CERM
10%50V
402
NO STUFF
321
4
5
Q7551CRITICAL
HAT2165HLFPAK
2
1 C7551
402CERM
0.0022UF10%50V
NO STUFF
2
1C75301uF10%
402
6.3VCERM
21
R7530
MF-LF1/16W5%
10
402
C7513
X5R1210
20%16V
22UF
2
1R7536
402MF-LF1/16W1%2.0K
NO STUFF
2
1R75331%1.40K1/16W
402MF-LF
2
1C7533
CERM50V
470pF10%
402
2
1C7544
6.3V
402
0.22uF
X5R
20%
2
1R7543
402
11K1/16W1%
MF-LF
21
R7593
MF-LF402
1/16W1%
30.1K
21
R7591
MF-LF1/16W
402
1%
30.1K
2
1C7528
603X5R
10%1uF16V
2
1 C75294.7uF
CERM6.3V20%
603
21
R7531
402
1/16WMF-LF
10
5%
21
R7528
1/16W5%
10
402MF-LF
2
1C7546
CERM16V10%
0.01uF
402
2
1R7547
1/16W
402
1%4.02K
MF-LF
2
1R7544
402MF-LF1/16W1%499
2
1C754120%
6.3VX5R402
0.22UF
2
1C758010%
CERM402
0.0068uF25V
2
1C7542NO STUFF
0.001uF50V10%
402CERM
2
1R7548
MF-LF
3.92K1/16W
402
1%
2
1 C7543
CERM
0.01uF10%16V
402
2
1R7507
MF-LF1/16W
15%
402
2
1R75575%
1/16WMF-LF
1
402
2
1 C7581NO STUFF
CERM
10%16V
0.01uF
4022
1C7582
402CERM
0.01uF16V10%
21
R7581
1/16WMF-LF
5%
402
0
21
R7582
5%1/16WMF-LF402
0
21
R7598
MF-LF1/16W1%
1M
402
2
5
1
4
3
U7595SOT23-5
LMV2011MF
21
R7592
1/16W
402MF-LF
1M
1%
51
2
1C75951uF
402
10%6.3VCERM
2
1
R754910KOHM-5%0603-LF
CRITICAL
21
C7598
402CERM
10%50V
470pF
21
C7592
10%50VCERM
470pF
402
2
1 C7534
402
390pF10%50VCERM
2
1
D7500CRITICAL
SMBB340LBXF
2
1
D7550CRITICAL
B340LBXFSMB
2
1
R7546470K
402
CRITICAL
C756322UF
1210X5R16V20%
2
1C7562
1210
22UF
X5R16V20%
2
1C756122UF
16V
1210X5R
20%2
1C756022UF
X5R1210
20%16V
21
L75050.36uH
CRITICAL
SM-PCC
21
L7555CRITICAL
0.36uH
SM-PCC
21
R7594
MF-LF402
1/16W
0
5%
2
1 C7594
402CERM10V20%
NO STUFF
0.1uF
2 1
XW7530SM
051-7099 D
75 104
IMVP6 CPU VCore RegulatorSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
IMVP6_COMP
IMVP6_NTC
GND_IMVP6_SGND
IMVP6_OCSET
IMVP6_DROOP
IMVP6_LGATE2 MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
IMVP6_ISEN2
IMVP6_VSEN_PIMVP6_VSEN_N
IMVP6_VO_R
IMVP6_DFB
=PP3V3R5V_S0_CPUISENSCPUISENS_NEG_RCCPUISENS_NEG
CPU_PSI_LMIN_NECK_WIDTH=0.25 mmIMVP6_UGATE2 MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mmVOLTAGE=5V
MIN_LINE_WIDTH=0.25 mmPP5V_S0_IMVP6_VDD
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmPP3V3_S0_IMVP6_R
VOLTAGE=3.3V
IMVP6_VW
IMVP6_BOOT2
IMVP6_DROOP
CPU_VCCSENSE_N
CPUVCORE_IOUT
IMVP6_LGATE1 MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
CPUISENS_POS
=PPVIN_S0_IMVP6
IMVP6_ISEN1
IMVP6_UGATE1 MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
IMVP6_VR_TT
=PP5V_S0_IMVP6
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmPPVIN_S0_IMVP6_R
VOLTAGE=12V
=PPVIN_S0_IMVP6
=PP3V3_S0_IMVP6
IMVP6_FB2
IMVP6_VDIFF
IMVP6_VDIFF_RC
IMVP6_FB
IMVP6_SOFT
IMVP6_RBIAS
IMVP6_NTC_R
IMVP_PWRGD_IN
IMVP_VR_ON
IMVP6_COMP_RC
IMVP6_VID<2>IMVP6_VID<1>
IMVP6_VID<3>
VR_PWRGD_CK410_L
CPU_DPRSTP_L
IMVP6_VID<0>
IMVP6_VID<4>IMVP6_VID<5>IMVP6_VID<6>
VR_PWRGOOD_DELAY
PM_DPRSLPVR
IMVP_DPRSLPVR
IMVP6_PHASE1 MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
IMVP6_VO
IMVP6_VSUM
=PPVOUT_S0_IMVP6_REG
IMVP6_BOOT1
IMVP6_PHASE2 MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
CPU_VCCSENSE_P
79
63
63
79
5
57
79
79
63
57
8
57
63
57
63
5
9
9
9
9
9
9
9
79
63
8
NC4
NC3
NC2
NC1
EXTVCC
FCB
INTVCC
PGOOD
3_3VOUT
RUN_SS2
ITH2
RUN_SS1
ITH1
SW1
TG1
BOOST1
BG1
PLLIN
SENSE1+
SENSE1-
VOSENSE1
BOOST2
TG2
BG2
SW2
PLLFLTR
SENSE2+
VOSENSE2
SENSE2-
THRML_PAD
SGND
PGND
VING
D
S
G
D
S
G
D
S
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Connect to RUNSS pins to control outputs.
NOTE: Be aware of pull-ups to VIN on these signals.
<Rb>
5V S3 FET
If unconnected, powers up with VIN.
(L7660 & Q7660 limit)8A max outputVout = 1.49V
<Rb>
<Ra>
Vout = 0.8V * (1 + Ra / Rb)
NC
NC
NCNCNC
NC
Vout = 4.98V
(L7620 limit)8A max output
<Ra>
5V S0 FET
CRITICAL
CMDSH-3SOD-323D7624
1
2
1uF
CERM402
10%6.3V
C7605 1
2
16V10%
402
0.01uF
CERM
C76071
2
22UF20%16VX5R1210
C76401
2
1/16W5%
402MF-LF
1MR76301
2
0.1uF20%
CERM402
10V
C76301
2
22K5%1/16W
402MF-LF
R76251
2
50V10%
402
470pF
CERM
C7625 1
250V5%
402
47pF
CERM
C76261
2
10
402
1/16WMF-LF
5%
R76001
2
10%
X5R603
1uF16V
C76001
2
CRITICAL
QFNLTC3728LXCU7600
7
18
17
21
4
20
5 8
10
16
29
32
19
27
2
28 13
30 12
11
6
15
26 14
33
1 9
CRITICAL
CMDSH-3SOD-323D7664
1
2
10V20%
402CERM
0.1uFC7670 1
2
CERM50V10%
402
470pFC76651
2
100pF
CERM402
5%50V
C7666 1
2
10K
MF-LF402
5%1/16W
R76651
2
CERM50V
0.001uF
402
10%
C76621
2
470pF
CERM402
10%50V
C76271
2
52.3K1/16W
402MF-LF
1%
R76271
2
25V
402X7R
1000pF
NO STUFF
10%
C76281
2
10K1/16WMF-LF
402
1%
R76281
2
IHLP2525CZ-SM
CRITICAL
2.2uH-14AL7660
1 2
39.2K
402
1%1/16WMF-LF
R76681
2
NO STUFF
25V10%
402X7R
1000pFC7668 1
2
34.0K1/16W1%
MF-LF402
R76671
2
470pF50V10%
402CERM
C7667 1
2
MF-LF1/16W
5%
402
1MR76701
2
402
6.3V10%1uF
CERM
C76021
2
603
6.3V20%
4.7uF
CERM
C7601 1
2MF-LF402
5%1/16W
30KR76031
2
1K
MF-LF402
5%1/16W
R76041
2
0.01uF
CERM402
10%16V
C76041
2
22UF20%16VX5R1210
C76411
2
22UF20%16VX5R
1210
C7680 1
2 X5R
22UF20%16V
1210
C7681 1
2
MF-LF402
1/16W
05%
R76641
2MF-LF
0
402
5%1/16W
R76241
2
CRITICAL
FDC796NSUPERSOT-6
Q7660
7
4
1 2 3 5 6
B240-X-FSMB
CRITICALD7621
1
2
SUPERSOT-6FDC796N
CRITICAL
Q7620
7
4
12356
SUPERSOT-6FDC796N
CRITICAL
Q7621
7
4
12356 NO STUFF
10%25VX7R402
1000pFC7661 1
2
402
0.1uF
CERM10V20%
C7664 1
2
805CERM6.3V20%22UFC76901
2
805CERM6.3V20%
22UFC7691 1
2
20%10VCERM402
0.1uFC76241
2
NO STUFF
402X7R25V10%1000pFC76211
2
10%
CERM50V
0.001uF
402
C7622 1
2
20%
CRITICAL
SMC-LFPOLY6.3V
150uFC7652 1
220%
22UF6.3VCERM805
C7650 1
2
CERM805
22UF20%6.3V
C76511
2
1/16W5%
402MF-LF
0
P5VP1V5_SKIPR76061
2
0
MF-LF402
P5VP1V5_CONT
5%1/16W
R76071
2
SMXW76001 2
402X5R
0.1uF10%16V
C7620 1
2
1%3.92K1/16WMF-LF402
R76201
2
0.1uF10%16VX5R402
C76231
2
9311/16WMF-LF
402
1%
R76231
2
0.1uF10%16VX5R402
C76601
2
1%
402
1/16WMF-LF
3.65KR76601
2
0.1uF
402X5R16V10%
C7663 1
2
1%909
402MF-LF1/16W
R76631
2
CASE-D2E-LF
330uF
CRITICAL
POLY
20%2.5V-ESR9V
C76921
2CRITICAL
IRF7832PBFSO-8
Q7661
5 6 7 8
4
1 2 3
SM5
4.7uH
CRITICALL7620
1 2
1%1.21K
MF-LF1/16W
402
R76691
2
1%1.21K
MF-LF1/16W
402
R76291
2
22UF
805CERM6.3V20%
C76171
2
22UF
805CERM6.3V20%
C7616 1
2
0.0022uF
402CERM50V10%
C76151 2
FDC638PSM-LF
Q7615
1
2
5
6
3
4
100K
5%1/16WMF-LF402
R76151 2
FDC638PSM-LF
Q7610
1
2
5
6
3
4
0.0022uF
402CERM
10%50V
C76101 2
MF-LF1/16W5%
402
100KR76101 2
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
5V / 1.5V Power Supply
051-7099 D
10476
P5VS5_SNS_N
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
=PP5V_S5_REG
P5VS5_SNS_P
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm P5VS5_SW
P5VS5_VOSNS P1V5S0_VOSNS
MIN_LINE_WIDTH=0.6 mmVOLTAGE=0V
MIN_NECK_WIDTH=0.25 mm
GND_P5VP1V5_SGND
=PP1V5_S0_REG
P1V5S0_SNS_R_P
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
P1V5S0_SNS_R_N
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
P5VP1V5_FSEL
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmP1V5S0_BOOST
MIN_LINE_WIDTH=0.6 mm P5VS5_BGMIN_NECK_WIDTH=0.25 mm
P5VS5_ITH
P5VP1V5_FSEL
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5VPP5V_S5_P5VP1V5_INTVCC
MIN_LINE_WIDTH=0.6 mm
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=12VMIN_NECK_WIDTH=0.25 mm
PPVIN_S5_P5VP1V5_R
P1V5S0_RUNSS
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmP1V5S0_BG
P5VS5_ITH_RC P1V5S0_ITH_RC
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP1V5S0_TG
PP5V_S5_P5VP1V5_INTVCC
=PP5V_S3_P5VS3
P5VS3_EN_L_RC
=PP5V_S0_P5VS0
=PP5V_S0_FET
=P5VS0_EN_L
=PP5V_S3_FET
P5VS0_EN_L_RC
P5VP1V5_FCB
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP1V5S0_SW
P5VS5_BOOSTMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm
P5VS5_TGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
P5VS5_BOOST_RCMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
PP5V_S5_P5VP1V5_INTVCC
P5VS5_RUNSS
=P5VP1V5_PGOOD
P1V5S0_ITH
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP1V5S0_BOOST_RC
=P5VS3_EN_L
=PP5V_S5_P5VP1V5_VCC
=PPVIN_S5_P5VP1V5
63
62
63 5
58
58
58
58
63
63
63
62
63
58
5
62
62
63
63
PVINSVIN
SHDN/RT
SYNC/MODE
SW
VFB
ITHPGOOD
PGND SGND
SW
SGND PGND PADTHERM
SVIN PVIN
PGOOD
VFB
ITHSYNC/MODE
RUN/SSRT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(Switcher limit)1.25A max output
Continuous
Burst
NOTE: Be aware of pull-up on this signal.
Connect RUNSS off-page to controlIf unconnected, powers up with PVIN.
ContinuousMode
2.5V S3 Regulator
2.5V S0 FET
1.2V S0 FET
Vout = 0.8V * (1 + Ra / Rb)
Vout = 0.8V * (1 + Ra / (Rb + Rc))
<Rc>
<Rb>
<Ra>
1.2V S3 Regulator
<Ra> Vout = 2.52V
Vout = 1.205V2.5A max output(Switcher limit)
<Rb>
LTC3411
CRITICAL
MSOP-LF
U7700
10
5
8
6
3
1
7
4
2 9
CERM
100pF
402
5%50V
C7703 1
2
4.99K
MF-LF402
1%1/16W
R77061
2
0.0033uF
CERM402
10%50V
C77041
2
2.2uH-1.32A
CDRH4D18-SM
CRITICALL7700
1 2
22pF5%
CERM402
50V
C7706 1
2
10K1/16W1%
MF-LF402
R77071
2
4.7K
MF-LF402
1%1/16W
R77081
2 805CERM
22UF20%6.3V
C77091
2
1uF
CERM402
10%6.3V
C77011
2
1/16W5%
402MF-LF
10R77001 2 10UF
603X5R6.3V20%
C77001
2
MF-LF402
1%324K1/16W
R77051
2
1M
MF-LF402
5%1/16W
R77041
2
1/16W5%
402MF-LF
1MR77011
2
SMXW77001 2
6.3V20%
805CERM
22UFC77561
2
6.3V20%
805CERM
22UFC7755 1
2
22UF
CERM805
20%6.3V
C77521
2805
22UF
CERM6.3V20%
C7751 1
2
50V5%
402CERM
22pFC77501
21/16W
1%
402MF-LF
47.0KR77501
2
MF-LF402
1%1/16W
61.9KR77511
2
SM-LF
CRITICAL
1.0UH-3.48AL7750
1 2
MF-LF402
1%1/16W
30.9KR77521
2
CRITICAL
TSSOP-LFLTC3412U7750
3
12
13
2
9 16
5
7
8
110
11
14
15
6
17
4
SMXW77501 2
309K
MF-LF402
1%1/16W
R77541
2
50V
470pF
CERM402
10%
C7757 1
2
1/16W5%
402MF-LF
0
NO STUFF
R77551
21/16W
5%
402MF-LF
1MR77571
2
0
MF-LF402
5%1/16W
R77561
2
CERM402
5%50V
22pFC7754 1
2
MF-LF402
1%1/16W
8.25KR77531
2
CERM402
10%50V
0.0022uFC77531
2
SI3446DVTSOP-LF
Q77201
2
5
6 3
450V
0.0022uF10%
CERM402
C7720 1
2
402
5%1/16WMF-LF
100KR77201 2
TSOP-LFSI3446DVQ7770
1
2
5
6 3
4
10%50V
402
0.0022uF
CERM
C7770 1
2
5%1/16WMF-LF402
100KR77701 2
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
2.5V & 1.2V Regulators
D051-7099
77 104
PPVIN_S3_P2V5S3_SVIN
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmVOLTAGE=3.3V
P2V5S3_ITH=P2V5S3_PGOOD
P2V5S3_ITH_RC
=PP2V5_S3_REG
P2V5S3_VFB
=PP1V2_S3_REG
P1V2S3_VFB
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP1V2S3_SW
MIN_NECK_WIDTH=0.25 mmP2V5S3_SW
MIN_LINE_WIDTH=0.5 mm
=P1V2S3_PGOOD
P2V5S0_EN_RC=P2V5S0_EN
=PP1V2_S0_FET=PP1V2_S0_P1V2S0
=P1V2S0_EN
=PP2V5_S0_FET=PP2V5_S0_P2V5S0
=P2V5S3_EN_L
=PPVIN_S3_P2V5S3
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmVOLTAGE=0VGND_P2V5S3_SGND
P2V5S3_MODE
P2V5S3_SHDNRT
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmVOLTAGE=0VGND_P1V2S3_SGND
P1V2S3_ITHP1V2S3_MODE
P1V2S3_RUNSS
P1V2S3_ITH_RC
P1V2S3_VFB_DIV
P1V2S3_RT
=PPVIN_S3_P1V2S3
P1V2S0_EN_RC
39
39
62
63
63
62
62
63 63
62
63 63
39
63
5
5
5
5
63
PGND
PHASE
UG
LG
PVCC
FCCM
EN
PGOOD
COMP
FSET
ISEN
FB
VO
BOOT
VIN
THRMLPAD
VCC
OUT
G
D S
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
1.8V S3 Current Sense
(Q7820 limit)17A max output
Vout = 0.6V * (1 + Ra / Rb)
<Rb>
(P1V8S3_FB)
R7894 and R7897
<Ra>
NC
close to inductor
Placement Note:Keep C7890, R7890,
1.8V S0 FET
Vout = 1.83V
20%2.5V-ESR9V
CASE-D2E-LFPOLY
330uFC7842 1
21/16WMF-LF
402
3.32K1%
R78211
2
1.62K
MF-LF402
1%1/16W
R78221
2
1.0uH-20.5
SM1
CRITICAL
L7820
1
2
3
LFPAKHAT2168H
CRITICAL
Q7820
5
4
1 2 3
CRITICAL
B340LBXFSMB
D7820
1
2
3.01K
1/16W1%
402MF-LF
R78101 2
6.3V
2.2UF
603CERM1
20%
C7802 1
2
603CERM1
2.2UF20%
6.3V
C7800 1
2603
10%1uF16VX5R
C7801 1
2
CRITICALQFN
ISL6269U7800
13
5
4
6
3
7
9
11
10
16
15
12
17
14
2
1
815PF
CERM402
5%50V
C7807 1
2
64.9K
MF-LF402
1%1/16W
R78081
2
50V10%
0.0022uF
402CERM
C7808 1
2
MF-LF
05%
1/16W
NO STUFF
402
R78041
2
1/16W5%
402MF-LF
0R78051
2
57.6K
MF-LF402
1%1/16W
R78061
2
0.01UF
CERM402
10%16V
C7806 1
2
22UF
X5R16V
1210
20%
C78311
21210X5R16V
22UF20%
C78301
2
22UF20%
CERM6.3V
805
C7840 1
2
805
6.3VCERM
22UF20%
C78411
2CASE-D2E-LF
330uF20%2.5V-ESR9VPOLY
C78431
2
1000pF
402X7R25V10%
NO STUFFC7822 1
2402
10%1000pF
X7R25V
NO STUFFC78211
2
SMXW78001 2
22UF20%
X5R16V
1210
C78331
216VX5R1210
20%22UFC78321
2
402
NO STUFF
MF-LF1/16W5%0R78021
2
LFPAKHAT2165H
CRITICAL
Q7822
5
4
1 2 3
HAT2165HLFPAK
CRITICAL
Q7821
5
4
1 2 3
51
1uF
CERM402
10%6.3V
C78951
2
10%
CERM402
470pF
50V
C789812
1/16W1%
1M
MF-LF402
R78981 2
LMV2011MFSOT23-5
U7895
3
4
1
5
2
50VCERM
10%
402
470pFC7892
12
1%
1M
1/16WMF-LF402
R78921 2
10KOHM-5%
CRITICAL
0603-LF
R7897
1
2
1%1K
402
1/16WMF-LF
R78961
2
20.0K
MF-LF402
1/16W1%
R78931 2
1/16W
20.0K
402MF-LF
1%
R78911 2
NO STUFF
1/16WMF-LF402
1K
1%
R78941 2
1uF
402CERM6.3V10%
C789012
6491%
MF-LF402
1/16W
R78901
2
SUPERSOT-6FDC796NQ7845
7
4
1
2
3
5
6
22UF6.3V
805CERM
20%
C78471
220%
6.3V
805
22UF
CERM
C7846 1
2
402CERM50V10%0.0022uFC78451
2
5%1/16WMF-LF402
0R78451 2
X5R
0.22uF
402
6.3V20%
C78091
2
05%
1/16WMF-LF
402
R78091
2
402CERM
10%0.0022uF
50V
NO STUFFC7820 1
2
5%
NO STUFF
01/16WMF-LF402
R78201
2
402MF-LF1/16W
5%470K
R78461
2
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
1.8V Supply
051-7099
78 104
D
MIN_NECK_WIDTH=0.25 mm
P1V8S3_UGMIN_LINE_WIDTH=0.6 mm
=PP1V8_S3_REG
P1V8S3_FB
=PP3V3R5V_S3_P1V8ISENS
P1V8ISENS_POS
P1V8S3_IOUT
P1V8ISENS_NEG
P1V8ISENS_NTC
=PP5V_S3_P1V8S3
P1V8S3_ISENP1V8S3_COMP
=PP1V8_S0_FET
GND_P1V8S3_SGND
P1V8ISENS_RC
P1V8S3_COMP_R
PP5V_S3_P1V8S3_VCC
VOLTAGE=5V
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
P1V8S3_FSET
P1V8S3_LGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
P1V8S3_FB_RC
P1V8S3_BOOTMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mmP1V8S3_BOOT_R
MIN_NECK_WIDTH=0.25 mm
P1V8S3_FCCM=P1V8S3_EN
=P1V8S3_PGOOD
=P1V8S0_EN P1V8S0_EN_RC
=PP1V8_S0_P1V8S0
=PPVIN_S3_P1V8S3
=PPBUS_S0_P1V8S0
P1V8S3_PHASE
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
63 51 5
63
63
5
63
5
62
62
62
63
63
63
PGND
PHASE
UG
LG
PVCC
FCCM
EN
PGOOD
COMP
FSET
ISEN
FB
VO
BOOT
VIN
THRMLPAD
VCC
OUT
PGND
PHASE
UG
LG
PVCC
FCCM
EN
PGOOD
COMP
FSET
ISEN
FB
VO
BOOT
VIN
THRMLPAD
VCC
G
D
S
G
D
S
G
D
S
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Vout = 0.6V * (1 + Ra / Rb)
1.05V Current Sense
Vout = 0.6V * (1 + Ra / Rb)
<Rb>
(P1V05S0_FB)
<Ra>
NC
Keep C7990, R7990,Placement Note:
Vout = 1.05V10A max output
1.05V S0 Regulator
3.3V S5 Regulator
(L7920 limit)
3.3V S0 FET
<Ra>
<Rb>
Vout = 3.32V
3.3V S3 FET
4.5A max output
R7994 and R7997close to inductor
(Q7970 & L7970 limit)
603X5R
10%1uF16V
C7951 1
2
QFNISL6269
CRITICAL
U7950
13
5
4
6
3
7
9
11
10
16
15
12
17
14
2
1
850V5%
402CERM
15PFC7957 1
2
CERM402
20%16V
0.01uFC7958 1
2
MF-LF402
1%1/16W
30.9KR79581
2
1/16W5%
MF-LF
0
NO STUFF
402
R79541
2
0
MF-LF402
5%1/16W
R79551
2
57.6K1%
402MF-LF1/16W
R79561
2
16V10%
402CERM
0.01UFC7956 1
2
SO-8
CRITICAL
IRF7832PBFQ7971
5 6 7 8
4
1 2 3
CASE-D2E-LF
2.5V-ESR9V
330uF20%
POLY
C79891
2
20%22UF
X5R16V
1210
C79821
2
MBRS140XXGSMB
CRITICALD7920
1
2
20%
X5R16V
1210
22UFC79301
2
NO STUFF
1/16WMF-LF402
5%0R79021
2
NO STUFF
402
0
MF-LF
5%1/16W
R79521
2
50V
470pF
CERM
10%
402
C799812
1uF
CERM402
10%6.3V
C79951
2
402MF-LF1/16W
1M
1%
R79981 2
LMV2011MFSOT23-5
U7995
3
4
1
5
2
50V
470pF
402CERM
10%
C799212
402MF-LF1/16W
1M
1%
R79921 2
CRITICAL
0603-LF
10KOHM-5%R7997
1
2402
MF-LF1/16W
1K1%
R79961
2
1%1/16W
402MF-LF
20.0KR79931 2
10%6.3VCERM402
1uFC7990
12
MF-LF
1%1/16W
20.0K
402
R79911 2
1%
1K
402MF-LF1/16W
NO STUFFR79941 2
1%1/16W
402MF-LF
649R79901
2
51
0
402
5%1/16WMF-LF
R79491 2
NO STUFF
20%16V
0.01uF
402CERM
C79491
2
402
10%25VCERM
0.0047uFC79201
2
0
1/16WMF-LF402
5%
R792012
402CERM
10%
0.0047uF
25V
C79471 2
SM-LFFDC638PQ7947
1
2
5
6
3
4
402MF-LF1/16W5%
100KR79471 2
0.0022uF
402CERM50V10%
C79451 2
SM-LFFDC638PQ7945
1
2
5
6
3
4
402MF-LF1/16W5%
100KR79451 2
5%0
1/16WMF-LF
402
R79091
2
0.22uF
402X5R6.3V20%
C79091
2
05%
1/16WMF-LF
402
R79591
2
20%6.3VX5R402
0.22uFC79591
2
402CERM
10%0.0022uF
50V
NO STUFFC7970 1
2
402MF-LF1/16W
05%
NO STUFFR79701
2
1210
22UF20%
X5R16V
C7980 1
2
1210
16VX5R
20%22UFC79811
2
3.01K
MF-LF402
1%1/16W
R79101 2
SMC-LFPOLY
20%150uF6.3V
C79421
2
603
2.2UF
CERM1
20%6.3V
C7902 1
2
10%25VX7R402
NO STUFF
1000pFC7921 1
2
SMXW79001 2
2.2UF
CERM1603
20%6.3V
C7900 1
2
10%
X5R
1uF
603
16V
C7901 1
2
ISL6269QFN
CRITICAL
U7900
13
5
4
6
3
7
9
11
10
16
15
12
17
14
2
1
850V
470pF10%
CERM402
C7907 1
2
0.022uF
CERM-X5R
10%16V
402
C7908 1
2
NO STUFF
MF-LF1/16W5%0
402
R79041
2
51.1K
402MF-LF1/16W1%
R79081
2
1/16W5%
402MF-LF
0R79051
2
1/16W
57.6K
MF-LF
1%
402
R79061
2
16V10%
402CERM
0.01UFC7906 1
2
22UF
805
6.3VCERM
20%
C7941 1
2
805
22UF20%6.3VCERM
C79401
2
3.32K
MF-LF402
1%1/16W
R79211
2
MF-LF402
1%1/16W
732R79221
2
FDC796NSUPERSOT-6
CRITICAL
Q7920
7
4
1 2 3 5 6
4.7uH
CRITICAL
IHLP
L7920
1 2
SUPERSOT-6
CRITICAL
FDC796NQ7921
7
4
1 2 3 5 6
2.2UF
CERM1603
20%6.3V
C7952 1
2
20%22UF
CERM6.3V
805
C7986 1
2
805
22UF20%6.3VCERM
C79851
21/16W
1%
402MF-LF
3.32KR79711
2
1/16W1%
MF-LF
4.42K
402
R79721
2
SM
1.53uH
CRITICAL
L7970
1
2
3
CRITICAL
SUPERSOT-6FDC796NQ7970
7
4
1 2 3 5 6
402MF-LF
1%1/16W
2.8KR79601 2
1000pF
402X7R25V10%
NO STUFFC7971 1
2
SMXW79501 2
2.2UF
CERM1603
20%6.3V
C7950 1
2
051-7099
79 104
D
SYNC_DATE=(MASTER)
3.3V / 1.05V Power SuppliesSYNC_MASTER=(MASTER)
=PP1V05_S0_REG
P1V05ISENS_POS
=PP3V3_S3_P3V3S3
P3V3S5_ISEN
P3V3S5_COMP_R
=PP3V3_S3_FET
P3V3S3_EN_L_RC
P3V3S5_LGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
P3V3S5_EN_RC
=P3V3S3_EN_L
=P3V3S5_PGOOD
=P3V3S5_EN
P3V3S5_COMP
P3V3S5_BOOT_RMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
P3V3S5_PHASE
P3V3S5_BOOTMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
=PP3V3_S0_P3V3S0
=PP3V3_S0_FET
P3V3S0_EN_L_RC=P3V3S0_EN_L
P3V3S5_FB
P3V3S5_FB_RC
GND_P3V3S5_SGND
=PP3V3_S5_REG
=PP5V_S5_P3V3S5
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmP1V05S0_BOOT_R
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP1V05S0_UG
P1V05S0_ISEN
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
P1V05S0_BOOT
P1V05S0_COMP_RMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP1V05S0_LG
=PP5V_S0_P1V05S0
P1V05S0_COMP
P1V05S0_FSET
GND_P1V05S0_SGND
=P1V05S0_EN
=P1V05S0_PGOODP1V05S0_FCCM
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
VOLTAGE=5V
PP5V_S0_P1V05S0_VCC
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
VOLTAGE=5V
PP5V_S5_P3V3S5_VCC
P3V3S5_FCCM
P1V05S0_FB_RC
=PP3V3R5V_S0_P1V05ISENS
P1V05ISENS_NEG
P1V05S0_FB
P1V05ISENS_RC
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm
SWITCH_NODE=TRUE
P1V05S0_PHASE
P1V05ISENS_NTC
=PPVIN_S0_P1V05S0
P3V3S5_FSET
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP3V3S5_UG
P1V05S0_IOUT
=PPVIN_S5_P3V3S5
63 51 5
63
63
62
48
62
5
63
63
62
63
63
63
5
5
62
62
63
63
5
63
FB
BIAS
SWSHDN*
NC
VIN BOOST
GND
G
D
S
V-
V+
OUT
THRML
V2V1
RST*
V3
V4
VADJ1
VADJ2
GND PAD
IN
G
D
S
G
D
S
OUT
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
IN
IN
IN
IN
IN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
R8076 serves as pull-down
Other S0 Rails PWRGD CircuitReports when 5V S0, 3.3V S0, 2.5V S0, 1.8V S0, 1.2V S0 and 0.9V S0 are in regulation
1.5V / 1.05V PWRGD Circuit1.5V Enable has pull-up to PBUS
GPU requires 1.2V, 1.8V, 2.5V and3.3V rise after VCore is up.
Unused PGOOD Signals
1.8V Enable has pull-up to PBUS
ISL6269 PGOOD does not
Reports when 1.5V S0 and 1.05V S0 are in regulation
NOTE: R8065 acts as 10K pull-up for PGOOD signalISL6269 undervoltage threshold 81-87% (0.85 - 0.91V)
LTC2908 threshold is 95% (4.75V, 3.135V, 2.375V, 1.71V, 1.14V, 0.86V)
1.5V Comp threshold set to 1.32V (88%)
and 3.3V level-shifter.
LTC2908 sources 6uA at 5.0V
Power Control Signals
Need to ensure that
GPU core voltage.
deassert while GPUPowerPlay is changing
(PM_SLP_S4_L)
(P5VS5_PGOOD)
(PM_SLP_S3_L)
5V Enable has pull-up to PBUS
2.5V S3 and 1.2V S3 supplies are controlledby ethernet power control circuit.
Ensure 1.2V and 2.5V S3 supplies are up
removing ethernet power in battery sleep.before enabling GPU VCore to support
Vout = 1.25V * (1 + Ra / Rb)
NC
<Rb>
<Ra>
Vout = 3.425200mA max output(Switcher limit)
PM_SLP_S3_L
1000
PM_SLP_S4_L
11
00
SMC_PM_G2_ENABLE
11
10Battery Off (G3Hot)
Run (S0)
Sleep (S3)
Soft-Off (S5)
State
Supply needs to guarantee 3.31V delivered to SMC VRef generator
3.425V "G3Hot" Supply
0.89V Reference
LT3470
CRITICAL
TSOT23-8
U8000
7
6
8
4
2
1 5
3
NO STUFF
MF-LF1/16W5%
402
0R80601 2
SOT-3632N7002DW-X-FQ8056
3
5
4
25V10%
1206X5R
10uFC8000 1
2
6.3V20%
805CERM
22UFC80151
2
1/16W1%
402MF-LF
200KR80111
2
10K
MF-LF402
5%1/16W
R80651
2
0.1uF
CERM402
20%10V
C8060 1
2
LMC7211SM-LF
U80604
3
1
5
2
MC74VHC1G08SC70
U8080
3
2
1
4
5
20%0.1UF
10VCERM402
C8080 1
2
57
0.1uF
CERM402
20%10V
C80711
2
CRITICAL
LTC2908LLP
U8070
1
2
9
5 4
7
3
6
8
1/16W
402MF-LF
1%549KR80761
2
4.99K
MF-LF402
1%1/16W
R80631
2
27.4K
MF-LF402
1%1/16W
R80611
2
10K
MF-LF402
1%1/16W
R80641
2
10K
MF-LF402
1%1/16W
R80621
2
0.1uF
CERM402
20%10V
C8070 1
2
MF-LF402
1%1/16W
124KR80721
2
MF-LF402
1%1/16W
100KR80731
2
61
68.1K
MF-LF402
1%1/16W
R80741
2
100K
MF-LF402
1%1/16W
R80751
2
10K
MF-LF402
5%1/16W
R80511
2
10K
MF-LF402
5%1/16W
R80501
2
2N7002DW-X-FSOT-363
Q80576
2
1
2N7002DW-X-FSOT-363
Q80506
2
1
47 26
100K
MF-LF402
5%1/16W
R80541
2
2N7002DW-X-FSOT-363
Q80573
5
4
1/16W1%
402MF-LF
348KR80101
2
1/16W
10K
MF-LF402
5%
R80551
2
2N7002DW-X-FSOT-363
Q80556
2
1
SOT-3632N7002DW-X-FQ8055
3
5
4
CDPH4D19F-SM
33uH
CRITICALL8010
1 2
SOT-3632N7002DW-X-FQ8059
3
5
4
1/16W5%
402MF-LF
470KR80591
2
SOT-3632N7002DW-X-FQ8059
6
2
1
2N7002DW-X-FSOT-363
Q80503
5
4
66
50V5%
402CERM
22pFC8010 1
2
MF-LF
100K
402
5%1/16W
R80561
2
47 41 23
100K
MF-LF402
5%1/16W
R80571
2
47 39 23
100K
MF-LF402
5%1/16W
R80581
2
48
47
6.3V20%
402X5R
0.22uFC8005 1
2
59
59 10K1/16W5%
402MF-LF
R80531
2
1/16W5%
402MF-LF
10KR80521
2
SYNC_DATE=(MASTER)
10480
051-7099 D
SYNC_MASTER=(MASTER)
3.3V G3Hot Supply & Power Control
P3V42G3H5_BOOST=PPVIN_G3H_P3V42G3H
MIN_LINE_WIDTH=0.5 mmP3V42G3H_SW
SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.25 mm
P3V42G3H_FB
=PP3V42_G3H_REG
P1V5S0_RUNSS
=PP5V_S5_PWRCTL
P5VS5_RUNSS
=PP3V42_G3H_PWRCTL
MAKE_BASE=TRUE
PM_SLP_S3_L
PM_SLP_S4_LS5VMAKE_BASE=TRUE
PM_SLP_S4_L
MAKE_BASE=TRUE
=P5VS0_EN_LLIO_P3V3S0_EN_L
=P1V05S0_EN=ENET_VMAIN_AVLBL=MEMVREF_EN=PBUSVSENS_EN
PM_SLP_S3
=GPUVCORE_ENGPUVCORE_ENMAKE_BASE=TRUE
=P3V3S3_EN_L=P5VS3_EN_L
=P1V8S3_EN=RTUSB_ENLIO_P3V3S3_EN
=P3V3S5_EN
SMC_PM_G2_EN_L
SMC_PM_G2_EN
=P1V2S3_PGOOD=P2V5S3_PGOOD
P5VS5_PGOODMAKE_BASE=TRUE
=GPUVCORE_PGOOD
PP1V5_S0
PP0V9_S0PP1V2_S0
PP2V5_S0PP1V8_S0
=PP3V3_S0_ALLSYSPG
P1V5P1V05S0_PGOODMAKE_BASE=TRUE
PP5V_S0
=PP3V3_S5_P1V5PG
ALL_SYS_PWRGD
IMVP_PWRGD_IN
P1V5S0_PGOOD
P1V0_P1V5PG_REF
P1V5S0_COMP_POS
S0PGOOD_0V9_DIV
S0PGOOD_1V2_DIV
=P1V05S0_PGOOD
PM_SLP_S3_LS5VMAKE_BASE=TRUE
=P3V3S0_EN_L
=P1V2S0_EN=P2V5S0_EN
P1V8S0_ENMAKE_BASE=TRUE
=P1V8S0_EN
MAKE_BASE=TRUETP_P5V_P1V5_PGOOD=P5VP1V5_PGOOD
MAKE_BASE=TRUETP_P1V8S3_PGOOD=P1V8S3_PGOOD
P3V3S0_EN_LMAKE_BASE=TRUE
MAKE_BASE=TRUEPM_SLP_S3_LS5V_L
=PP5V_S5_PWRCTL
=PP3V42_G3H_PWRCTL
P2V5S3_P1V2S3_PGOODMAKE_BASE=TRUE
PP3V3_S0
S0PGOOD_PWROK
58
63
58
63
45
45
63
63
63
5
63
5
62
5
62
58
5
61
37
32
51
66
61
58
60
44
5
61
63
63
63
63
63
63
63
63
61
59
59
60
58
60
62
62
63
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
"S3AC" rail is ON in S3 on AC, OFF in S3 on battery
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
Power Aliases
104
051-7099 D
81
VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mmGNDMIN_NECK_WIDTH=0.2 mm
=PP1V8R3V3_S0_GPU_VDDR4=PP3V3_S0_GPU_GPIOS
=PP1V8R3V3_S0_GPU_VDDR5
=PP3V3_S0_GPU_VDDR3=PP3V3_S0_GPUBBN=PP3V3_S0_GPUBBP=PP3V3_S0_GPU
=PP3V3R5V_S0_P1V05ISENS=PPSPD_S0_MEM
=PP3V3_S0_FWISENS=PP3V3R5V_S0_CPUISENS=PP3V3R5V_S0_GPUISENS
=PP3V3_S0_FAN_LT=PP3V3_S0_FAN_RT
=PP3V3_S0_ALLSYSPG
=PP3V3_S0_RSTBUF=PP3V3_S0_SMC_LS
=PP3V3_S0_SMBUS_SMC_B_S0=PP3V3_S0_SMBUS_SMC_BSB
=PP3V3_S0_SMBUS_SMC_0_S0=PP3V3_S0_SMBUS_SB=PP3V3_S0_RSTHMSNS=PP3V3_S0_GPUTHMSNS
=PP3V3_S0_KBDLED=PP3V3_S0_THRM_SNR
=PP3V3_S0_VGASYNC=PP3V3_S0_TPM
=PP3V3_S0_SB_VCC3_3_IDE=PP3V3_S0_SB_VCC3_3_PCI=PP3V3_S0_SB_VCCLAN3_3
=PP3V3_S0_FET
=PP3V3_S3_FET
=PP3V3_S0_SB_VCC3_3=PP3V3_S0_SB_PM=PP3V3_S0_SB_PCI
=PP3V3_S0_SB_3V3_1V5_VCCHDA=PP3V3_S0_SB_GPIO
=PP3V3_S0_SB=PP3V3_S0_NB_VCC_HV=PP3V3_S0_NB
=PP3V3_S0_IMVP6=PP3V3_S0_INVERTER
=PP3V3_S0_IDE=PP3V3_S0_CK410=PP3V3_S0_DDC_LCD=PP3V3_S0_DDC_DVI
=PP3V3R5V_S3_P1V8ISENS=PPVIN_S3_P1V2S3
=PP3V3_S3_MEMVREF=PP3V3_S3_FW
=PP3V3_S3_LTALS
=PP3V3_S3_BT=PP3V3_S3_TOPCASE
=PP3V3_S3_TPM
=PP3V3_S3_RTALS=PP3V3_S3_P3V3S3AC
=PP3V3_S0_LCD=PP3V3_S0_P3V3S0
=PP3V3_S3_P3V3S3=PPVIN_S3_P2V5S3
=PP3V3_S5_ROM=PP3V3_S5_P1V5PG=PP3V3_S5_FWLATEVG
=PP5V_S0_AUDIO_XW=PP5V_S0_ISENSECAL
=PP5V_S0_GPUBBCTL=PP5V_S0_LPCPLUS
=PP5V_S0_KBDLED
=PP5V_S0_FAN_LT=PP5V_S0_FAN_RT
=PP5V_S0_MEMVTT=PP5V_S0_SB
=PP5V_S0_INVERTER=PP5V_S0_IMVP6=PP5V_S0_HDD
=PP5V_S0_FET=PP5V_S0_IDE=PP5V_S0_DVI_DDC
=PP5V_S3_FET
=PP5V_S3_TOPCASE=PP5V_S3_IR
=PP5V_S3_SYSLED=PP5V_S3_CAMERA
=PP5V_S0_P1V05S0=PP5V_S0_GPUVCORE
=PP5V_S3_RTUSB=PP5V_S0_P5VS0
=PP5V_S3_P5VS3=PP5V_S5_PWRCTL
=PP5V_S3_P1V8S3
=PP5V_S5_REG
=PP5V_S5_LIO=PP5V_S5_P5VP1V5_VCC=PP5V_S5_P3V3S5=PP5V_S5_SB
=PPBUS_S5_FW_FET =PPFW_PORT1
=PPBUS_S0_INVERTER=PPBUS_S0_P1V8S0
=PPVIN_S0_P1V05S0=PPVIN_S0_GPUVCORE
=PPVIN_S3_P1V8S3
=PPVIN_S5_P3V3S5=PPBUS_S5_FWPWRSW
=PPBUS_G3H_LIO_CONN =PPBUS_G3H_S3AC=PPVIN_S5_P5VP1V5=PPVIN_S0_IMVP6
=PP3V3_S5_REG
=PP3V42_G3H_REG
=PP3V3_S5_SB_VCCSUS3_3=PP3V3_S5_SB_VCCSUS3_3_USB
=PP3V3_S5_SB_IO
=PP3V3_S5_SB_USB=PP3V3_S5_SB_PM
=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA=PP3V3_S5_SB
=PP3V3_S5_SMC=PP3V3_S5_LPCPLUS
=PP3V42_G3H_LIDSWITCH=PP3V42_G3H_PBUSVSENS=PP3V42_G3H_LIO
=PP3V42_G3H_SMC_PWRGD=PP3V42_G3H_SMC_CLK
=PP3V42_G3H_SMBUS_SMC_BSA=PP3V42_G3H_PWRCTL=PP3V42_G3H_SB_RTC
=PP3V42_G3H_SMCVREF
=PPVOUT_S0_IMVP6_REG =PPVCORE_S0_CPU
=PPVOUT_S0_GPUBBP_LDO =PPBB_S0_GPU
=PNVOUT_S0_GPUBBN_REG =PNBB_S0_GPU
=PP3V3_S3AC_FET =PP3V3_S3_ENET
PP3V3_S0MIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 mmVOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUEVOLTAGE=3.3V
PP3V3_S3MIN_LINE_WIDTH=0.5 MM
MAKE_BASE=TRUEVOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 mmPP3V3_S5MIN_NECK_WIDTH=0.25 mm
PP5V_S0
VOLTAGE=5VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
PP5V_S3
MAKE_BASE=TRUEVOLTAGE=5V
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
PP5V_S5
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.3 mm
MAKE_BASE=TRUEVOLTAGE=33V
PPBUS_S5_FW_FET
PPBUS_G3H
VOLTAGE=12.6VMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
PP3V42_G3H
VOLTAGE=3.425VMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
PPVCORE_S0_CPU
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=1.1V
MIN_NECK_WIDTH=0.25 mmVOLTAGE=1.9V
PPBB_S0_GPU
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE
PNBB_S0_GPU
VOLTAGE=-0.7V
PP3V3_S3AC
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.22 mmVOLTAGE=3.3V
MAKE_BASE=TRUE
PP1V05_S0
VOLTAGE=1.05VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
=PPVCORE_S0_SB=PPVCORE_S0_NB
=PP0V9_S0_MEMVTT_LDO
=PPDCIN_G3H_LIO
PPDCIN_G3H
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=18.5V
=PPVCORE_S0_GPU_REG
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.2VMAKE_BASE=TRUE
PPVCORE_S0_GPU
=PP2V5_S0_FET
VOLTAGE=0
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
PP2V5_S0MIN_NECK_WIDTH=0.25 mm
=PP2V5_S3_REG
MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE
PP2V5_S3
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.6 mm
=PP1V8_S0_FET
=PP1V8_S3_REG
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE
PP1V8_S3
VOLTAGE=1.8V
=PP1V5_S0_REG
=PP1V2_S0_FET
VOLTAGE=1.2VMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
PP1V2_S0
=PP1V2_S3_REG
=PP1V05_S0_REG
MAKE_BASE=TRUE
PP0V9_S0
VOLTAGE=0.9V
MIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.25 mm
=PP1V2_S0_PCIE_GPU_PVDD
=PP1V2_S0_GPU_VDDPLL=PP1V2_S0_PCIE_GPU
=PP1V05_S0_NB_CRT
=PP1V2_S3_ENET=PP1V2_S0_P1V2S0
=PP1V05_S0_SB_CPU_IO
=PPVIN_G3H_P3V42G3H
=PPVCORE_S0_GPU_BBP=PPVCORE_S0_GPU
=PP2V5_S0_GPU_VDDC_CT
=PP2V5_S0_GPU_PVDD=PP2V5_S0_GPU
=PP1V8R2V0_S0_FB_GPU
=PP1V8_S0_MEMVTT=PP1V8_S3_MEMVREF=PP1V8_S3_MEM_NB=PP1V8_S3_MEM
=PP1V5_S0_SB_VCCSATAPLL=PP1V5_S0_SB_VCC1_5_A_USB_CORE=PP1V5_S0_SB_VCC1_5_A_ATX=PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V5_S0_SB=PP1V5_S0_NB_VCCD_HMPLL=PP1V5_S0_NB_VCCAUX
=PP1V5_S0_NB_PLL
=PP1V5_S0_NB_3GPLL=PP1V5_S0_NB_3G=PP1V5_S0_NB=PP1V5_S0_CPU
=PP1V2_S0_PCIE_GPU_VDDR
=PP1V05_S0_NB_VTT
=PP0V9_S0_MEM_TERM
=PP1V05_S0_CPU=PP1V05_S0_FSB_NB
=PP2V5_S0_P2V5S0=PP2V5_S3_ENET
=PP1V8_S0_P1V8S0
=PP1V8_S0_FB_VDDQ=PP1V8_S0_FB_VDD
=PP1V5_S0_SB_VCC1_5_A
=PP1V5_S0_SB_VCCUSBPLL
=PP2V5_S0_GPU_VDD25
=PP2V5_S0_NB_VCCA_3GBG
=PP3V3_S3_PCI
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_SMS
=PP1V5_S0_LIO
=PP1V5_S0_NB_TVDAC
=PP1V5_S0_NB_PCIE
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.22 mmMIN_LINE_WIDTH=0.6 mm
VOLTAGE=1.2V
PP1V2_S3
PP1V5_S0
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
VOLTAGE=0
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUEVOLTAGE=1.8V
PP1V8_S0
11
72
20
26
51
60
61
25
72
19
19
9
34
69
29
25
25
25
25
25
23
25
19
19
34
76
56
51
49
54
43
45
64
25
25
23
25
48
49
45
9
25
19
45
51
58
51
24
67
68
16
29
25
25
25
25
19
17
9
19
8
19
71
71
25
25
19
55
45
19
72
69
72
72
66
66
66
61
28
41
57
66
54
54
62
26
48
27
27
27
27
50
50
53
10
75
56
24
24
24
61
61
24
26
26
24
21
22
17
14
57
74
36
33
74
75
60
59
32
40
5
76
43
48
53
39
74
61
61
59
52
62
42
45
5
66
5
53
5
54
31
25
74
57
76
58
36
75
58
43
76
48
5
61
66
44
58
58
62
60
58
5
58
61
25
41 42
74
60
61
66
60
61
41
5 39
58
57
61
62
24
24
22
22
11
24
23
47
5
43
51
5
48
35
27
62
26
48
57 8
66 67
66 67
39 37
62
62
48
51
5
24
16
31
5
66
5
59
62
59
60
5
5
59
62
59
5
62
65
72
65
19
37
59
21
62
66
51
72
72
73
67
31
32
14
28
24
24
24
24
25
17
16
19
19
19
19
8
65
17
30
7
12
59
37
60
70
70
24
24
72
17
40
27
48
5
19
13
62
62
OUT
IO
IO
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
518S0368
518S0293
Battery Connector (Digital Signals)
NC
NC
Left I/O Power Connector
CRITICAL
SM-2MT-LFJ8250
5
6
1
2
3
4
CRITICAL
M-RT-SM87438J8200
1
2
3
4
5
6
5%1/16WMF-LF402
10R82501
2
051-7099 D
10482
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
PBus-In & Battery Connectors
SMC_BS_ALRT_L=SMBUS_BATT_SDA=SMBUS_BATT_SCLGND_BATT
=PPBUS_G3H_LIO_CONN
27
27
63
5
5
5
5
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PCIE_PVSS
PCIE_VDDR_12
PCIE_PVDD_12
PCIE_VSS
(1.2V)
(1.2V)
PCIE_VSS
(2 OF 7)
PCI EXPRESS POWER & GROUND
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
PCIE_REFCLKP
PCIE_REFCLKN
PERST*
PERST*_MASK
PCIE_TEST
PCIE_RX15N
PCIE_RX14P
PCIE_RX13N
PCIE_RX12N
PCIE_RX12P
PCIE_RX1P
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX2N
PCIE_TX1N
PCIE_TX2P
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8N
PCIE_TX8P
PCIE_TX9P
PCIE_TX10P
PCIE_TX9N
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13N
PCIE_TX13P
PCIE_TX14N
PCIE_TX14P
PCIE_TX15N
PCIE_TX15P
PCIE_CALRP
PCIE_CALRN
PCIE_CALI
PCIE_RX1N
PCIE_RX2N
PCIE_RX2P
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6N
PCIE_RX6P
PCIE_RX7N
PCIE_RX7P
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX13P
PCIE_RX14N
PCIE_RX0N
PCIE_RX0P
PCIE_RX15P
PCI-EXPRESS BUS INTERFACE
(1 OF 7)
OUT
OUT
OUT
OUT
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
2000mA
NC
100mA
X5R 402
0.1uF
16V10%
C8481 1 2
402
0.1uF
X5R16V10%
C8482 1 2
0.1uF
40216V10% X5R
C8479 1 2
402
0.1uF
X5R16V10%
C8480 1 2
402
0.1uF
X5R16V10%
C8477 1 2
402X5R16V10%
0.1uFC8478 1 2
402
0.1uF
X5R16V10%
C8475 1 2
402
0.1uF
X5R16V10%
C8476 1 2
402
0.1uF
X5R16V10%
C8473 1 2
402
0.1uF
X5R16V10%
C8474 1 2
40210% 16V X5R
0.1uFC8420 1 2
402
0.1uF
X5R16V10%
C8471 1 2
402
0.1uF
X5R16V10%
C8472 1 2
402
0.1uF
X5R16V10%
C8469 1 2
402
0.1uF
X5R16V10%
C8470 1 2
402
0.1uF
X5R16V10%
C8467 1 2
10%
0.1uF
16V X5R 402
C8421 1 2
402
0.1uF
X5R16V10%
C8468 1 2
402
0.1uF
X5R16V10%
C8465 1 2
402
0.1uF
X5R16V10%
C8466 1 2
402
0.1uF
X5R16V10%
C8463 1 2
402
0.1uF
X5R16V10%
C8464 1 2
10% 16V X5R
0.1uF
402
C8450 1 2
402
0.1uF
X5R16V10%
C8461 1 2
0.1uF
402X5R16V10%
C8462 1 2
402
0.1uF
X5R16V10%
C8459 1 2
402
0.1uF
X5R16V10%
C8460 1 2
402
0.1uF
X5R16V10%
C8457 1 2
10% 16V X5R 402
0.1uFC8451 1 2
0.1uF
402X5R16V10%
C8458 1 2
MF-LF1/16W
402
1%562R84961
2
1%2.0K
MF-LF402
1/16W
R84951
2
1.47K1%
402MF-LF1/16W
R84971
2
BGAM56P
OMIT
U8400
N23
P23
U23
V23
W23
N25
N26
AM28
AM29
AM30
AM31
N27
N28
N29
AL29
AL30
AL31
AL32
AM27
N24
N30
R25
R26
R29
R31
T24
T26
T27
T29
U24
U26
P24
U28
U29
U30
V24
V25
V26
V29
V31
W24
W26
P25
W27
W29
Y24
Y26
Y28
Y29
Y30
AA23
AA25
AA26
P26
AA29
AA31
AB23
AB26
AB27
AB29
AC23
AC24
AC26
AC28
P28
AC29
AC30
AD25
AD26
AD29
AD31
AE26
AE27
AE29
AF26
P29
AF28
AF29
AF30
AG25
AG26
AG29
AG31
AH24
AH26
AH27
P30
AH29
AJ26
AJ28
AJ29
AJ30
AJ32
AK26
AK29
AK30
AK31
R23
AK32
AL27
R24
CERM
1uF6.3V
402
10%
C8402 1
2
10% 16V X5R
0.1uF
402
C8448 1 2
402CERM
10%6.3V
1uFC8401 1
2
10%6.3VCERM402
1uFC8407 1
2
10% 16V X5R
0.1uF
402
C8449 1 2
10%6.3VCERM402
1uFC8413 1
2
1uF
402CERM6.3V10%
C8406 1
2
1uF
402CERM6.3V10%
C8411 1
210%
6.3VCERM402
1uFC8412 1
2
20%
CERM805
6.3V
22UFC84001
2
22UF6.3V
805CERM
20%
C84101
210% 16V X5R
0.1uF
402
C8446 1 2
22UF6.3V
805CERM
20%
C84051
2
200-OHM-EMI0402
L8400
1
2
10% 16V X5R
0.1uF
402
C8447 1 2
10% 16V X5R
0.1uF
402
C8444 1 2
10% 16V X5R
0.1uF
402
C8445 1 2
10% 16V X5R
0.1uF
402
C8442 1 2
10% 16V X5R
0.1uF
402
C8443 1 2
10% 16V X5R
0.1uF
402
C8440 1 2
10% 16V X5R
0.1uF
402
C8441 1 2
10% 16V X5R
0.1uF
402
C8438 1 2
10% 16V X5R 402
0.1uFC8439 1 2
10% 16V X5R
0.1uF
402
C8436 1 2
10% 16V X5R
0.1uF
402
C8437 1 2
10% 16V X5R
0.1uF
402
C8434 1 2
10% 16V X5R
0.1uF
402
C8435 1 2
10% 16V X5R
0.1uF
402
C8432 1 2
10% 16V X5R
0.1uF
402
C8433 1 2
10% 16V X5R
0.1uF
402
C8430 1 2
10% 16V X5R 402
0.1uFC8431 1 2
10% 16V X5R
0.1uF
402
C8428 1 2
10% 16V X5R
0.1uF
402
C8429 1 2
10% 16V X5R
0.1uF
402
C8426 1 2
10% 16V X5R
0.1uF
402
C8427 1 2
16V X5R
0.1uF
40210%
C8424 1 2
10% 16V X5R
0.1uF
402
C8425 1 2
0.1uF
10% X5R 40216V
C8422 1 2
10% 16V X5R
0.1uF
402
C8423 1 2
10% 16V X5R
0.1uF
402
C8455 1 2
10% 16V X5R
0.1uF
402
C8456 1 2
M56PBGA
OMIT
U8400
AB24
AE24
AD24
AK28
AL28
AH31
AJ31
V30
W30
U32
V32
T31
U31
R30
T30
P32
R32
N31
P31
AG30
AH30
AF32
AG32
AE31
AF31
AD30
AE30
AC32
AD32
AB31
AC31
AA30
AB30
Y32
AA32
W31
Y31
AA24
AJ27
AK27
W25
Y25
V28
W28
U27
V27
T25
U25
R28
T28
P27
R27
AH25
AJ25
AG28
AH28
AF27
AG27
AE25
AF25
AD28
AE28
AC27
AD27
AB25
AC25
AA28
AB28
Y27
AA27
AG24
AF24
402
0.1uF
X5R16V10%
C8485 1 2
402
0.1uF
X5R16V10%
C8486 1 2
402
0.1uF
X5R16V10%
C8483 1 2
402
0.1uF
X5R16V10%
C8484 1 2
051-7099
SYNC_DATE=(MASTER)
D
10484
ATI M56 PCI-ESYNC_MASTER=(MASTER)
=PP1V2_S0_PCIE_GPU_PVDD
PP1V2_S0_PCIE_GPU_PVDD_F
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
PEG_D2R_N<1>
PEG_D2R_N<12>
PEG_R2D_P<5>
PEG_R2D_C_P<9>
=PP1V2_S0_PCIE_GPU_VDDR
PEG_D2R_C_N<2>
PEG_R2D_N<4>
PEG_R2D_C_P<5>
PEG_R2D_C_N<13>
PEG_R2D_C_P<14>
PEG_R2D_C_N<14>
GPU_PCIE_CALRP
GPU_PCIE_CALI
PEG_R2D_N<0>
PEG_R2D_N<1>
PEG_R2D_N<2>
PEG_R2D_N<3>
PEG_R2D_N<6>
PEG_R2D_N<5>
PEG_R2D_N<9>
PEG_R2D_N<8>
PEG_R2D_N<7>
PEG_R2D_N<11>
PEG_R2D_N<10>
PEG_R2D_N<12>
PEG_R2D_N<13>
PEG_R2D_N<14>
PEG_R2D_N<15>
PEG_R2D_P<0>
PEG_R2D_P<1>
PEG_R2D_P<2>
PEG_R2D_P<3>
PEG_R2D_P<4>
PEG_R2D_P<6>
PEG_R2D_P<7>
PEG_R2D_P<8>
PEG_R2D_P<9>
PEG_R2D_P<10>
PEG_R2D_P<11>
PEG_R2D_P<12>
PEG_R2D_P<13>
PEG_R2D_P<14>
PEG_R2D_P<15>
PEG_R2D_C_N<0>
PEG_R2D_C_P<0>
PEG_R2D_C_N<1>
PEG_R2D_C_P<1>
PEG_R2D_C_P<2>
PEG_R2D_C_N<2>
PEG_R2D_C_P<3>
PEG_R2D_C_N<3>
PEG_R2D_C_P<4>
PEG_R2D_C_N<4>
PEG_R2D_C_P<6>
PEG_R2D_C_N<5>
PEG_R2D_C_N<6>
PEG_R2D_C_P<7>
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_P<8>
PEG_R2D_C_N<9>
PEG_R2D_C_P<10>
PEG_R2D_C_N<10>
PEG_R2D_C_P<11>
PEG_R2D_C_N<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<13>
PEG_R2D_C_N<12>
PEG_R2D_C_P<15>
PEG_CLK100M_GPU_P
PEG_RESET_L
PEG_CLK100M_GPU_N
PEG_R2D_C_N<15>
GPU_PCIE_CALRN
PEG_D2R_C_N<0>
PEG_D2R_C_N<1>
PEG_D2R_C_N<3>
PEG_D2R_C_N<4>
PEG_D2R_C_N<5>
PEG_D2R_C_N<6>
PEG_D2R_C_N<7>
PEG_D2R_C_N<8>
PEG_D2R_C_N<9>
PEG_D2R_C_N<10>
PEG_D2R_C_N<11>
PEG_D2R_C_N<12>
PEG_D2R_C_N<13>
PEG_D2R_C_N<14>
PEG_D2R_C_N<15>
PEG_D2R_P<0>
PEG_D2R_N<0>
PEG_D2R_P<1>
PEG_D2R_N<2>
PEG_D2R_P<2>
PEG_D2R_N<3>
PEG_D2R_P<3>
PEG_D2R_N<4>
PEG_D2R_P<4>
PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_N<5>
PEG_D2R_N<6>
PEG_D2R_P<7>
PEG_D2R_N<7>
PEG_D2R_P<8>
PEG_D2R_N<8>
PEG_D2R_N<9>
PEG_D2R_P<9>
PEG_D2R_N<10>
PEG_D2R_P<10>
PEG_D2R_N<11>
PEG_D2R_P<11>
PEG_D2R_P<12>
PEG_D2R_P<13>
PEG_D2R_P<14>
PEG_D2R_N<13>
PEG_D2R_P<15>
PEG_D2R_N<14>
PEG_D2R_N<15>
PEG_D2R_C_P<0>
PEG_D2R_C_P<1>
PEG_D2R_C_P<2>
PEG_D2R_C_P<3>
PEG_D2R_C_P<4>
PEG_D2R_C_P<5>
PEG_D2R_C_P<6>
PEG_D2R_C_P<7>
PEG_D2R_C_P<8>
PEG_D2R_C_P<9>
PEG_D2R_C_P<10>
PEG_D2R_C_P<11>
PEG_D2R_C_P<12>
PEG_D2R_C_P<13>
PEG_D2R_C_P<14>
PEG_D2R_C_P<15>
=PP1V2_S0_PCIE_GPU
63
13
13
13
63
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
34
26
34
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
63
PGND
PHASE
UG
LG
PVCC
FCCM
EN
PGOOD
COMP
FSET
ISEN
FB
VO
BOOT
VIN
THRMLPAD
VCC
PG
EN
VIN
ADJ
VOUT
GND
G
D
S
OUT
G
D
S
G
D
S
G
D
S
CAP-
FB
OUT
SHDN_L
CAP+
LIN/SKIP_L
IN
GND
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
<Rc>
<Rb>
Back-Bias Positive SupplyBack-bias positive supply provides VDDC + 0.5V when active.
Vout(high) = 0.6V * (1 + Ra / Req)Req = Rb || Rc
Vout(high) = 0.59V * (1 + Ra/Req)
pull-up must be powered before VCore
NOTE: BBP tracks VDDC based on GPU voltage GPIO.
Pull-up voltage must be high enough to
SI3446DV max Vgs is 1.6VVin must be > 2.8V
For proper M56 power sequence, this
When inactive, provides VDDC to BBP pins.
<Rb>
<Ra>
satisfy BBP FET Vgs (where Vs = 1.2V)
NC
<Ra>
Vout = -Vin * Rb / Ra
(Regulator limit)125mA max output
close to inductor
GPU VCore Supply
Placement Note:
Vout(low) = 0.6V * (1 + Ra / Rb)
<Ra>
R8594 and R8597Keep C8590, R8590,
(GPUVCORE_FB)
<Rc>
Vout(low) = 0.59V * (1 + Ra/Rb)
Req = Rb || Rc
Vout = (1.58V /) 1.50V180mA max output(LDO limit)
When inactive, provides VSS to BBN pins.
Back-Bias Negative Supply
Rb = -Vout / 50 uARa = Vin / 50 uARecommended values:<Rb>
Vout = 1.10V / 0.95V17A max output(Q8520 limit)
Vout = -0.55V
Back-bias negative supply provides VSS - 0.55V when active.
GPU VCore Current Sense
330uF
POLYCASE-D2E-LF
20%2.5V-ESR9V
C8542 1
2
3.01K1/16WMF-LF
1%
402
R85211
2
1/16WMF-LF
5.11K1%
402
R85221
2
1210X5R
20%16V
22UFC85321
2
CRITICAL
1.0uH-20.5
SM1
L8520
1
2
3
LFPAKHAT2168H
CRITICAL
Q8520
5
4
1 2 3
SMBB340LBXF
CRITICALD8520
1
2HAT2165HLFPAK
CRITICAL
Q8522
5
4
1 2 3
1/16W1%
3.01K
402MF-LF
R85101 2
CERM1
2.2UF6.3V20%
603
C8502 1
2
6.3VCERM1
20%
603
2.2UFC8500 1
2603
16V10%
X5R
1uFC8501 1
2
QFNISL6269
CRITICAL
U8500
13
5
4
6
3
7
9
11
10
16
15
12
17
14
2
1
8
CERM402
50V
15pF5%
C8507 1
2MF-LF402
1%1/16W
150KR85081
2
10%
402
50VCERM
470pFC8508 1
2
1/16W
0
MF-LF
5%
402
R85041
2
NO STUFF
MF-LF402
5%1/16W
0R85051
2
1/16W1%
402MF-LF
57.6KR85061
2
16V10%
402CERM
0.01UFC8506 1
2
X5R
22UF
1210
20%16V
C85311
220%22UF16VX5R1210
C85301
2
6.3V20%
CERM805
22UFC8540 1
2
22UF
CERM
20%6.3V
805
C85411
2
LFPAKHAT2165H
CRITICAL
Q8521
5
4
1 2 3
SMXW85001 2
NO STUFF
10%
402X7R
1000pF25V
C8522 1
2
NO STUFF
1000pF
X7R
10%25V
402
C85211
2
22UF
CERM805
20%6.3V
C8556 1
2
22UF20%
CERM6.3V
805
C85571
2
1/16WMF-LF402
1%24.9KR85551
2
16.2K1/16W1%
402MF-LF
R85561
2
16V10%
402CERM
0.01UFC8555 1
2
FAN2558SOT23-6-LF
CRITICAL
U8550
53
2
4
1 6
CERM1603
2.2uF6.3V20%
C8551 1
2
330uF20%2.5V-ESR9V
CASE-D2E-LFPOLY
C85431
2
12.4K
402
1%
MF-LF1/16W
R85231 2
NO STUFF
1/16W5%
MF-LF
0
402
R85021
2
1/16W5%
402MF-LF
10KR85601
2
2N7002SOT23-LF
Q85703
1
2
100K
MF-LF
5%1/16W
402
R85701
2
50V
0.0022uF10%
402CERM
C85701
2
GPU_BB_CTL
0
MF-LF402
5%1/16W
R85611 2
50V
470pF
402CERM
10%
C859812
51
402
50V
470pF
CERM
10%
C859212
402MF-LF
1M
1%1/16W
R85981 2
LMV2011MFSOT23-5
U8595
3
4
1
5
2
402
1M
1%
MF-LF1/16W
R85921 2
1uF
CERM402
10%6.3V
C85951
2
20.0K
MF-LF402
1/16W1%
R85931 2
20.0K
1%
MF-LF402
1/16W
R85911 2
1/16WMF-LF
402
1%649
R85901
2
1%
1K
402MF-LF1/16W
NO STUFFR85941 2
CERM
10%
402
1uF
6.3V
C859012
10KOHM-5%
CRITICAL
0603-LF
R8597
1
2402
MF-LF1/16W
1K1%
R85961
2
NO STUFF
1%1/16W
174K
402MF-LF
R85541
2
CERM-X5R
0.022uF16V10%
402
C8523 1
2
5%1/16WMF-LF
402
10KR85241
2
10K
402MF-LF
5%1/16W
R85251 2
0.0022uF
NO STUFF
10%50V
CERM402
C8520 1
2
10K
MF-LF1/16W
5%
402
R85261
2
2N7002DW-X-FSOT-363
Q85233
5
4
2N7002DW-X-FSOT-363
Q85236
2
1
NO STUFF
2N7002SOT23-LF
Q85543
1
2
68.1K
402
1/16WMF-LF
1%
R85871
2
11.3K1%
402
1/16WMF-LF
R85881
2
2.2uF
603CERM16.3V20%
C85811
2
6.3VX5R
10uF20%
603
C8580 1
2
805
22UF
CERM
20%6.3V
C85891
2
CRITICALSOI
MAX1673U8580
3
2
6
7
8
1
5
4
SI3446DVTSOP-LF
Q85751
2
5
63
4
1/16W5%
402MF-LF
0
NO STUFFR85201
2
0.22UF
402X5R6.3V20%
C85091
2402
MF-LF1/16W
05%
R85091
2
051-7099
SYNC_MASTER=(MASTER)
104
D
85
GPU (M56) Core SuppliesSYNC_DATE=(MASTER)
=PPVCORE_S0_GPU_REG
GPUBBN_FB
GPUVCORE_FB
=PP3V3_S0_GPU
=PNVOUT_S0_GPUBBN_REG
GPUVCORE_PHASE
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
=PPVIN_S0_GPUVCORE=PP5V_S0_GPUVCORE
GPUISENS_NTC
GPUVCORE_FB_LOW
GPUVCORE_FB_RC
GPUISENS_POS
GPUISENS_NEG
GPUISENS_RC
GPUVCORE_BOOT_RMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmGPUVCORE_BOOT
PP5V_S0_GPUVCORE_VCC
VOLTAGE=5V
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
GPUBB_EN
GPUBBN_CAPPMIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.25 mm
GPUBBN_CAPNMIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.25 mm
=PP3V3_S0_GPUBBN
GPU_VCORE_HIGH_RC
GPU_VCORE_LOW
GPU_VCORE_HIGH
GPUVCORE_ISEN
MIN_LINE_WIDTH=0.6 mmGPUVCORE_UG
MIN_NECK_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
GPUVCORE_LGMIN_LINE_WIDTH=0.6 mm
GPUVCORE_IOUT
=PP3V3R5V_S0_GPUISENS
=GPUVCORE_PGOOD
=GPUVCORE_ENGPUVCORE_FCCM
GPUVCORE_COMP
GPUVCORE_FSET
GPUVCORE_COMP_R
GPUBBP_ADJ_LOW
=PP3V3_S0_GPUBBP
GPUBB_EN
GPU_VCORE_HIGH
=PP5V_S0_GPUBBCTL
GPU_GENERICDGPUBB_EN
=PPVOUT_S0_GPUBBP_LDO
GPUBB_EN_L
=PPVCORE_S0_GPU_BBP
GPUBB_EN_L
GPUBBP_ADJ
GND_GPUVCORE_SGND
72 69
63
63
63
63
63
66
63
69
66
63
62
62
5
5
63
66
66
63
72
66
63
66
63
66
5
MEMORY & CORE POWER / GROUND
(1.0V/1.2V)
(1.0V/1.2V)
(7 OF 7)
VDDR1
VSS
VSS
(1.8V/2.0V) VSS
VDDC
BBP BBN
VDDCI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(NONE)
(NONE)
- =PP1VR1V3_GPU_VCORE
BOM options provided by this page:
Signal aliases required by this page:
Page NotesPower aliases required by this page:- =PP1V5_GPU_VDD15
14.2A @ 445/452MHz Core/Mem Clk for VDDC+VDDCI
2.0A @ 500MHz 1.8V GDDR3
100mA (Preliminary)
100mA (Preliminary)
OMIT
BGAM56PU8400
K15
R10
Y23
AC17
K18
M23
V10
AC14
P14
P18
U15
U16
U17
V14
V15
V16
V18
W14
W15
W19
P19
AC11
AC12
AD11
R15
R17
R18
R19
T16
T17
T18
K14
P16
T14
T23
U19
W10
W17
A3
A9
F32
H13
H19
J1
J10
J11
J13
J18
J19
J20
A12
J32
K11
K13
K19
K20
K21
K24
L23
L24
L32
A15
M1
M10
N9
N10
P8
P9
P10
R1
R9
V1
A18
Y8
Y9
Y10
AA1
A21
A24
A30
C1
C32
K23
A2
B1
R3
R6
R14
R16
T10
T15
T19
U1
U5
U6
B32
U7
U8
U9
U10
U14
U18
V3
V6
V17
V19
C4
W16
W18
Y1
Y5
Y6
Y7
AA4
AA6
AC9
AC10
C5 AD6
AD7
AD8
AD9
AD10
AD13
AD14
AD15
AD16
AD17
C6
AE8
AE14
AE15
AE16
AE17
AF14
AF16
AG11
AG16
AG23
C9
AH10
AH11
AH16
AJ10
AK16
AL1
AL13
AM2
AM13
C10
C15
C18
C20
A8
C21
C24
C27
D11
D30
E5
E8
E9
E12
E13
A11
E16
E19
E25
E28
E30
E32
F3
F6
F10
F13
A13
F15
F16
F18
F19
F21
F22
F24
F27
F30
G13
A16
G16
G19
G20
G21
G22
G25
H1
H5
H7
H16
A19
H20
H21
H28
H32
J3
J6
J9
J12
J16
J21
A22
J24
J28
J30
K10
K12
K16
K17
K27
K30
L1
A25
L6
L7
L29
M3
M6
M7
M8
M9
M24
M28
A31
M32
N3
N7
N8
P1
P5
P6
P7
P15
P17
0.1uF
402X5R16V10%
C8697 1
210%
402
1uF
CERM6.3V
C8696 1
2
10%
402
1uF
CERM6.3V
C86911
2
0.1uF
402X5R16V10%
C86921
2
CERM6.3V
1uF
402
10%
C86101
26.3VCERM
1uF
402
10%
C86091
26.3VCERM
1uF
402
10%
C86081
26.3VCERM
1uF
402
10%
C86071
26.3VCERM
1uF
402
10%
C86061
26.3VCERM
1uF
402
10%
C86051
2402
6.3VCERM
1uF10%
C86041
2
10%
402
1uF
CERM6.3V
C86161
210%
402
1uF
CERM6.3V
C86151
210%
402
1uF
CERM6.3V
C86141
210%
402
1uF
CERM6.3V
C86131
210%
402
1uF
CERM6.3V
C86121
2
1/10W
603
05%
MF-LF
R86301
2
6.3VCERM
1uF
402
10%
C86341
26.3VCERM
1uF
402
10%
C86331
26.3VCERM
1uF
402
10%
C86321
26.3VCERM
1uF
402
10%
C86311
2
6.3VCERM
1uF
402
10%
C86601
2
10%
402
1uF
CERM6.3V
C86661
2
6.3VCERM
1uF
402
10%
C86591
26.3VCERM
1uF
402
10%
C86581
26.3VCERM
1uF
402
10%
C86571
2
10%
402
1uF
CERM6.3V
C86651
210%
402
1uF
CERM6.3V
C86641
210%
402
1uF
CERM6.3V
C86631
2
6.3VCERM
1uF
402
10%
C86561
2
10%
402
1uF
CERM6.3V
C86621
2
6.3VCERM
1uF
402
10%
C86551
2
10%
402
1uF
CERM6.3V
C86611
2
6.3VCERM
1uF
402
10%
C86721
2
10%
402
1uF
CERM6.3V
C86781
2
6.3VCERM
1uF
402
10%
C86711
26.3VCERM
1uF
402
10%
C86701
26.3VCERM
1uF
402
10%
C86691
2
10%
402
1uF
CERM6.3V
C86771
210%
402
1uF
CERM6.3V
C86761
210%
402
1uF
CERM6.3V
C86751
2
6.3VCERM
1uF
402
10%
C86681
2
10%
402
1uF
CERM6.3V
C86741
2
CERM6.3V
1uF
402
10%
C86671
2
10%
402
1uF
CERM6.3V
C86731
2
6.3VCERM
22UF
805
20%
C8653 1
220%
6.3VCERM805
22UFC8652 1
2CERM6.3V
22UF
805
20%
C8651 1
2
22UF
805CERM6.3V20%
C8650 1
2
10%
402
1uF
CERM6.3V
C86831
210%
402
1uF
CERM6.3V
C86821
210%
402
1uF
CERM6.3V
C86811
210%
402
1uF
CERM6.3V
C86801
26.3VCERM
1uF
402
10%
C86791
2
22UF
805CERM6.3V20%
C8601 1
2
6.3VCERM
1uF
402
10%
C86111
2
20%6.3VCERM805
22UFC8690 1
2
20%6.3VCERM805
22UFC86951
2
20%6.3VCERM805
22UFC8630 1
2
20%6.3VCERM805
22UFC8600 1
2
ATI M56 Core PowerSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
D051-7099
10486
=PPVCORE_S0_GPU
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mm
PPVCORE_S0_GPU_VDDCIVOLTAGE=1.2V
=PPBB_S0_GPU
=PP1V8R2V0_S0_FB_GPU
=PNBB_S0_GPU
72 63
68
51
63
63
63
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IN
IN
IN
IN
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DQA_58
DQA_59
WEA1*
DQA_61
DQA_62
MVREFD_0
MVREFS_0
VDDRH0
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15
DQMA_0*
DQMA_1*
DQMA_2*
DQMA_3*
DQMA_4*
DQMA_5*
DQMA_6*
DQMA_7*
QSA_1
QSA_2
QSA_0
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
QSA_0*
QSA_1*
QSA_2*
QSA_3*
QSA_4*
QSA_5*
QSA_6*
QSA_7*
CLKA0
CLKA0*
CSA0_0*
CKEA0
RASA0*
CASA0*
WEA0*
ODTA0
CLKA1*
CSA1_0*
CKEA1
RASA1*
CASA1*
ODTA1
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_45
DQA_44
DQA_46
DQA_47
DQA_48
DQA_50
DQA_51
DQA_49
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_60
DQA_63
VSSRH0
CLKA1
CSA0_1*
CSA1_1*
WRITE STROBE
READ STROBE
MEMORY INTERFACE A
(3 OF 7)
2.0V)(1.8V/
DQB_62
VDDRH1
MVREFS_1
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_15
MAB_14
MAB_13
DQMB_0*
DQMB_1*
DQMB_2*
DQMB_3*
DQMB_4*
DQMB_5*
DQMB_6*
DQMB_7*
QSB_0
QSB_1
QSB_2
QSB_4
QSB_3
QSB_5
QSB_6
QSB_7
QSB_0*
QSB_1*
QSB_2*
QSB_3*
QSB_4*
QSB_5*
QSB_6*
QSB_7*
CLKB0*
CLKB0
CSB0_0*
CKEB0
RASB0*
WEB0*
CASB0*
ODTB0
CLKB1
CLKB1*
CKEB1
RASB1*
WEB1*
CASB1*
ODTB1
DRAM_RST
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_15
DQB_14
DQB_13
DQB_16
DQB_17
DQB_18
DQB_20
DQB_19
DQB_22
DQB_21
DQB_23
DQB_25
DQB_24
DQB_27
DQB_26
DQB_28
DQB_30
DQB_29
DQB_33
DQB_31
DQB_32
DQB_35
DQB_34
DQB_37
DQB_36
DQB_38
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_48
DQB_47
DQB_52
DQB_53
DQB_56
DQB_55
DQB_54
DQB_58
DQB_57
DQB_60
DQB_59
DQB_61
DQB_63
MVREFD_1
VSSRH1
TEST_MCLK
TEST_YCLK
MEMTEST
DQB_39
CSB1_0*
DQB_51
DQB_50
DQB_49
CSB0_1*
CSB1_1*
WRITE STROBE
READ STROBE
MEMORY INTERFACE B
(4 OF 7)
(1.8V/ 2.0V)
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
- =PP1V8R2V0_S0_FB_GPU
BOM options provided by this page:
Signal aliases required by this page:
Power aliases required by this page:
(NONE)
(NONE)
NC
NC NC
NC
Page Notes
1%1/16WMF-LF402
40.2R87221
2
1%1/16WMF-LF
402
40.2R87201
2
0.1uF
402X5R16V10%
C87231
2
100
402MF-LF1/16W1%
R87231
2
1/16W
100
402MF-LF
1%
R87211
2
16V
0.1uF
402X5R
10%
C8721 1
210%16VX5R402
0.1uFC87131
2
1%1/16WMF-LF402
40.2R87121
2
100
402MF-LF
1%1/16W
R87131
2402X5R16V10%
0.1uFC8711 1
2
1%1/16WMF-LF
402
40.2R87101
2
100
402MF-LF1/16W
1%
R87111
2
402
2431%1/16WMF-LF
R87321
2
MF-LF1/16W
5%4.7K
402
R87311
2
4.7K
402
5%1/16WMF-LF
R87301
2
5%1/16WMF-LF402
4.7KR87331
2
M56PBGA
OMIT
U8400
C29
B22
B30
C22
D31
E31
B20
C19
B29
C28
B23
C23
M31
M30
L28
L27
J27
H29
G29
G27
M26
L26
M25
L25
L31
J25
G28
H27
H26
F26
G26
H25
H24
H23
H22
L30
J23
J22
E23
D22
D23
E22
E20
F20
D19
D18
H30
B19
B18
C17
B17
C14
B14
C13
B13
D17
E18
G31
E17
F17
E15
E14
F14
D13
H18
H17
G18
G17
G30
G15
G14
H14
J14
F31
M27
M29
H31
J29
J26
G23
E21
B15
D14
J17
D26
F28
D29
B27
E27
E29
B25
C25
D28
D25
E24
E26
D27
F25
C26
B26
C31
C30
F29
D24
J31
K31
K29
K28
K25
K26
F23
G24
D20
D21
B16
C16
D16
D15
H15
J15
B28
B24
A27
A28
B31
B21
M56PBGA
OMIT
U8400
D3
L2
C2
L3
B4
B5
N2
P3
D2
E3
K2
K3
B12
C12
E11
F11
F9
D8
D7
F7
G12
G11
H12
H11
B11
H9
E7
F8
G8
G6
G7
H8
J8
K8
L8
C11
K9
L9
K5
L4
K4
L5
N5
N6
P4
R4
C8
P2
R2
T3
T2
W3
W2
Y3
Y2
T4
R5
B7
T5
T6
V5
W5
W6
Y4
R8
T8
R7
T7
C7
V7
W7
W8
W9
B6
F12
D12
B8
D9
G9
K7
M5
V2
W4
T9
AA3
G4
E6
D4
F2
F5
D5
H2
H3
E4
H4
J5
G5
F4
H6
G3
G2
AA7
B3
C3
D6
J4
B9
B10
D10
E10
H10
G10
K6
J7
N4
M4
U2
U3
U4
V4
V8
V9
E2
J2
AA5
AA2
F1
E1
B2
M2
6.3V
402
10%
CERM
1uFC8716 1
210%
402CERM6.3V
1uFC8715 1
210%
402
1uF
CERM6.3V
C8726 1
26.3VCERM
1uF
402
10%
C8725 1
2
FERR-220-OHM
0402
L8725
1 2
FERR-220-OHM
0402
L8715
1 2
SMXW87251 2
SMXW87151 2
SYNC_MASTER=(MASTER)
ATI M56 Frame Buffer I/FSYNC_DATE=(MASTER)
D051-7099
10487
=PP1V8R2V0_S0_FB_GPU VOLTAGE=1.8VPP1V8R2V0_S0_GPU_VDDRH0
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm =PP1V8R2V0_S0_FB_GPU MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mmVOLTAGE=1.8V
PP1V8R2V0_S0_GPU_VDDRH1
FB_B_DQ<17>FB_B_DQ<18>
FB_A_CLK_P<0>
FB_A_CS_L<0>
FB_A_BA<2>
GND_GPU_VSSRH1MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=0V
=PP1V8R2V0_S0_FB_GPU=PP1V8R2V0_S0_FB_GPU
FB_A_CLK_N<0>
FB_A_BA<0>
FB_B_MA<11>FB_B_MA<10>
FB_A_MA<4>FB_A_MA<3>
FB_A_DQ<0>
FB_B_DQ<62>
GPU_MVREFS1
FB_B_MA<0>FB_B_MA<1>FB_B_MA<2>FB_B_MA<3>FB_B_MA<4>FB_B_MA<5>FB_B_MA<6>FB_B_MA<7>FB_B_MA<8>FB_B_MA<9>
TP_FB_B_MA12
FB_B_BA<1>FB_B_BA<0>FB_B_BA<2>
FB_B_DQM_L<0>FB_B_DQM_L<1>FB_B_DQM_L<2>FB_B_DQM_L<3>FB_B_DQM_L<4>FB_B_DQM_L<5>FB_B_DQM_L<6>FB_B_DQM_L<7>
FB_B_RDQS<0>FB_B_RDQS<1>FB_B_RDQS<2>
FB_B_RDQS<4>FB_B_RDQS<3>
FB_B_RDQS<5>FB_B_RDQS<6>FB_B_RDQS<7>
FB_B_WDQS<0>FB_B_WDQS<1>FB_B_WDQS<2>FB_B_WDQS<3>FB_B_WDQS<4>FB_B_WDQS<5>FB_B_WDQS<6>FB_B_WDQS<7>
FB_B_CLK_N<0>FB_B_CLK_P<0>
FB_B_CS_L<0>
FB_B_CKE<0>
FB_B_RAS_L<0>
FB_B_WE_L<0>
FB_B_CAS_L<0>
TP_FB_B_ODT<0>
FB_B_CLK_P<1>FB_B_CLK_N<1>
FB_B_CKE<1>
FB_B_RAS_L<1>
FB_B_WE_L<1>
FB_B_CAS_L<1>
TP_FB_B_ODT<1>
FB_DRAM_RST
FB_B_DQ<0>FB_B_DQ<1>FB_B_DQ<2>FB_B_DQ<3>FB_B_DQ<4>FB_B_DQ<5>FB_B_DQ<6>FB_B_DQ<7>FB_B_DQ<8>FB_B_DQ<9>FB_B_DQ<10>FB_B_DQ<11>FB_B_DQ<12>
FB_B_DQ<15>FB_B_DQ<14>FB_B_DQ<13>
FB_B_DQ<16>
FB_B_DQ<20>FB_B_DQ<19>
FB_B_DQ<22>FB_B_DQ<21>
FB_B_DQ<23>
FB_B_DQ<25>FB_B_DQ<24>
FB_B_DQ<27>FB_B_DQ<26>
FB_B_DQ<28>
FB_B_DQ<30>FB_B_DQ<29>
FB_B_DQ<33>
FB_B_DQ<31>FB_B_DQ<32>
FB_B_DQ<35>FB_B_DQ<34>
FB_B_DQ<37>FB_B_DQ<36>
FB_B_DQ<38>
FB_B_DQ<40>FB_B_DQ<41>FB_B_DQ<42>FB_B_DQ<43>FB_B_DQ<44>FB_B_DQ<45>FB_B_DQ<46>
FB_B_DQ<48>FB_B_DQ<47>
FB_B_DQ<52>FB_B_DQ<53>
FB_B_DQ<56>FB_B_DQ<55>FB_B_DQ<54>
FB_B_DQ<58>FB_B_DQ<57>
FB_B_DQ<60>FB_B_DQ<59>
FB_B_DQ<61>
FB_B_DQ<63>
GPU_MVREFD1
GPU_TEST_MCLKGPU_TEST_YCLKGPU_MEMTEST
FB_B_DQ<39>
FB_B_CS_L<1>
FB_B_DQ<51>FB_B_DQ<50>FB_B_DQ<49>
FB_A_DQ<58>FB_A_DQ<59>
FB_A_WE_L<1>
FB_A_DQ<61>FB_A_DQ<62>
GPU_MVREFD0
FB_A_MA<0>FB_A_MA<1>FB_A_MA<2>
FB_A_MA<5>FB_A_MA<6>FB_A_MA<7>
FB_A_MA<11>TP_FB_A_MA12
FB_A_DQM_L<0>FB_A_DQM_L<1>FB_A_DQM_L<2>FB_A_DQM_L<3>FB_A_DQM_L<4>
FB_A_CKE<0>
FB_A_RAS_L<0>
FB_A_CAS_L<0>
FB_A_WE_L<0>
TP_FB_A_ODT<0>
FB_A_CLK_N<1>
FB_A_CS_L<1>
FB_A_CKE<1>
FB_A_RAS_L<1>
FB_A_CAS_L<1>
TP_FB_A_ODT<1>
FB_A_DQ<1>FB_A_DQ<2>FB_A_DQ<3>FB_A_DQ<4>FB_A_DQ<5>FB_A_DQ<6>FB_A_DQ<7>FB_A_DQ<8>FB_A_DQ<9>FB_A_DQ<10>FB_A_DQ<11>FB_A_DQ<12>FB_A_DQ<13>FB_A_DQ<14>FB_A_DQ<15>FB_A_DQ<16>FB_A_DQ<17>FB_A_DQ<18>FB_A_DQ<19>FB_A_DQ<20>FB_A_DQ<21>FB_A_DQ<22>FB_A_DQ<23>FB_A_DQ<24>FB_A_DQ<25>FB_A_DQ<26>FB_A_DQ<27>FB_A_DQ<28>FB_A_DQ<29>FB_A_DQ<30>FB_A_DQ<31>FB_A_DQ<32>FB_A_DQ<33>FB_A_DQ<34>FB_A_DQ<35>FB_A_DQ<36>FB_A_DQ<37>FB_A_DQ<38>FB_A_DQ<39>FB_A_DQ<40>FB_A_DQ<41>FB_A_DQ<42>FB_A_DQ<43>
FB_A_DQ<45>FB_A_DQ<44>
FB_A_DQ<46>FB_A_DQ<47>FB_A_DQ<48>
FB_A_DQ<50>FB_A_DQ<51>
FB_A_DQ<49>
FB_A_DQ<52>FB_A_DQ<53>FB_A_DQ<54>FB_A_DQ<55>FB_A_DQ<56>
FB_A_DQ<63>
FB_A_CLK_P<1>
FB_A_MA<9>FB_A_MA<8>
FB_A_MA<10>
FB_A_BA<1>
FB_A_DQM_L<7>FB_A_DQM_L<6>
FB_A_RDQS<0>FB_A_RDQS<1>FB_A_RDQS<2>FB_A_RDQS<3>FB_A_RDQS<4>FB_A_RDQS<5>
FB_A_RDQS<7>FB_A_RDQS<6>
FB_A_WDQS<0>FB_A_WDQS<1>
FB_A_WDQS<3>FB_A_WDQS<2>
FB_A_WDQS<4>FB_A_WDQS<5>FB_A_WDQS<6>FB_A_WDQS<7>
FB_A_DQ<60>
FB_A_DQM_L<5>
FB_A_DQ<57>
GPU_MVREFS0
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
VOLTAGE=0V
GND_GPU_VSSRH0
68 68
68 68
67 67
67 67
71
63 63
71
71
70
70
70
63 63
70
70
71
71
70
70
70
71
71
71
71
71
71
71
71
71
71
71
69
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
70
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
70
70
70
70
70
70
70
70
70
70
70
70
69
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Required for debug access
Required for debug access
Required for debug access
Required for debug access
0000 = 128MB0010 = 256MB
0110 = Reserved0100 = 64MB
ROMCFGID[3..0]
Required for debug access
Also required: GPIO10 - GPIO13
Renamed signals
Unused signals
TESTIN[0] TX_PWRS_ENb
TESTIN[6] Reserved
TESTIN[5] Reserved
TESTIN[3] Reserved
VDD_VCL TESTIN[2] Reserved
TESTOUT[11] ROMIDCFG[2]
TESTIN[4] DEBUG_ACCESS
TESTIN[9] PWRCNTL
IPD
Serial ROM TestBus Misc Straps
TESTIN[1] TX_DEEMPH_EN
IPD
TESTIN[8]
IPD
IPD
IPD
IPD
TESTOUT[10] ROMIDCFG[1]
ROMSCK TESTOUT[8]
ROMSI ROMIDCFG[3]
ROMSO TESTWR Reserved
ENA_BL TESTIN[7]
IPD
TESTOUT[9] ROMIDCFG[0]
SS_IN
Thm Mon Int
402MF-LF
10K5%
1/16W
R88001
2
GPU_DEEPMH_EN
10K5%1/16WMF-LF402
R88011
2
MF-LF
5%1/16W
10K
402
NO STUFFR88021
2
5%1/16WMF-LF402
10K
NO STUFF
R88031
2
5%10K1/16W
402MF-LF
NO STUFFR88061
2402
1/16W5%
10K
MF-LF
NO STUFFR88041
2
1/16WMF-LF
10K
402
5%
NO STUFF
R88081
2
10K
402MF-LF1/16W5%
R88051
2
5%
GPU_MEM_256M
1/16WMF-LF
402
10KR88121
2
1/16WMF-LF
402
5%10K
NO STUFFR88091
2NO STUFF
5%1/16W
10K
402MF-LF
R88111
2402MF-LF
10K1/16W5%
GPU_MEM_64MR88131
2
1/16W
402MF-LF
4.7K5%
R93911
2MF-LF
402
1/16W
4.7K5%
R93901
2
MF-LF402
1/16W
10K5%
GPU_MEM_256MR88241
2
1/16WMF-LF
10K
402
5%
GPU_MEM_HYNIX
R88271
2
GPU StrapsSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
051-7099 D
10488
GPU_GPIO_16
GPU_GPIO_17
GPU_GPIO_18
GPU_GPIO_19
GPU_GPIO_20
GPU_GPIO_14
GPU_GPIO_7
GPU_GPIO_10
MAKE_BASE=TRUENO_TEST=TRUE
NC_GPU_GPIO_22
MAKE_BASE=TRUENO_TEST=TRUE
NC_GPU_GPIO_32
MAKE_BASE=TRUENO_TEST=TRUE
NC_GPU_GPIO_33
MAKE_BASE=TRUENO_TEST=TRUE
NC_GPU_GPIO_34
MAKE_BASE=TRUENO_TEST=TRUE
NC_GPU_GPIO_29
NO_TEST=TRUE
NC_GPU_GPIO_30MAKE_BASE=TRUE
MAKE_BASE=TRUENO_TEST=TRUE
NC_GPU_GPIO_31
MAKE_BASE=TRUENO_TEST=TRUE
NC_GPU_GPIO_28
NO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_GPIO_26
NO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_GPIO_23
NO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_GPIO_19
MAKE_BASE=TRUENO_TEST=TRUE
NC_GPU_GPIO_20
MAKE_BASE=TRUENC_GPU_GPIO_18
NO_TEST=TRUE
MAKE_BASE=TRUENC_GPU_GPIO_17 NO_TEST=TRUE
MAKE_BASE=TRUENC_GPU_GPIO_14 NO_TEST=TRUE
GPU_GPIO_15
GPU_GPIO_21
GPU_GPIO_23
GPU_GPIO_22
GPU_GPIO_26
GPU_GPIO_25
GPU_GPIO_28
GPU_GPIO_31
GPU_GPIO_30
GPU_GPIO_29
GPU_GPIO_34
GPU_GPIO_33
GPU_GPIO_32
MAKE_BASE=TRUEGPU_CLK27MSS_IN
TP_GPU_GPIO_10MAKE_BASE=TRUE
MAKE_BASE=TRUEGPU_BLON
GPU_GPIO_0
GPU_GPIO_1
NC_GPU_GPIO_21MAKE_BASE=TRUENO_TEST=TRUE
MAKE_BASE=TRUENO_TEST=TRUE
NC_GPU_GPIO_25
GPU_GPIO_24
GPU_GPIO_27
MAKE_BASE=TRUEGPU_VCORE_LOW
GPU_DDC_B_CLKGPU_DDC_B_DATA
=PP3V3_S0_GPU
ATI_DVPDATA<15..0>MAKE_BASE=TRUE NO_TEST=TRUENC_ATI_DVPDATA<15..0>
ATI_DVPCNTL<2..0>MAKE_BASE=TRUE NO_TEST=TRUENC_ATI_DVPCNTL<2..0>
LVDS_L_DATA_N<3>NO_TEST=TRUEMAKE_BASE=TRUE
NC_LVDS_L_DATAN<3>
ATI_DVPCLKNO_TEST=TRUEMAKE_BASE=TRUE
NC_ATI_DVPCLK
LVDS_L_DATA_P<3>NO_TEST=TRUEMAKE_BASE=TRUE
NC_LVDS_L_DATAP<3>
LVDS_U_DATA_N<3>NO_TEST=TRUEMAKE_BASE=TRUE
NC_LVDS_U_DATAN<3>
LVDS_U_DATA_P<3>NO_TEST=TRUEMAKE_BASE=TRUE
NC_LVDS_U_DATAP<3>
GPU_TV_COMPMAKE_BASE=TRUE NO_TEST=TRUENC_GPU_TV_COMP
GPU_TV_YNO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_TV_Y
GPU_TV_CMAKE_BASE=TRUE NO_TEST=TRUENC_GPU_TV_C
GPU_VGA_VSYNCMAKE_BASE=TRUETP_GPU_VGA_VSYNC
GPU_VGA_HSYNCMAKE_BASE=TRUETP_GPU_VGA_HSYNC
GPU_VGA_BNO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_VGA_B
GPU_VGA_RMAKE_BASE=TRUE NO_TEST=TRUENC_GPU_VGA_R
GPU_VGA_GNO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_VGA_G
GPU_GENERICCNO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_GENERICC
GPU_GENERICBMAKE_BASE=TRUE NO_TEST=TRUENC_GPU_GENERICB
GPU_GENERICANO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_GENERICA
TP_FB_B_MA12MAKE_BASE=TRUE NO_TEST=TRUENC_FB_B_MA12
TP_FB_A_MA12MAKE_BASE=TRUE NO_TEST=TRUENC_FB_A_MA12
TP_ATI_ROMCS_LMAKE_BASE=TRUE NO_TEST=TRUENC_ATI_ROMCS_L
GPU_XTALOUTMAKE_BASE=TRUE NO_TEST=TRUENC_GPU_XTALOUT
GPU_XTALINMAKE_BASE=TRUEGPU_CLK27M
ATI_DVPDATA<23..16>MAKE_BASE=TRUETP_ATI_DVPDATA<23..16>
GPU_GPIO_5
GPU_GPIO_4
GPU_GPIO_12
GPU_GPIO_8
GPU_GPIO_6
GPU_GPIO_11
GPU_GPIO_3
GPU_GPIO_9
GPU_GPIO_2
GPU_GPIO_13
MAKE_BASE=TRUEGPU_MEM_256M
MAKE_BASE=TRUEGPU_MEMID
=PP3V3_S0_GPU_GPIOS
72 66
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
34
74
72
72
72
72
66
73
73
63
72
72
73
72
73
73
73
73
73
73
73
73
73
73
73
72
72
72
68
68
72
72
72 34
72
72
72
72
72
72
72
72
72
72
72
63
DQ1
DQ0
DQ2
DQ3
DQ5
DQ6
DQ4
DQ8
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ24
DQ23
DQ22
DQ25
DQ26
DQ27
DQ29
DQ28
DQ30
DQ31
RDQS3
RDQS2
RDQS1
RDQS0
SEN
RESET
MF
ZQ
RAS*
CAS*
WE*
CS*
CK*
A9
A6
A7
A3
A4
A2
A0
A1
CK
WDQS2
WDQS1
WDQS0
WDQS3
BA0
BA2
BA1
RFU1
RFU2
DM3
DM2
DM1
DM0
A5
A11
A8/AP
A10
CKE
MFHIGH
MFHIGH
MFHIGH
(1 OF 2)
VSS0
VSS1
VSS2
VSS5
VSS3
VSS4
VSS7
VSS6
VSSA0
VSSA1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ5
VSSQ6
VSSQ4
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ16
VSSQ15
VSSQ17
VSSQ18
VSSQ19VDDQ19
VDDQ20
VDDQ21
VREF1
VREF0
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ18
VDDQ16
VDDQ17
VDDQ9
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ5
VDDQ3
VDDQ4
VDDQ6
VDDQ7
VDDQ8
VDD0
VDD1
VDD2
VDD5
VDD3
VDD4
VDD6
VDD7
VDDA0
(2 OF 2)
IN
IN
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DQ1
DQ0
DQ2
DQ3
DQ5
DQ6
DQ4
DQ8
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ24
DQ23
DQ22
DQ25
DQ26
DQ27
DQ29
DQ28
DQ30
DQ31
RDQS3
RDQS2
RDQS1
RDQS0
SEN
RESET
MF
ZQ
RAS*
CAS*
WE*
CS*
CK*
A9
A6
A7
A3
A4
A2
A0
A1
CK
WDQS2
WDQS1
WDQS0
WDQS3
BA0
BA2
BA1
RFU1
RFU2
DM3
DM2
DM1
DM0
A5
A11
A8/AP
A10
CKE
MFHIGH
MFHIGH
MFHIGH
(1 OF 2)
VSS0
VSS1
VSS2
VSS5
VSS3
VSS4
VSS7
VSS6
VSSA0
VSSA1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ5
VSSQ6
VSSQ4
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ16
VSSQ15
VSSQ17
VSSQ18
VSSQ19VDDQ19
VDDQ20
VDDQ21
VREF1
VREF0
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ18
VDDQ16
VDDQ17
VDDQ9
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ5
VDDQ3
VDDQ4
VDDQ6
VDDQ7
VDDQ8
VDD0
VDD1
VDD2
VDD5
VDD3
VDD4
VDD6
VDD7
VDDA0
(2 OF 2)
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IO
IO
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Connect to designated pin, then GND
BOM options provided by this page:
Signal aliases required by this page:
Power aliases required by this page:
Page Notes
NOTE: U8900 DQ0-7 MUST connect to GPU
within byte-lane, but software must know
U8900.J12U8900.J1
NCNCNC
NC
U8900.J1 U8900.J12
- =PP1V8_S0_FB_VDDQ- =PP1V8_S0_FB_VDD
(NONE)
(NONE)
GDDR3 vendor/device identification scheme.how these bits are mapped for GPU to support
DQA0-7 or DQA8-15. Bits can be swapped
Connect to designated pin, then GND
2
1R89302.37K
MF-LF402
1%1/16W
2
1R89315.49K
MF-LF
1%1/16W
402
2
1 C89030.1uF
X5R402
10%16V2
1 C8902
X5R402
10%16V
0.1uF
2
1 C89040.1uF
X5R402
10%16V2
1 C89010.1uF
X5R402
10%16V
2
1 C89220.1uF
X5R402
10%16V 2
1 C89230.1uF
402
10%16VX5R 2
1 C89240.1uF
X5R402
10%16V 2
1 C89250.1uF
X5R402
10%16V 2
1 C8926
X5R402
10%16V
0.1uF
A4
H4
P2
P11
D11
D2
V4
J3
J2
V9
P3
P10
D10
D3
H10
A9
B10
B11
G3
F2
F3
E2
T3
T2
C3
R3
R2
M3
N2
L3
M2
T10
T11
R10
R11
C2
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B3
B2
N3
N10
E10
E3
F4
H9
J10
J11
F9
H3
G4
G9
M4
K2
L4
K3
H2
K4
M9
K10
L9
K11
H11
K9 U8900FBGA
CRITICALOMIT
K4J52324QC-BC20
16MX32-GDDR3-500MHZ
G11
G2
D12
D9
D4
D1
B12
B9
T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
B4
B1
J12
J1
V10
V3
L12
L1
G12
G1
A10
A3
H12
H1
E12
E9
E4
E1
C12
C9
C4
V12
V1
C1
R12
R9
R4
R1
N12
N9
N4
N1
J9
J4
A12
A1
K12
K1
V11
V2
M12
M1
F12
F1
A11
A2U8900FBGA
K4J52324QC-BC20
16MX32-GDDR3-500MHZ
CRITICALOMIT
2
1R8949
MF-LF402
5%1/16W
100
2
1R89415%
402MF-LF1/16W
1K
2
1R8948243
MF-LF402
1%1/16W
2
1R894560.4
MF-LF402
1%1/16W
2
1R8946
1/16W1%
402MF-LF
60.4
2
1 C8933
16V10%
402X5R
0.1uF
2
1R8932
1/16W1%
402MF-LF
2.37K
2
1R89335.49K
MF-LF402
1%1/16W
2
1 C8921
16V
402X5R
0.1uF10%
21
L8910
0402
FERR-220-OHM
21
L8915
0402
FERR-220-OHM
2
1 C89150.1uF
X5R402
10%16V2
1 C89100.1uF
X5R402
16V10%
2
1R8940
1/16W
402MF-LF
1211%
2
1R8947
1/16W
402MF-LF
1211%
2
1R89441%
121
MF-LF402
1/16W
2
1R8943
1/16W
402
1211%
MF-LF
2
1R89421%
121
MF-LF402
1/16W
2
1R8991
MF-LF402
5%1/16W
1K
2
1R89901%
121
MF-LF402
1/16W
2
1R8992
1/16W
402MF-LF
1211%
2
1 C8971
16V
402X5R
0.1uF10%
2
1 C8972
16V10%
402X5R
0.1uF
2
1R8998
1/16W1%
402MF-LF
243
2
1R8999
1/16W5%
402MF-LF
100
A4
H4
P2
P11
D11
D2
V4
J3
J2
V9
P3
P10
D10
D3
H10
A9
B10
B11
G3
F2
F3
E2
T3
T2
C3
R3
R2
M3
N2
L3
M2
T10
T11
R10
R11
C2
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B3
B2
N3
N10
E10
E3
F4
H9
J10
J11
F9
H3
G4
G9
M4
K2
L4
K3
H2
K4
M9
K10
L9
K11
H11
K9 U8950FBGA
K4J52324QC-BC20
16MX32-GDDR3-500MHZ
OMITCRITICAL
2
1R89931%121
MF-LF402
1/16W
2
1R8995
1/16W1%
402MF-LF
60.4
2
1R8994
1/16W
402MF-LF
1211%
2
1R89971%121
MF-LF402
1/16W
2
1R899660.4
MF-LF402
1%1/16W
2
1R8981
1/16W1%
402MF-LF
5.49K
2
1R8980
1/16W1%
402MF-LF
2.37K
2
1R8983
1/16W1%
402MF-LF
5.49K
2
1R89822.37K
MF-LF402
1%1/16W
2
1 C8973
16V10%
402X5R
0.1uF
2
1 C8981
16V10%
402X5R
0.1uF
2
1 C8974
16V10%
402X5R
0.1uF
2
1 C8975
16V10%
402X5R
0.1uF
2
1 C89830.1uF
X5R402
10%16V
G11
G2
D12
D9
D4
D1
B12
B9
T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
B4
B1
J12
J1
V10
V3
L12
L1
G12
G1
A10
A3
H12
H1
E12
E9
E4
E1
C12
C9
C4
V12
V1
C1
R12
R9
R4
R1
N12
N9
N4
N1
J9
J4
A12
A1
K12
K1
V11
V2
M12
M1
F12
F1
A11
A2U8950FBGA
K4J52324QC-BC20
16MX32-GDDR3-500MHZ
OMITCRITICAL
2
1 C8976
16V10%
402X5R
0.1uF
21
L8965FERR-220-OHM
0402
21
L8960FERR-220-OHM
0402
2
1 C8951
16V10%
402
0.1uF
X5R 2
1 C8952
16V10%
X5R
0.1uF
402
2
1 C8960
16V10%
402X5R
0.1uF
2
1 C8953
16V10%
402X5R
0.1uF
2
1 C8965
16V10%
402X5R
0.1uF
2
1 C8954
16V10%
402X5R
0.1uF
2
1C8900
6.3VCERM805
20%22UF
2
1C892020%
6.3V
805
22UF
CERM
2
1C895022UF
805CERM6.3V20%
2
1C897022UF
CERM6.3V20%
805
2
1 C89310.1uF
X5R402
10%16V
051-7099 D
10489
GDDR3 Frame Buffer ASYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
=PP1V8_S0_FB_VDDQ
FB_A0_VREF0MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
FB_A1_VREF0MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
FB_A_CKE<1>
FB_A_MA<10>
FB_A_MA<8>
FB_A_MA<11>
FB_A_MA<5>
FB_A_DQM_L<4>FB_A_DQM_L<5>FB_A_DQM_L<6>FB_A_DQM_L<7>
FB_A_BA<1>FB_A_BA<0>
FB_A_WDQS<7>
FB_A_WDQS<4>FB_A_WDQS<5>FB_A_WDQS<6>
FB_A_CLK_P<1>
FB_A_MA<1>FB_A_MA<0>
FB_A_MA<2>
FB_A_MA<4>FB_A_MA<3>
FB_A_MA<7>FB_A_MA<6>
FB_A_MA<9>
FB_A_CLK_N<1>FB_A_CS_L<1>FB_A_WE_L<1>FB_A_CAS_L<1>
FB_A1_ZQFB_A1_MF
FB_DRAM_RSTFB_A1_SEN
FB_A_RDQS<4>FB_A_RDQS<5>
FB_A_DQ<58>FB_A_DQ<63>
FB_A_DQ<62>FB_A_DQ<56>
FB_A_DQ<57>FB_A_DQ<61>FB_A_DQ<59>
FB_A_DQ<54>FB_A_DQ<53>FB_A_DQ<60>
FB_A_DQ<55>FB_A_DQ<52>FB_A_DQ<51>FB_A_DQ<50>FB_A_DQ<49>FB_A_DQ<48>FB_A_DQ<45>FB_A_DQ<47>FB_A_DQ<44>
FB_A_DQ<39>
FB_A_DQ<35>
FB_A_DQ<32>
FB_A_MA<10>
FB_A_MA<8>
FB_A_DQM_L<0>
FB_A_DQM_L<2>FB_A_DQM_L<3>
FB_A_BA<1>FB_A_BA<0>
FB_A_WDQS<3>
FB_A_WDQS<0>
FB_A_MA<1>
FB_A_MA<9>
FB_A_CLK_N<0>FB_A_CS_L<0>FB_A_WE_L<0>
FB_A0_ZQFB_A0_MF
FB_A_DQ<31>FB_A_DQ<28>
FB_A_DQ<29>FB_A_DQ<30>
FB_A_DQ<27>FB_A_DQ<26>FB_A_DQ<25>
FB_A_DQ<20>FB_A_DQ<22>FB_A_DQ<24>
FB_A_DQ<21>FB_A_DQ<23>FB_A_DQ<17>FB_A_DQ<18>FB_A_DQ<16>FB_A_DQ<19>FB_A_DQ<13>FB_A_DQ<12>FB_A_DQ<14>FB_A_DQ<15>FB_A_DQ<11>FB_A_DQ<10>FB_A_DQ<9>
FB_A_DQ<7>FB_A_DQ<8>
FB_A_DQ<4>
FB_A_DQ<6>FB_A_DQ<5>
FB_A_DQ<3>FB_A_DQ<2>
FB_A_DQ<0>FB_A_DQ<1>
FB_A_MA<7>FB_A_MA<6>
FB_A_MA<11>
FB_A_WDQS<2>FB_A_WDQS<1>
FB_A0_VREF1MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
=PP1V8_S0_FB_VDDQ
FB_A_RAS_L<1>
FB_A_BA<2>FB_A_BA<2>
FB_A_DQM_L<1>
FB_A_CLK_P<0>
FB_A_RDQS<3>FB_A_RDQS<2>FB_A_RDQS<1>
FB_A0_SEN
FB_A_RDQS<0>
FB_DRAM_RST
FB_A_CAS_L<0>
FB_A_CKE<0>
FB_A_MA<4>FB_A_MA<5>
FB_A_DQ<34>FB_A_DQ<33>
FB_A_DQ<36>FB_A_DQ<37>FB_A_DQ<38>
FB_A_DQ<40>FB_A_DQ<41>FB_A_DQ<42>FB_A_DQ<43>FB_A_DQ<46>
FB_A1_VREF1MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.8VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmPP1V8_S0_FB_A1_VDDA0
VOLTAGE=1.8VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmPP1V8_S0_FB_A1_VDDA1
VOLTAGE=1.8VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmPP1V8_S0_FB_A0_VDDA1
VOLTAGE=1.8VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmPP1V8_S0_FB_A0_VDDA0
=PP1V8_S0_FB_VDD
FB_A_MA<3>FB_A_MA<2>
FB_A_MA<0>
FB_A_RAS_L<0>
FB_A_RDQS<6>FB_A_RDQS<7>
=PP1V8_S0_FB_VDD
71
71
71
71
71 71
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70 70
70
70
70
70
70
70
70
70
63
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
63
68
68 68
68
68
68
68
68
68
68
68
68
68
68 68
68
68
68
68
68
68
68
68
68
63
68
68
68
68
68
68
63
DQ1
DQ0
DQ2
DQ3
DQ5
DQ6
DQ4
DQ8
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ24
DQ23
DQ22
DQ25
DQ26
DQ27
DQ29
DQ28
DQ30
DQ31
RDQS3
RDQS2
RDQS1
RDQS0
SEN
RESET
MF
ZQ
RAS*
CAS*
WE*
CS*
CK*
A9
A6
A7
A3
A4
A2
A0
A1
CK
WDQS2
WDQS1
WDQS0
WDQS3
BA0
BA2
BA1
RFU1
RFU2
DM3
DM2
DM1
DM0
A5
A11
A8/AP
A10
CKE
MFHIGH
MFHIGH
MFHIGH
(1 OF 2)
VSS0
VSS1
VSS2
VSS5
VSS3
VSS4
VSS7
VSS6
VSSA0
VSSA1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ5
VSSQ6
VSSQ4
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ16
VSSQ15
VSSQ17
VSSQ18
VSSQ19VDDQ19
VDDQ20
VDDQ21
VREF1
VREF0
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ18
VDDQ16
VDDQ17
VDDQ9
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ5
VDDQ3
VDDQ4
VDDQ6
VDDQ7
VDDQ8
VDD0
VDD1
VDD2
VDD5
VDD3
VDD4
VDD6
VDD7
VDDA0
(2 OF 2)
IN
IN
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DQ1
DQ0
DQ2
DQ3
DQ5
DQ6
DQ4
DQ8
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ24
DQ23
DQ22
DQ25
DQ26
DQ27
DQ29
DQ28
DQ30
DQ31
RDQS3
RDQS2
RDQS1
RDQS0
SEN
RESET
MF
ZQ
RAS*
CAS*
WE*
CS*
CK*
A9
A6
A7
A3
A4
A2
A0
A1
CK
WDQS2
WDQS1
WDQS0
WDQS3
BA0
BA2
BA1
RFU1
RFU2
DM3
DM2
DM1
DM0
A5
A11
A8/AP
A10
CKE
MFHIGH
MFHIGH
MFHIGH
(1 OF 2)
VSS0
VSS1
VSS2
VSS5
VSS3
VSS4
VSS7
VSS6
VSSA0
VSSA1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ5
VSSQ6
VSSQ4
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ16
VSSQ15
VSSQ17
VSSQ18
VSSQ19VDDQ19
VDDQ20
VDDQ21
VREF1
VREF0
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ18
VDDQ16
VDDQ17
VDDQ9
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ5
VDDQ3
VDDQ4
VDDQ6
VDDQ7
VDDQ8
VDD0
VDD1
VDD2
VDD5
VDD3
VDD4
VDD6
VDD7
VDDA0
(2 OF 2)
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IO
IO
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Page NotesPower aliases required by this page:
BOM options provided by this page:
Signal aliases required by this page:(NONE)
(NONE)
- =PP1V8_S0_FB_VDD- =PP1V8_S0_FB_VDDQ
U9000.J12U9000.J1
NCNC NC
NC
U9000.J1 U9000.J12Connect to designated pin, then GNDConnect to designated pin, then GND
2
1R9030
1/16W1%
402MF-LF
2.37K
2
1R9031
1/16W1%
402MF-LF
5.49K
2
1 C9003
16V10%
X5R
0.1uF
4022
1 C9002
16V10%
402X5R
0.1uF
2
1 C9004
16V10%
402X5R
0.1uF
2
1 C9001
402
16V10%
X5R
0.1uF
2
1 C9022
16V10%
402X5R
0.1uF
2
1 C9023
16V10%
402X5R
0.1uF
2
1 C9024
16V10%
402X5R
0.1uF
2
1 C9025
16V10%
402X5R
0.1uF
2
1 C902610%
X5R
0.1uF
402
16V
A4
H4
P2
P11
D11
D2
V4
J3
J2
V9
P3
P10
D10
D3
H10
A9
B10
B11
G3
F2
F3
E2
T3
T2
C3
R3
R2
M3
N2
L3
M2
T10
T11
R10
R11
C2
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B3
B2
N3
N10
E10
E3
F4
H9
J10
J11
F9
H3
G4
G9
M4
K2
L4
K3
H2
K4
M9
K10
L9
K11
H11
K9 U9000
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
FBGA
CRITICALOMIT
G11
G2
D12
D9
D4
D1
B12
B9
T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
B4
B1
J12
J1
V10
V3
L12
L1
G12
G1
A10
A3
H12
H1
E12
E9
E4
E1
C12
C9
C4
V12
V1
C1
R12
R9
R4
R1
N12
N9
N4
N1
J9
J4
A12
A1
K12
K1
V11
V2
M12
M1
F12
F1
A11
A2U9000
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
CRITICALOMIT
FBGA
2
1R9049
1/16W5%
402MF-LF
100
2
1R9041
MF-LF402
5%1/16W
1K
2
1R9048
1/16W1%
402MF-LF
243
2
1R9045
1/16W1%
402MF-LF
60.4
2
1R904660.4
MF-LF402
1%1/16W
2
1 C90330.1uF
X5R402
10%16V
2
1R9032
MF-LF402
1%1/16W
2.37K
2
1R9033
1/16W1%
402MF-LF
5.49K
2
1 C9021
16V10%
X5R
0.1uF
402
21
L9010FERR-220-OHM
0402
21
L9015FERR-220-OHM
0402 2
1 C9015
16V10%
402X5R
0.1uF
2
1 C9010
16V10%
402X5R
0.1uF
2
1R90401%
121
MF-LF402
1/16W
2
1R90471%121
MF-LF402
1/16W
2
1R9044
1/16W
402MF-LF
1211%
2
1R90431%121
MF-LF402
1/16W
2
1R9042
1/16W
402MF-LF
1211%
2
1R9091
1/16W5%
402MF-LF
1K
2
1R9090
1/16W
402MF-LF
1211%
2
1R9092
MF-LF
1211%
402
1/16W
2
1 C9071
X5R402
10%16V
0.1uF
2
1 C9072
X5R402
10%16V
0.1uF
2
1R9098
1/16W
402MF-LF
2431%
2
1R9099
1/16W
402MF-LF
5%100
A4
H4
P2
P11
D11
D2
V4
J3
J2
V9
P3
P10
D10
D3
H10
A9
B10
B11
G3
F2
F3
E2
T3
T2
C3
R3
R2
M3
N2
L3
M2
T10
T11
R10
R11
C2
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B3
B2
N3
N10
E10
E3
F4
H9
J10
J11
F9
H3
G4
G9
M4
K2
L4
K3
H2
K4
M9
K10
L9
K11
H11
K9 U9050
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
OMITCRITICAL
FBGA
2
1R90931%
MF-LF402
1/16W
121
2
1R9095
MF-LF402
1%1/16W
60.4
2
1R9094121
MF-LF1/16W
1%
402
2
1R9097
402
1%1/16WMF-LF
121
2
1R9096
1/16W1%
402MF-LF
60.4
2
1R9081
402MF-LF
5.49K1%
1/16W
2
1R9080
402MF-LF
2.37K1%
1/16W
2
1R9083
MF-LF
5.49K
402
1/16W1%
2
1R9082
MF-LF402
1/16W1%
2.37K
2
1 C907310%
402X5R16V
0.1uF
2
1 C90810.1uF
X5R402
10%16V
2
1 C9074
16V10%
402X5R
0.1uF
2
1 C9075
X5R402
10%16V
0.1uF
2
1 C9083
402
10%16VX5R
0.1uF
G11
G2
D12
D9
D4
D1
B12
B9
T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
B4
B1
J12
J1
V10
V3
L12
L1
G12
G1
A10
A3
H12
H1
E12
E9
E4
E1
C12
C9
C4
V12
V1
C1
R12
R9
R4
R1
N12
N9
N4
N1
J9
J4
A12
A1
K12
K1
V11
V2
M12
M1
F12
F1
A11
A2U9050
K4J52324QC-BC20
OMITCRITICAL
FBGA
16MX32-GDDR3-500MHZ
2
1 C9076
X5R402
10%16V
0.1uF
21
L9065
0402
FERR-220-OHM
21
L9060
0402
FERR-220-OHM
2
1 C90510.1uF
X5R402
10%16V 2
1 C90520.1uF
X5R402
10%16V
2
1 C9060
16V10%
402X5R
0.1uF
2
1 C9053
16V10%
402X5R
0.1uF
2
1 C9065
16V10%
402X5R
0.1uF
2
1 C90540.1uF
X5R402
10%16V
2
1C900022UF
805CERM6.3V20%
2
1C902022UF
805CERM6.3V20%
2
1C905022UF
805CERM6.3V20%
2
1C9070
805CERM6.3V20%
22UF
2
1 C9031
16V10%
402
0.1uF
X5R
90 104
D051-7099
GDDR3 Frame Buffer BSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
FB_B_MA<4>
FB_B_CS_L<1>
FB_B_MA<9>
FB_B_DQ<2>FB_B_DQ<7>
FB_B_DQ<24>
FB_B_DQ<13>FB_B_DQ<14>FB_B_DQ<12>FB_B_DQ<15>
FB_B_DQM_L<3>
FB_B_WDQS<1>
FB_B_RDQS<0>FB_B_RDQS<3>FB_B_RDQS<2>
FB_DRAM_RST
FB_B0_ZQ
FB_B0_SEN
FB_B_DQ<23>
FB_B_CLK_N<1>
FB_B_CAS_L<1>FB_B_WE_L<1>
FB_B_RAS_L<1>FB_B1_ZQ
FB_B_DQ<61>
FB_B_DQ<46>
FB_B_CLK_P<1>
FB_B_MA<1>FB_B_MA<2>FB_B_MA<3>
FB_B_CKE<1>
FB_B_DQ<58>FB_B_DQ<59>
=PP1V8_S0_FB_VDDQ
FB_B_MA<5>
FB_B_MA<7>
FB_B_BA<0>FB_B_BA<1>
FB_B_CKE<0>
FB_B_DQ<9>FB_B_DQ<11>
FB_B_DQ<8>
FB_B_DQ<18>FB_B_DQ<10>
FB_B_DQ<17>FB_B_DQ<19>FB_B_DQ<16>FB_B_DQ<20>FB_B_DQ<22>
FB_B_DQ<21>FB_B_DQ<29>FB_B_DQ<30>FB_B_DQ<28>FB_B_DQ<31>FB_B_DQ<27>
FB_B_DQ<1>FB_B_DQ<25>FB_B_DQ<26>
FB_B_DQ<6>FB_B_DQ<0>FB_B_DQ<5>FB_B_DQ<3>
FB_B_DQ<4>
FB_B_RDQS<1>
FB_B0_MF
FB_B_CAS_L<0>FB_B_WE_L<0>FB_B_CS_L<0>FB_B_CLK_N<0>
FB_B_MA<9>
FB_B_MA<6>FB_B_MA<7>
FB_B_MA<0>FB_B_MA<1>
FB_B_WDQS<3>FB_B_WDQS<2>
FB_B_WDQS<0>
FB_B_DQM_L<0>
FB_B_DQM_L<2>FB_B_DQM_L<1>
FB_B_MA<5>
FB_B_MA<11>
FB_B_MA<8>
FB_B_MA<10>
FB_B_DQ<53>FB_B_DQ<54>
FB_B_DQ<52>FB_B_DQ<55>
FB_B_DQ<48>FB_B_DQ<49>
FB_B_DQ<50>
FB_B_DQ<44>FB_B_DQ<51>
FB_B_DQ<47>FB_B_DQ<45>
FB_B_DQ<43>FB_B_DQ<41>FB_B_DQ<42>FB_B_DQ<40>FB_B_DQ<37>FB_B_DQ<32>FB_B_DQ<39>FB_B_DQ<34>FB_B_DQ<36>FB_B_DQ<35>
FB_B_DQ<63>FB_B_DQ<33>
FB_B_DQ<62>FB_B_DQ<60>FB_B_DQ<56>
FB_B_DQ<57>
FB_B_RDQS<7>FB_B_RDQS<4>
FB_B_RDQS<6>
FB_B1_SENFB_DRAM_RST
FB_B1_MF
FB_B_MA<6>
FB_B_WDQS<4>FB_B_WDQS<5>FB_B_WDQS<6>
FB_B_WDQS<7>
FB_B_BA<0>FB_B_BA<1>
FB_B_DQM_L<7>FB_B_DQM_L<4>FB_B_DQM_L<5>FB_B_DQM_L<6>
FB_B_MA<11>
FB_B_MA<8>
FB_B1_VREF1MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
FB_B1_VREF0MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
FB_B0_VREF1MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
FB_B0_VREF0MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
FB_B_RAS_L<0>
FB_B_BA<2> FB_B_BA<2>
FB_B_RDQS<5>
FB_B_MA<10>
FB_B_DQ<38>
=PP1V8_S0_FB_VDDQ
FB_B_MA<4>FB_B_MA<3>FB_B_MA<2>
FB_B_CLK_P<0>
VOLTAGE=1.8VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmPP1V8_S0_FB_B1_VDDA1
VOLTAGE=1.8VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmPP1V8_S0_FB_B1_VDDA0
=PP1V8_S0_FB_VDD
VOLTAGE=1.8VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmPP1V8_S0_FB_B0_VDDA0
VOLTAGE=1.8VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmPP1V8_S0_FB_B0_VDDA1
=PP1V8_S0_FB_VDD
FB_B_MA<0>
71
71
71
71
71 71
71
71
70
71
71
71
70
71
71
71
71
71
71
71
71
71
71
71
71
71
70
71
71
71
71
71
71 71
71
70
71
71
71
70 70
71
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
63
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68 68
68
68
68
63
68
68
68
68
63 63
68
GPIO_0
GPIO_1
TESTEN
GPIO_2
GPIO_27
PLLTEST
XTALOUT
XTALIN
MPVSS
MPVDD
PVSS
PVDD
GPIO_16
GPIO_17
GPIO_15
GPIO_14
GPIO_13
GPIO_12
GPIO_11
GPIO_10
GPIO_9
GPIO_8
GPIO_7_BLON
GPIO_6
GPIO_5
GPIO_4
GPIO_3
VREFG
GPIO_33
GPIO_31
GPIO_32
GPIO_25
GPIO_26
GPIO_24
GPIO_21
GPIO_20
GPIO_19
DMINUS
DPLUS
ROMCS*
GPIO_34
GPIO_29
GPIO_30
NC_DVOVMODE_0
NC_DVOVMODE_1
DVPCLK
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPDATA_2
DVPDATA_1
DVPDATA_0
DVPDATA_4
DVPDATA_3
DVPDATA_5
DVPDATA_7
DVPDATA_6
DVPDATA_9
DVPDATA_8
DVPDATA_10
DVPDATA_11
DVPDATA_13
DVPDATA_12
DVPDATA_15
DVPDATA_14
DVPDATA_16
DVPDATA_18
DVPDATA_17
DVPDATA_19
DVPDATA_21
DVPDATA_20
DVPDATA_23
DVPDATA_22
GENERICA
GENERICB
GENERICC
GENERICD
DIGON
VARY_BL
NC0
GPIO_18
VDDPLL
GPIO_28
GPIO_22
GPIO_23
GENERAL PURPOSE I/O
(1.2V)
(2.5V)
ROM
TEST
PLL & XTAL
VIP HOST / EXTERNAL TMDS
PANELCONTROL
VDDR3(3.3V)
(2.5V)VDD25
VDDR5
(1.8V/3.3V)
(1.8V/3.3V)
VDDR4
DIODETHERMAL
(2.5V)
(6 OF 7)
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
100mA
BOM options provided by this page:
Typically <50mA
Typically <50mA
Typically <50mA
20mA
external TMDS transmitters
- =PP2V5_PVDD
(NONE)
external TMDS transmitters
- =PP1V8_GPU_LVDS_PLL
- =PP3V3_GPU_GPIOS
- =I2C_GPU_TMDS_SDA - I2C data line for
(PP2V5_S0_GPU_PVDD_F)
(GND_GPU_MPVSS)
(GND_GPU_PVSS)
Signal aliases required by this page:
NC
NC
NCNC
(PP1V0R1V2_S0_GPU_MPVDD)
Page Notes
- =I2C_GPU_TMDS_SCL - I2C clock line for
Power aliases required by this page:
70mA total for VDD25
20mA
10%16VX5R
0.1uF
402
C91121
26.3VCERM
1uF
402
10%
C91111
2
402
1uF6.3VCERM
10%
C91161
26.3VCERM
1uF10%
402
C91171
2
10%
X5R402
0.1uF16V
C91371
26.3VCERM402
10%1uFC91361
2
FERR-220-OHM
0402
L9135
1 2
6.3VCERM
1uF
402
10%
C91411
2
FERR-220-OHM
0402
L9140
1 2
X5R16V
0.1uF10%
402
C91421
2
5%1/16WMF-LF402
1KR91951
2
SMXW91401 2
1%4991/16WMF-LF402
R91911
2
1%499
402MF-LF1/16W
R91901
2
SMXW91351 2
22UF
805CERM6.3V20%
C9100 1
2
20%6.3VCERM805
22UFC9110 1
2
22UF
805CERM6.3V20%
C9115 1
2
20%6.3VCERM805
22UFC9120 1
2
22UF
805CERM6.3V20%
C9125 1
2
10%
402
1uF6.3VCERM
C91321
2
22UF
805CERM6.3V20%
C9130 1
2
805CERM6.3V20%
22UFC9135 1
2
22UF
805CERM6.3V20%
C9140 1
2
10%16VX5R402
0.1uFC9191 1
2
OMIT
BGAM56PU8400
AE11
AH12
AG12
AG1
AF2
AF1
AF3
AG2
AG3
AL3
AM3
AE6
AF4
AF5
AG4
AJ3
AH4
AJ4
AG5
AH2
AH5
AF6
AE7
AG6
AH3
AJ2
AJ1
AK2
AK1
AK3
AL2
AK22
AF23
AE23
AD23
AD4
AD2
AC4
AB3
AB4
AB5
AD5
AB8
AA8
AB7
AE13
AF13
AD1
AF9
AG7
AE10
AE9
AF7
AF8
AH6
AF10
AG10
AH9
AD3
AJ8
AH8
AG9
AH7
AG8
AC1
AC2
AC3
AB2
AC6
AC5
A6
A5
AB6
AK4
AL4
AG14
AJ14
AH14
AC7
AG22
AD12K22
L10
AA10
AC13
AC16
AC18
AC15
AA9
AB9
AB10
AC19
AC20
AD18
AD19
AD20
AJ5
AK5
AL5
AM5
AE2
AE3
AE4
AE5
AC8
AL26
AM26
0.1uF
402X5R16V10%
C91271
210%
402
1uF
CERM6.3V
C91261
2
10%16VX5R
0.1uF
402
C91221
26.3VCERM
1uF10%
402
C91211
2
FERR-220-OHM
0402
L9120
1 2
FERR-220-OHM
0402
L9125
1 2
200-OHM-EMI
0402
L9130
1 2
10%
402CERM6.3V
1uFC91311
2
10%
402
1uF
CERM6.3V
C91011
26.3V
1uF10%
402CERM
C91021
26.3VCERM
1uF
402
10%
C91031
2
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
ATI M56 GPIO/DVO/Misc
91 104
D051-7099
=PPVCORE_S0_GPU
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
VOLTAGE=1.2V
PPVCORE_S0_GPU_MPVDD
=PP2V5_S0_GPU_PVDD
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
VOLTAGE=2.5V
PP2V5_S0_GPU_PVDD_F
=PP1V2_S0_GPU_VDDPLL
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
VOLTAGE=1.2V
PP1V2_S0_GPU_VDDPLL
=PP1V8R3V3_S0_GPU_VDDR5
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
VOLTAGE=3.3V
PP1V8R3V3_S0_GPU_VDDR5_F
=PP1V8R3V3_S0_GPU_VDDR4
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
VOLTAGE=3.3V
PP1V8R3V3_S0_GPU_VDDR4_F
GPU_GPIO_4GPU_GPIO_24
ATI_VREFG
=PP3V3_S0_GPU
ATI_TESTEN
GPU_GPIO_23GPU_GPIO_22
GPU_GPIO_28
GPU_GPIO_18
GPU_VARY_BLGPU_DIGON
GPU_GENERICDGPU_GENERICCGPU_GENERICBGPU_GENERICA
ATI_DVPDATA<22>ATI_DVPDATA<23>
ATI_DVPDATA<20>ATI_DVPDATA<21>
ATI_DVPDATA<17>ATI_DVPDATA<18>
ATI_DVPDATA<16>
ATI_DVPDATA<14>ATI_DVPDATA<15>
ATI_DVPDATA<12>ATI_DVPDATA<13>
ATI_DVPDATA<11>ATI_DVPDATA<10>
ATI_DVPDATA<8>ATI_DVPDATA<9>
ATI_DVPDATA<6>ATI_DVPDATA<7>
ATI_DVPDATA<5>
ATI_DVPDATA<3>ATI_DVPDATA<4>
ATI_DVPDATA<1>
ATI_DVPCNTL<2>ATI_DVPCNTL<1>ATI_DVPCNTL<0>
ATI_DVPCLK
GPU_GPIO_29
GPU_GPIO_34
TP_ATI_ROMCS_L
ATI_TDIODE_N
GPU_GPIO_19GPU_GPIO_20GPU_GPIO_21
GPU_GPIO_26GPU_GPIO_25
GPU_GPIO_32GPU_GPIO_33
GPU_GPIO_3
GPU_GPIO_5GPU_GPIO_6GPU_GPIO_7
GPU_GPIO_9GPU_GPIO_10GPU_GPIO_11GPU_GPIO_12GPU_GPIO_13GPU_GPIO_14GPU_GPIO_15
GPU_GPIO_17GPU_GPIO_16
GPU_XTALINGPU_XTALOUT
GPU_GPIO_27
GPU_GPIO_2GPU_GPIO_1GPU_GPIO_0
ATI_TDIODE_P
ATI_DVPDATA<2>
ATI_DVPDATA<19>
ATI_DVPDATA<0>
GPU_GPIO_8
GPU_GPIO_31GPU_GPIO_30
=PP2V5_S0_GPU_VDDC_CT
=PP2V5_S0_GPU_VDD25
=PP3V3_S0_GPU_VDDR3
GND_GPU_PVSS
VOLTAGE=0V
MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm
GND_GPU_MPVSS
VOLTAGE=0V
MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm
67
69
63
66
51
63
63
63
63
69 69
63
69
69
69
69
74
74
66
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
50
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
50
69
69
69
69
69
69
63
63
63
DDC3DATA
DDC3CLK
DDC2DATA
DDC2CLK
DDC1DATA
DDC1CLK
TXOUT_L3N
TXOUT_L3P
TXOUT_L2N
TXOUT_L2P
TXOUT_L1N
TXOUT_L1P
TXOUT_L0N
TXOUT_L0P
TXCLK_LP
TXCLK_LN
TXOUT_U3N
TXOUT_U2N
TXOUT_U3P
TXOUT_U2P
TXOUT_U1N
TXOUT_U1P
TXOUT_U0N
TXOUT_U0P
TXCLK_UN
TXCLK_UP
COMP
C
Y
V2SYNC
H2SYNC
B2
G2
R2
VSYNC
HSYNC
B
G
R
TX2M
TX2P
TX1M
TX0M
TX1P
TX0P
TXCM
HPD1
LPVSS
LPVDD
R2SET
VDD2DI
VSS2DI
A2VSSQ
NC_A2VDDQ
VSS1DI
RSET
AVSSQ
VDD1DI
TXCP
TPVSS
TPVDD
TX3P
TX3M
TX4P
TX4M
TX5P
TX5M
A2VSS
A2VDD(2.5V)
AVSS
(2.5V)AVDD
TXVSSR
IDENTIFICATION
(5 OF 7)
LVDDR
LVSSR
DAC (CRT)
DAC2 (TV/CRT2)
LVDS
MONITOR
TXVDDR
(2.5V)
(2.5V)
(2.5V)
(2.5V)
(2.5V)
(2.5V)
INTEGRATED TMDS
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Page Notes
Sum of peak currents on this page: 605mA
Power aliases required by this page:
Signal aliases required by this page:
20mA peak
Composite/S-Video VGA Component
Y G YC R Pr
Comp B Pb
200mA peak
65mA peak
150mA peak
NC
BOM options provided by this page:
(NONE)
(NONE)
- =PP2V5_S0_GPU- =PP1V8R2V5_S0_GPU_LVDDR
130mA peak
20mA peak
20mA peak
20mA peak
BGAM56P
OMIT
U8400
AL16
AM16
AL17
AM17
AK13
AL25
AM25
AJ24
AK25
AK23AL24
AL15
AJ13
AH15
AH23
AH22
AG13
AH13
AF12
AE12
AM24
AM15
AF15
AF11
AJ23
AE19
AE18
AC21
AC22
AD21
AD22
AE20
AE21
AE22
AF19
AF20
AF17
AF18
AF21
AF22
AG17
AG19
AH17
AH19
AJ19
AK17
AL14
AK24
AK15
AK14
AL22
AM8
AL8
AK10
AL10
AL11
AM11
AL12
AM12
AK9
AJ9
AK11
AJ11
AK12
AJ12
AL18
AM18
AK21
AJ21
AL9
AM9
AK19
AL19
AL20
AM20
AL21
AM21
AK18
AJ18
AH18
AG18
AJ20
AK20
AH20
AG20
AG21
AH21
AJ6
AK6
AL6
AM6
AJ7
AK7
AK8
AL7
AM7
AG15
AM23
AJ16
AL23
AJ17
AJ22
AJ15
1/16W1%
402MF-LF
499R93501
2
0.1uF
X5R402
10%16V
C93461
2
0.1uF
X5R402
10%16V
C93421
26.3V
402CERM
1uF10%
C93411
2
0402
FERR-220-OHML9300
1 2
1uF
CERM
10%6.3V
402
C93011
2
1uF
CERM402
10%6.3V
C93061
2
0402
FERR-220-OHML9305
1 2
10%
402X5R
0.1uF16V
C93071
2
0402
FERR-220-OHML9330
1 2
6.3V10%
402CERM
1uFC93311
2
SMXW93451 2
SMXW93301 2
X5R402
10%0.1uF16V
C93221
2
1uF
402
10%
CERM6.3V
C93211
2
0402
FERR-220-OHML9320
1 2
SMXW93201 2
10%
402X5R
0.1uF16V
C93121
26.3V10%
CERM
1uF
402
C93111
2
0402
FERR-220-OHML9310
1 2
SMXW93101 2
SMXW93051 2
SMXW93001 2
SMXW93141 2
SMXW93241 2
16V10%
X5R
0.1uF
402
C93171
2402CERM6.3V10%1uFC93161
2
16V10%
402X5R
0.1uFC93271
26.3V
402CERM
10%1uFC93261
2
0402
FERR-220-OHML9325
1 2
0402
FERR-220-OHML9315
1 2
0402
FERR-220-OHML9345
1 2
0.1uF
X5R402
10%16V
C93471
220%
6.3VCERM805
22UFC9340 1
220%
6.3VCERM805
22UFC9345 1
2
6.3V10%
402CERM
1uFC93321
2
1uF
CERM
10%
402
6.3V
C93021
26.3VCERM805
22UF20%
C9300 1
2
22UF
805CERM6.3V20%
C9305 1
2
20%6.3VCERM805
22UFC9310 1
2
22UF
805CERM6.3V20%
C9315 1
2
20%
CERM
22UF
805
6.3V
C9320 1
2
CERM6.3V20%
22UF
805
C9325 1
2
20%6.3V
805
22UF
CERM
C9330 1
2
715
MF-LF402
1%1/16W
R93511
2
93 104
D051-7099
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
ATI M56 Video Interfaces
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.35 mm
VOLTAGE=2.5V
PP2V5_S0_GPU_LVDDR
GND_GPU_LVSSR
VOLTAGE=0V
MIN_LINE_WIDTH=0.35 mmMIN_NECK_WIDTH=0.25 mm
=PP2V5_S0_GPU
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmPP2V5_S0_GPU_LPVDD
VOLTAGE=2.5V
PP2V5_S0_GPU_VDD2DIMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
VOLTAGE=2.5V
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.3 mm
VOLTAGE=2.5V
PP2V5_S0_GPU_A2VDD
PP2V5_S0_GPU_VDD1DIMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
VOLTAGE=2.5V
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmPP2V5_S0_GPU_AVDD
VOLTAGE=2.5V
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.3 mmPP2V5_S0_GPU_TXVDDR
VOLTAGE=2.5V
PP2V5_S0_GPU_TPVDDMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
VOLTAGE=2.5V
VOLTAGE=0V
GND_GPU_TPVSSMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm
TMDS_DATA_P<0>
TMDS_DATA_P<1>
TMDS_DATA_P<2>
TMDS_DATA_P<3>
TMDS_DATA_P<4>
TMDS_DATA_P<5>
TMDS_CLK_P
VOLTAGE=0V
GND_GPU_A2VSSQMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.25 mm
GPU_H2SYNC
VOLTAGE=0V
GND_GPU_A2VSSNMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
GND_GPU_AVSSQMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
GPU_DDC_C_DATAGPU_DDC_C_CLK
LVDS_L_CLK_N
LVDS_U_DATA_P<2>LVDS_U_DATA_N<2>
ATI_R2SETATI_RSET
GPU_DDC_A_DATA
GPU_DDC_B_CLKGPU_DDC_B_DATA
GPU_DDC_A_CLK
LVDS_L_DATA_N<3>LVDS_L_DATA_P<3>
LVDS_L_DATA_P<2>LVDS_L_DATA_N<2>
LVDS_L_DATA_N<1>
TMDS_DATA_N<3>
TMDS_DATA_N<4>
TMDS_DATA_N<5>
TMDS_DATA_N<2>
TMDS_DATA_N<1>
TMDS_DATA_N<0>
TMDS_CLK_N
LVDS_U_DATA_N<0>LVDS_U_DATA_P<0>
LVDS_U_CLK_NLVDS_U_CLK_P
GPU_VGA_HSYNCGPU_VGA_VSYNC
LVDS_L_DATA_N<0>LVDS_L_DATA_P<1>
LVDS_L_DATA_P<0>
LVDS_L_CLK_P
LVDS_U_DATA_P<1>LVDS_U_DATA_N<1>
LVDS_U_DATA_P<3>LVDS_U_DATA_N<3>
GPU_HPD
ATI_RSET
ATI_R2SET
VOLTAGE=0V
GND_GPU_AVSSNMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
GPU_V2SYNC
GPU_B2GPU_G2GPU_R2
GPU_VGA_BGPU_VGA_GGPU_VGA_R
GPU_TV_Y
GPU_TV_COMP
VOLTAGE=0V
GND_GPU_LPVSSMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm
GPU_TV_C
GND_GPU_TXVSSR
VOLTAGE=0V
MIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.25 mm
79
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79
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79
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75
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75
75
77
77
77
77
77
77
75
75
75
75
75
75
75
77
77
77
77
77
77
77
77
77
77
75
75
75
63
74
74
74
74
74
74
74
75
74
74
74
74
74
73
73
75
69
69
75
69
69
74
74
74
74
74
74
74
74
74
74
74
74
74
74
69
69
74
74
74
74
74
74
69
69
75
73
73
75
74
74
74
69
69
69
69
69
69
G
D
S
N-CHN
S
D
G
P-CHN
G
DS
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
LCD (LVDS) INTERFACE
no-panel case (development)
INVERTER EXPECTS ACTIVE HIGH PWM SIGNAL
518S0289
518S0293
NCPanel has 2K pull-ups
100K pull-ups are for
NET_TYPE
NC
NC
INVERTER INTERFACE
PHYSICALELECTRICAL_CONSTRAINT_SET SPACING
100K
MF-LF402
5%1/16W
R94501
2
0.001uF
CERM402
20%50V
C9454 1
2
50V20%
402CERM
0.001uFC94521
2
CERM
0.001uF50V20%
402
C94501
2
10UF
X5R603
20%6.3V
C9451 1
2
SM
FERR-1K-OHM-EMIL9450
1 2
SM-1
400-OHM-EMIL9454
1 2
10V20%
402CERM
0.1uF
INVERTER_BUFC9453 1
2
SM-1
400-OHM-EMIL9452
1 2
0.001uF
CERM
20%50V
402
C9420 1
2
1/16W5%
402MF-LF
100KR94101
2
402
0.001uF
CERM
20%50V
C9410 1
2
1/16W5%
402MF-LF
100KR94111
2
0.001uF
20%
CERM402
50V
C942112
MSC-RB30-5-FAF-RT-SM
CRITICALJ9400
33
34
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
4
5
6
7
8
9
SM60-OHM-EMI
L9455
1
2
0.001uF
402
20%50VCERM
C94551
2
0.001uF
CERM
20%50V
402
C9401 1
2
SM
FERR-250-OHML940050V
CERM
0.0022uF
10%
402
C94001 2
100K
MF-LF402
1/16W5%
R9401MF-LF
402
5%1/16W
100KR94001
2
SI3443DVTSOP-LF
Q9400
12563
4
2N7002SOT23-LF
Q94013
1
2
5%1/16WMF-LF
402
10KR94891
2
100K
402MF-LF1/16W
5%
R94941
2
INVERTER_UNBUF
5%1/16W
402
0
MF-LF
R94961 2
MC74VHC1G08SC70
INVERTER_BUF
U9453
3
2
1
4
5
SM-2MT-LF
CRITICAL
J94505
6
1
2
3
4
SC70-6FDG6332C_NLQ9450
6
2
1
SC70-6FDG6332C_NLQ9450
3
5
4
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
94 104
D051-7099
Internal Display Connectors
GND_INVERTERMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=0V
PP5V_INVERTER_SWMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=5V
GPU_DDC_C_DATA
GPU_B2VGA VGA
GPU_G2VGA VGA
GPU_R2VGA VGA
LVDS_U_DATA_N<2..0>LVDS LVDS
LVDS_U_DATA_P<2..0>LVDS LVDS
LVDS_U_CLK_NLVDSLVDS
LVDS_U_CLK_PLVDSLVDS
LVDS_L_DATA_N<2..0>LVDSLVDS
LVDS_L_DATA_P<2..0>LVDS LVDS
LVDS_L_CLK_NLVDS LVDS
LVDS_L_CLK_PLVDSLVDS
TMDS_DATA_P<5..3>TMDS TMDSTMDS_DATA_N<5..3>TMDS TMDS
TMDS_DATA_N<2..0>TMDS TMDS
TMDS_DATA_P<2..0>TMDS TMDS
TMDS_CLK_NTMDS TMDS
TMDS_CLK_PTMDS TMDS
LVDS_L_DATA_CONN_N<2..0>LVDS LVDS
LVDS_L_DATA_CONN_P<2..0>LVDSLVDS
LVDS_L_CLK_CONN_NLVDSLVDS
LVDS_L_CLK_CONN_PLVDS LVDS
LVDS_U_DATA_CONN_N<2..0>LVDSLVDS
LVDS_U_DATA_CONN_P<2..0>LVDSLVDS
LVDS_U_CLK_CONN_NLVDS LVDS
LVDSLVDS LVDS_U_CLK_CONN_P
LVDS_U_CLK_CONN_PLVDS_U_CLK_CONN_N
LVDS_U_DATA_CONN_P<2>LVDS_U_DATA_CONN_N<2>
LVDS_U_DATA_CONN_P<1>LVDS_U_DATA_CONN_N<1>
LVDS_U_DATA_CONN_P<0>
LVDS_L_DATA_CONN_N<1>LVDS_L_DATA_CONN_P<1>
LVDS_L_DATA_CONN_N<2>LVDS_L_DATA_CONN_P<2>
LVDS_L_CLK_CONN_PLVDS_L_CLK_CONN_N
LVDS_U_DATA_CONN_N<0>
LVDS_L_DATA_CONN_N<0>LVDS_L_DATA_CONN_P<0>
=PP3V3_S0_DDC_LCD
GPU_DDC_C_CLK
GPU_VARY_BL
=PP3V3_S0_INVERTER
INVERTER_PWM_F
=GND_CHASSIS_INVERTER
=PPBUS_S0_INVERTER
=PP3V3_S0_LCD
LCD_PWREN_L
GPU_DIGON
LCD_PWREN_L_RC
VOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPP3V3_LCD_SW
=GND_CHASSIS_LCD1
PP3V3_LCD_CONNMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=3.3V
=GND_CHASSIS_LCD4
=GND_CHASSIS_LCD3
VOLTAGE=12.8V
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
PPBUS_S0_INVERTER
FP_PWR_EN_L
GPU_BLON
PP5V_INVERTER_SW_FMIN_LINE_WIDTH=0.5 mm
VOLTAGE=5VMIN_NECK_WIDTH=0.25 mm
=PP5V_S0_INVERTER
=GND_CHASSIS_LCD2
INVERTER_PWM
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63
73
72
63 6
63
63
72
6
6
6
69
63
6
G
SD
G
SD
G
SD
LCFILTER
LCFILTER
LCFILTERSYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TMDS FilteringPlace series R’s and common-mode filtering close to GPU, common mode chokes near connector.
(DAC2 Comp)
(DAC2 Y)
(DAC2 C)
PLACE CLOSE TO CONNECTORANALOG FILTERING
PLACE U9750 & U9751 CLOSE TO DVI CONNECTOR
VGA SYNC BUFFERS
DVI INTERFACEDVI DDC CURRENT LIMIT
3V LEVEL SHIFTERS
(55mA requirement per DVI spec)
PHYSICAL
NET_TYPE
SPACINGELECTRICAL_CONSTRAINT_SET
Isolation required for DVI power switch
(PP5V_S0_DDC)
PLACE NEAR C5A & C5B
PLACE NEAR 3, 11 & 19
514-0278
1/16W5%
MF-LF
10K
402
R97211
2
1/16W5%
402MF-LF
10KR97201
2
SOT-3632N7002DW-X-F
Q9711
6
2
1
SOT-3632N7002DW-X-F
Q9711
3
5
4
1/16W5%
402MF-LF
100KR97221
2
50V5%
402CERM
100pFC97131
2
4.7K
MF-LF402
5%1/16W
R97121
2
1/16W5%
402MF-LF
4.7KR97101
2
100pF
CERM402
5%50V
C97111
2
0.01uF
CERM603
20%50V
C9710 1
2
400-OHM-EMI
SM-1
L9710
1 2
SOT-3632N7002DW-X-F
Q9714
3
5
4
CRITICAL
0.5AMP-13.2V
SM-LF
F97101 2
B0530WXF
SOD-123D97101 2
402
100pF
CERM
5%50V
C97141
2
MF-LF402
5%1/16W
100R97111 2
MF-LF402
5%1/16W
100R97131 2
MF-LF402
5%1/16W
100R97141 2
0
MF-LF402
5%1/16W
R973012
0
MF-LF
5%1/16W
402
R973112
3.3pF
CERM402
0.25%50V
C97411
2
1/16W1%
402MF-LF
75R97421
2
1/16W1%
402MF-LF
75R97401
2
1/16W1%
402MF-LF
75R97411
2
3.3pF
CERM402
0.25%50V
C97421
2
3.3pF
CERM402
0.25%50V
C97401
2
CRITICAL
SM-220MHZ-LF
FL9740
1 2
3 4
SM-220MHZ-LF
CRITICAL FL9741
1 2
3 4
CRITICAL
SM-220MHZ-LF
FL9742
1 2
3 4
CRITICAL
90-OHM-300mA2012H
L9702
1
2 3
4
CRITICAL
90-OHM-300mA2012H
L9701
1
2 3
4
33
5%1/16WMF-LF402
R97501 2
1/16W5%
402MF-LF
33R97511 2
90-OHM-300mA2012H
CRITICAL
L9703
1
2 3
4
90-OHM-300mA2012H
CRITICAL
L9704
1
2 3
4
CRITICAL
90-OHM-300mA2012H
L9705
1
2 3
4
90-OHM-300mA2012H
CRITICAL
L9700
1
2 3
4
QH11121-RIG02-4FF-RT-TH-DVI
CRITICALJ9700
C1
C2
C3
C4
C5AC5B
31
32
33
34
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
3
4
5
6
7
8
9
5%1/16WMF-LF
402
20KR97151
2
1%1/16W
402MF-LF
182R97861
2
5%1/16WMF-LF
0
402
R97851 2
5%1/16WMF-LF
0
402
R97841 2
402MF-LF1/16W
1%182
R97821
2
0
402MF-LF1/16W5%
R97801 2
5%1/16WMF-LF402
0R97811 2
0
402MF-LF1/16W5%
R97771 2
5%1/16WMF-LF402
0R97761 2
1%1/16WMF-LF
402
182R97781
2
402MF-LF1/16W
1%90.9
R97751
2
1%1/16WMF-LF402
90.9R97741
2
402
0
MF-LF1/16W5%
R97731 2
5%
402
0
MF-LF1/16W
R97721 2
10%50VCERM402
0.001uFC9774
1 2
1%1/16WMF-LF
402
182R97701
2
5%
MF-LF402
0
1/16W
R97691 2
5%
402
0
MF-LF1/16W
R97681 2
MF-LF1/16W
1%
402
182R97661
2
5%1/16WMF-LF
0
402
R97651 2
402
0
MF-LF1/16W5%
R97641 2
5%1/16WMF-LF402
0R97611 2
0
402MF-LF1/16W5%
R97601 2
CRITICAL
SM370-OHML9706
1
2 3
4
402
0.1uF10V20%
CERM
C9751 1
2
0.1uF
402CERM10V20%
C9750 1
2
SC70MC74VHC1G08
U9750
3
2
1
4
5
SC70MC74VHC1G08
U9751
3
2
1
4
5
402
1/16WMF-LF
1821%
R97621
2
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
External Display Connector
051-7099 D
10497
=GND_CHASSIS_DVI1
=GND_CHASSIS_DVI5=GND_CHASSIS_DVI3
TMDS_DATA_F_P<0>
TMDS_DATA_F_N<2>TMDS_DATA_F_N<1>
TMDS_DATA_F_P<1>
DVI_DDC_CLK_R
DVI_DDC_DATA_R
VGA_VSYNC
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmVOLTAGE=5VPP5V_S0_DDC
TMDS_DATA_F_P<3>
TMDS_DATA_F_N<0>
TMDS_DATA_F_P<4>TMDS_DATA_F_N<3>TMDS_DATA_F_N<4>
TMDS_DATA_F_P<2>
VGA_G
VGA_R
=GND_CHASSIS_DVI4
DVI_HPD_R
TMDS TMDS TMDS_DATA_R_N<5..0>
TMDS_CLK_R_PTMDS TMDS
=PP5V_S0_DVI_DDC
PP5V_S0_DDC_PULLUPSVOLTAGE=5VMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
=GND_CHASSIS_DVI2
PP5V_S0_DDC_FVOLTAGE=5VMIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.25 mm
DVI_HPD
DVI_DDC_CLK
DVI_DDC_DATA
TMDS_CLK_F_P
TMDS_CLK_F_N
VGA_B
VGA_HSYNC
TMDS_DATA_F_N<5>
TMDS_DATA_F_P<5>
=PP3V3_S0_DDC_DVI
TMDS_DATA_F_P<0>
TMDS_DATA_F_N<0>
TMDS_DATA_F_P<1>
TMDS_DATA_F_N<1>
TMDS_DATA_F_P<2>
TMDS_DATA_F_N<2>
TMDS_CLK_F_P
TMDS_CLK_F_N
TMDS_CLK_CMF
TMDS_CLK_R_N
TMDS_CLK_R_P
TMDS_DATA_F_P<3>
TMDS_DATA_F_N<3>
TMDS_DATA_F_N<4>
TMDS_DATA_F_P<4>
=PP3V3_S0_VGASYNC
=PP3V3_S0_VGASYNC
GPU_H2SYNC
GPU_V2SYNC
VGA_HSYNC_R VGA_HSYNC
VGA_VSYNC_R VGA_VSYNC
TMDSTMDS TMDS_DATA_R_P<5..0>
TMDS TMDS TMDS_CLK_R_N
TMDS_DATA_F_N<5..0>TMDSCONNTMDSCONN
TMDS_DATA_F_P<5..0>TMDSCONN TMDSCONN
TMDS_CLK_F_PTMDSCONNTMDSCONNTMDS_CLK_F_NTMDSCONNTMDSCONN
VGA_B
VGA_G
VGA_R
GPU_B2
GPU_G2
GPU_R2
GPU_DDC_A_CLK
GPU_DDC_A_DATA
GPU_HPD
TMDS_DATA_F_P<5>
TMDS_DATA_F_N<5>
TMDS_DATA_N<0>
TMDS_DATA_P<0>
TMDS_DATA_N<1>
TMDS_DATA_P<1>
TMDS_DATA_N<2>
TMDS_DATA_P<2>
TMDS_DATA_R_P<0>
TMDS_DATA_R_N<1>
TMDS_DATA_R_P<1>
TMDS_DATA_R_N<2>
TMDS_DATA_R_P<2>
TMDS_DATA_N<3>
TMDS_DATA_P<3>
TMDS_DATA_N<4>
TMDS_DATA_P<4>
TMDS_DATA_N<5>
TMDS_DATA_P<5>
TMDS_DATA_R_N<3>
TMDS_DATA_R_P<3>
TMDS_DATA_R_N<4>
TMDS_DATA_R_P<4>
TMDS_DATA_R_N<5>
TMDS_DATA_R_P<5>
TMDS_CLK_N
TMDS_CLK_P
TMDS_DATA_R_N<0>79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
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79
79
79
79
79
79
79
79
79
79
79
79
75
75
79
79
79
79
74
74
74
79
79
74
74
74
74
74
74
74
74
74
74
74
74
74
74
6
75
75
75
75
75
75
75
75
75
75
75
75
75
6
75
75
63
6
75
75
75
75
75
75
63
75
75
75
75
75
75
75
75
75
75
75
75
75
75
63
63
73
73
75
75
75
75
75
75
75
75
75
75
75
73
73
73
73
73
73
75
75
73
73
73
73
73
73
75
75
75
75
75
73
73
73
73
73
73
75
75
75
75
75
75
73
73
75
IO
IO
IN
OUT
SYM_VER-1
IN
INOUT
OUT
SYM_VER-1
IO
IO
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Bluetooth (M13P), IR & SATA HDD Flex Connector
518S0395
are to remove this noise from SATA signals.up significant noise. Common-mode chokesNOTE: _UF_ nets cross DDR2 signals and pick
NC
NC
516S0412
Left ALS Connector
FH19-4S-0.5SH-48
CRITICAL
F-RT-SM
J6430
5
6
1
2
3
4
CRITICALPLACEMENT_NOTE=Place FL4960 close to J4960
90-OHM-300mA2012H
FL4960
1
2 3
4
0.0047uF
10%
CERM25V
402
PLACEMENT_NOTE=Place C4960 close to southbridge
C49601 2
25VCERM
0.0047uF
402
10%
PLACEMENT_NOTE=Place C4961 next to C4960
C49611 2
PLACEMENT_NOTE=Place FL4965 close to southbridgeCRITICAL
2012H90-OHM-300mAFL4965
1
2 3
4
PLACEMENT_NOTE=Place C4965 close to J4960
402
25VCERM
0.0047uF
10%
C49652 1
PLACEMENT_NOTE=Place C4966 next to C4965
25VCERM
10%
402
0.0047uFC4966
2 1
CRITICAL
M-ST-SMQT500206-L020
J4960
1
10
11 12
13 14
15 16
17 18
19
2
20
3 4
5 6
7 8
9
M1 Specific Connectors
051-7099 D
10498
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
=PP3V3_S3_LTALS
SATA_C_R2D_C_NSATA_C_R2D_UF_N
SATA_C_R2D_C_PSATA_C_R2D_UF_P
SATA_C_R2D_NSATA_C_R2D_P
=USB_BT_N=USB_BT_P
=USB_IR_N=USB_IR_P
SYS_LED_ANODE
ALS_GAINLTALS_OUT
SATA_C_D2R_C_NSATA_C_D2R_C_P
SATA_C_D2R_UF_PSATA_C_D2R_P
SATA_C_D2R_N
=PP5V_S0_HDD
=PP3V3_S3_BT=PP5V_S3_IR
SATA_C_D2R_UF_N
47
63
6
5
21
21
6
6
6
6
48
5
21
21
63
63
63
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
on LVDS signals when they should be 0V.the pump-up in the panel, though some voltage will still be seen
requirements. Resulting pump-up in LCD panel can cause startup
M56 part. Bias voltage is present on LVDS interface pins evenNOTE: These parts are to counter an invalid state caused by the
LVDS Interface Pull-downs
when they should be tri-stated to meet panel power sequence
and long-term reliability issues. Pull-down resistors reduce
SM-LF
LVDS_PD
5%1/16W
8.2KRP99001 8
SM-LF
LVDS_PD
1/16W5%
8.2KRP99021 8
SM-LF
LVDS_PD
1/16W5%
8.2KRP99023 6
SM-LF
LVDS_PD
5%1/16W
8.2KRP99024 5
SM-LF
LVDS_PD
1/16W5%
8.2KRP99032 7
SM-LF
LVDS_PD
5%1/16W
8.2KRP99031 8
SM-LF
LVDS_PD
1/16W5%
8.2KRP99033 6
SM-LF
LVDS_PD
5%1/16W
8.2KRP99034 5
SM-LF
LVDS_PD
1/16W5%
8.2KRP99002 7
SM-LF
LVDS_PD
5%1/16W
8.2KRP99004 5
SM-LF
LVDS_PD
1/16W5%
8.2KRP99003 6
SM-LF
LVDS_PD
1/16W5%
8.2KRP99012 7
SM-LF
LVDS_PD
5%1/16W
8.2KRP99011 8
SM-LF
LVDS_PD
1/16W5%
8.2KRP99013 6
SM-LF
LVDS_PD
5%1/16W
8.2KRP99014 5
SM-LF
LVDS_PD
5%1/16W
8.2KRP99022 7
051-7099 D
10499
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
LVDS Interface Pull-downs
LVDS_L_DATA_CONN_P<0>MAKE_BASE=TRUELVDS_L_DATA_P<0>
LVDS_L_DATA_CONN_N<0>MAKE_BASE=TRUELVDS_L_DATA_N<0>
LVDS_L_DATA_CONN_P<1>LVDS_L_DATA_P<1>MAKE_BASE=TRUE
LVDS_L_DATA_CONN_N<1>LVDS_L_DATA_N<1>MAKE_BASE=TRUE
LVDS_L_DATA_CONN_P<2>MAKE_BASE=TRUELVDS_L_DATA_P<2>
LVDS_L_DATA_CONN_N<2>MAKE_BASE=TRUELVDS_L_DATA_N<2>
LVDS_L_CLK_CONN_PLVDS_L_CLK_PMAKE_BASE=TRUE
LVDS_L_CLK_CONN_NLVDS_L_CLK_NMAKE_BASE=TRUE
LVDS_U_DATA_CONN_P<0>MAKE_BASE=TRUELVDS_U_DATA_P<0>
LVDS_U_DATA_CONN_N<0>MAKE_BASE=TRUELVDS_U_DATA_N<0>
LVDS_U_DATA_CONN_P<1>LVDS_U_DATA_P<1>MAKE_BASE=TRUE
LVDS_U_DATA_CONN_N<1>LVDS_U_DATA_N<1>MAKE_BASE=TRUE
LVDS_U_DATA_CONN_P<2>MAKE_BASE=TRUELVDS_U_DATA_P<2>
LVDS_U_DATA_CONN_N<2>MAKE_BASE=TRUELVDS_U_DATA_N<2>
LVDS_U_CLK_CONN_PLVDS_U_CLK_PMAKE_BASE=TRUE
LVDS_U_CLK_CONN_NLVDS_U_CLK_NMAKE_BASE=TRUE
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74 73
74 73
74 73
74 73
74 73
74 73
74 73
74 73
74 73
74 73
74 73
74 73
74 73
74 73
74 73
74 73
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
2006/03/03 - 4457801 - Added 128S0081 as alternate for 128S0061.
2006/02/09 - 4440116 - Restructured BOM for 3 CPU configs.
2006/01/26 - 4420815 - Changed 2x 128S0077 to 128S0068.
2006/02/13 - 4437189 - Changed R7757 to 1Mohm & R7770 to 100K.
2006/02/13 - 4420815 - Changed remaining 128S0077 to 128S0086.
(A.0.0)
2005/10/13 - 4247941 - Spacing/Physical rule updates to match latest board database.
(A.1.0)
(B.0.0)
DMS Checkin #07006
2005/10/10 - 4248911 - Sync with M38 & M42.
2005/08/28 - 4225369 - Changed ISL6269 PVCC aliases, added RC for 3.3V S5.
2005/08/28 - 4217535 - Added Left ALS FFC connector.
2005/08/27 - 4235213 - Changed R8305, R8310, R8315 to slow down FET RCs.
2006/02/09 - 4440116 - Pulled new schematic part number (051-7099).
2005/10/12 - 4298899 - Changed stuffing option to disable PLT_RST gating.
DMS Release #B000 (PVT BOM Update)
2005/10/11 - 4261313 - Updated SATA connector pinout to match latest flex.
(13.2.0)
2005/10/10 - 4214847 - Changed 0-ohm resistor to solder jumper.2005/10/10 - 4214493 - Cost reductions to GPU power supply circuitry.
2005/10/10 - 4232826 - Swapped Vtt RPAK functions to optimize layout.
2005/10/09 - 4235898 - Part moves & refdes changes to support sync with M9.
2005/08/27 - 4227325 - Removed S0 option for camera, now S3-only.
2005/08/27 - 4235401 - Moved a few pins at LIO BTB connector.
2005/08/27 - 4235208 - Changed value of R7707 to fix 2.5V S3 supply.
Changes from Proto Branch (DMS Release #04000):
2005/08/11 - 4214109 - Changed J4931 to proper 518S0342 part.
DMS Release #03000 (RFA #394758)
2006/02/09 - 4440116 - Updated BootROM / SMC part numbers.
2006/01/05 - 4362451 - Removed power jumpers and 0-ohm resistor.2006/01/05 - 4362451 - Restructured BOM tables to eliminate LeMenu.
2006/01/05 - 4394079 - Added BOMOPTION to SYS_ONEWIRE pull-up.
2006/01/03 - 4290282 - Removed BOM table, changed L9455 to 155S0002.2006/01/03 - 4347845 - Changed LVDS pull-downs from 10K to 8.2K.
2006/01/03 - 4375840 - Synced 1 page from mlb_dvt branch back to trunk.
2006/01/03 - 4391436 - Swapped N/P signal names on one portion of SATA_R2D.
2006/01/05 - 4362566 - Removed 920- number for thin PCB option.
2006/01/06 - 4362451 - Changed BOM options for production SMC, BootROM.
2005/10/14 - 4247941 - Restored NO_TEST properties, added EXPOSED_VIA properties.2005/10/17 - 4292633 - Changed remaining 10K NTCs to new 5% part.
DMS Release #08000-11000 (EVT releases)
2005/10/26 - 4310267 - Synced 4 pages from mlb_evt branch back to trunk.
2005/09/19 - 4247941 - GND line/neck/voltage properties updated per PCB request.
2006/01/03 - 4362451 - Changed SCH/PCB/BOM part descriptions for Rev A.
2005/12/12 - 4362451 - Added MAKE_BASE=TRUE to SMC 32KHz SUSCLK net.
2006/01/03 - 4362451 - Removed power jumpers and 0-ohm resistor.
2006/01/06 - 4402184 - Changed R7540 value for IMVP6 load-line improvement.2006/01/06 - 4362451 - Added System Block Diagram, updated Power Diagram.
2005/10/10 - 4247941 - Net property updates found via back-annotation.
2005/10/09 - 4272237 - Changed 2.5V S0 FET RC to 100K to slow down turn-on.
2005/10/08 - 4290735 - Swapped trackpad & PCIe Mini Card USB connections.
2005/10/08 - 4214493 - Simplified FireWire port power circuit for BOM consolidation.
DMS Checkin #070032005/10/07 - 4248911 - Sync with M38 & M42.
2005/08/27 - 4227369 - Removed SMC options for display/backlight, now GPU-only.
2005/08/27 - 4230219 - Changed Y3301 to non-obsoleted part.
2005/09/03 - 4244484 - Changed P1V5S0_RUNSS circuit to work properly in G3Hot.
2005/08/31 - 4240157 - Corrected pinout at SATA/BT conn (J4960) to match flex.
2005/08/30 - 4217535 - Removed BOM tables and OMITs for new 4-pin WTB connector.
(11.10.0) DMS Release #12000-13000 (DVT releases)2005/12/07 - 4375840 - Synced 4 pages from mlb_dvt branch back to trunk.
2005/10/08 - 4293072 - Various BOM / connection changes at IMVP6 (CPU VCore).
2005/10/07 - 4292633 - Changed IMVP6 10K NTC from 10% to 5% part.2005/10/07 - 4286888 - BOM restructuring per EVT build plan.
2005/10/04 - 4261313 - Deleted placeholder connector, grew HDD connector for IR.
2005/09/30 - 4274915 - C1001 stuffing change from Proto 2 MLB branch.
(11.8.0)
2005/08/29 - 4227336 - Changed Y5920 to 197S0169.2005/08/29 - 4227309 - Resolved sync issues with M38 (SB page 21).
2005/08/29 - 4227322 - Sync page 44 with M42 to fix FW power net S-states.
2005/12/02 - 4217524 - Updated part number for J6430.
2005/12/02 - 4256256 - Added BOMOPTION to R8801 to allow per-project control.
2005/10/12 - 4244539 - Retasked FET to control 3.3V S0 FET from GPU VCore PGOOD.
2005/10/21 - 4310267 - Synced 3 pages from mlb_evt branch back to trunk.
2005/11/15 - 4322537 - Updated thru-hole SO-DIMM connector part number.
2005/11/16 - 4235898 - Changed Yukon power rail neck widths per M9 request.
2005/11/16 - 4345921 - FUNC_TEST updates per test team request.2005/11/16 - 4227333 - Updated SMC net names per ERS v1.2.1.
2005/11/16 - 4235898 - Aliased connection to ALS_GAIN to support M9 request.
2005/09/20 - 4214847 - Updated L1970 (old part no longer exists in library).
(11.9.0)
2005/10/10 - 4229560 - Removed Physical Security circuitry.
2005/08/31 - 4227328 - Added ESD protection diode on right USB port.
2005/08/31 - 4237025 - Added R8824 and R8827 for GPU memory configuration straps.2005/08/31 - 4227315 - Changed BSA bus pull-ups from 2K to 10K.
DMS Checkin #11002
2005/11/22 - 4352020 - Changed 2.5V S3 supply inductor & compensation values.2005/11/28 - 4347845 - Added pull-down resistors on LVDS interface.2005/11/30 - 4227340 - Removed CPU VCore current sense input RC.
DMS Checkin #07007
2005/08/31 - 4227328 - Changed EMI caps from 50V to 16V to fid in ESD protection.
2005/09/03 - 4232534 - Added notes for power supplies and connectors.
DMS Checkin #040072005/09/06 - 4240486 - Removed NO_TEST property from GPU HSYNC and VSYNC.
2005/09/06 - 4232534 - Fixed label BOM tables to call out proper EEE #’s.
2005/08/12 - 4231030 - Changed pinout of J4960, added placement notes.
2005/10/17 - 4304248 - Updated GPU VCore / BBP voltages for B13/B24 support.
2005/11/16 - 4346006 - Updated J5500 pinout to match updated LIO board pinout.
(11.7.0)
2005/11/21 - 4351196 - Added 1K pull-down on IDE_RESET_L.(11.5.0) 2005/11/21 - 4343202 - Changed RC value and net name for USB OC.
2005/08/31 - 4240150 - Swapped PCIE Mini Card R2D/D2R connections at J5500.
(11.4.0)
2005/11/15 - 4310267 - Synced 5 pages from mlb_evt branch back to trunk.
2005/11/16 - 4235898 - Sync with M38 & M42.
2005/11/18 - 4235898 - Changed R4210 package size per M9 request.
2005/08/29 - 4217524 - Changed R6430 from 4.5K to 3.5K.2005/08/29 - 4232826 - Changed MEM_ODT* from RPAKs to discrete Rs.2005/08/29 - 4235179 - Changed J8200 to proper 6-pin part.
2005/08/29 - 4227335 - Changed U5900 to resolve ROHS issue.
2005/08/28 - 4232715 - Added FireWire ISense resistor, changed INA193 to INA194.
2005/09/19 - 4235898 - Moved signal alias to improve schematic reuse.
DMS Checkin #04005
DMS Checkin #04006
DMS Checkin #04003
DMS Checkin #04001
DMS Checkin #04004
DMS Checkin #04002
2005/08/29 - 4237119 - Changed LIO 5V S3 to 5V S5.
2005/08/29 - 4227312 - Resolved sync issues with M38 (SB page 23).
2005/09/16 - 4229560 - Changed FW PCI REQ/GNT pair for Physical Security.
2005/09/21 - 4234952 - Replaced FDG6324L parts with FDG6332C for cost & supply.
2005/09/26 - 4274915 - Thermal sensor BOM updates from Proto 2 MLB branch.
Date - Radar # - Description
2005/09/26 - 4274915 - U6301 part number updated to M1 development BootROM.
2005/09/21 - 4227306 - Changed CPU VCore caps to proper production part number.
2005/08/31 - 4232563 - Corrected net properties on R2/G2/B2 nets.
2005/08/27 - 4225433 - Changed PBUS voltage sense circuit.
2005/08/28 - 4217524 - Added LEFT ALS connector (J6430).
DMS Release #05000-07000 (Proto 2 releases)
2005/08/28 - 4235203 - Changed BOM settings to stuff R2251.
2005/10/11 - 4227308 - Deleted unnecessary MCH TVDAC filtering.
DMS Checkin #07004
DMS Checkin #07001
DMS Checkin #07002
2005/10/12 - 4223808 - Power supply changes per vendor feedback.
DMS Checkin #07008
2005/08/28 - 4217535 - OMITs and tables to change 4-pin WTB connector parts.
2005/08/28 - 4225369 - OMITs and tables for staged LeMenu BOM approach.
DMS Checkin #07005
2005/10/12 - 4298943 - Replaced last remaining non-RoHS compliant connector.
DMS Checkin #07009
2005/10/08 - 4286729 - Changed value of TPM Xtal caps.
2005/10/10 - 4295280 - Changed sleep LED connection per new SMC ERS.
2005/10/12 - 4248911 - Sync with M38 & M42.
2005/10/13 - 4247941 - Swapped pins at trackpad ESD protection diode.
2005/10/21 - 4235898 - Synced 2 pages from m9/mlb.
2005/08/28 - 4225433 - Changed PBUS Voltage Sense circuit.
2005/08/28 - 4235217 - Added RC on Q3820 gate to slow down ODD FET turn-on.
2005/08/28 - 4227323 - Repinned Top-Case Flex connector.
2005/08/29 - 4225369 - Changed 3.3V S5 sequence to follow 5V S5 PGOOD.
2005/08/29 - 4227310 - Resolved sync issues with M38 (SB page 22).
2005/08/29 - 4227332 - Resolved sync issues with M38 (SMC page 58).
2005/08/30 - 4225433 - Fixed voltage divider values in PBUS VSense circuit.
2005/09/02 - 4244019 - Moved GPU-related power alias from PP3V3_S0 to PP3V3_S0_GPU.
2005/09/08 - 4214493 - Combined RTC coin cell diodes into dual-diode package.
2005/09/03 - 4232534 - Fixed documentation of battery address on I2C page.
2005/09/08 - 4247941 - Net property & name changes to support PCB/ICT requests.
2005/10/13 - 4247941 - Removed NO_TEST properties from CPU FSB strobe signals.
2005/10/13 - 4247941 - Unswapped pins at trackpad ESD protection diode.
2005/08/31 - 4240486 - Power line width & neck reductions at PCB request.2005/08/31 - 4240300 - Changed C6455 to a smaller part for cost & MCO.
2005/09/02 - 4241087 - Fixed pinout of USB D+/D- at camera connector to match FHB.
2005/10/12 - 4227320 - Updated SB pin name for GPIO 5 (ODD_PWR_EN_L).
2005/11/15 - 4298899 - Removed unused platform reset gate.
2005/11/16 - 4345498 - Updated Ethernet & FireWire crystal part numbers.
2005/08/31 - 4227306 - Swapped primary & alt part numbers for CPU VCore caps.
2005/08/31 - 4223808 - Various power supply R/C updates, plus some R/C adds.
2005/08/31 - 4214109 - Reversed pinout of J4931 to match updated PCB footprint.
2005/09/02 - 4243269 - Inverted GPU VCore control, adjusted supply R values.
2005/09/03 - 4244539 - Added GPUVCORE_PGOOD to 1.2V, 1.8V, & 2.5V S0 sequence.
2005/11/16 - 4346184 - Inserted common-mode chokes on SATA R2D/D2R pairs.
(11.2.0)(11.1.0)
2005/11/18 - 4235898 - Changed C9710 GND connection per M9 request.
2005/11/16 - 4298899 - Fixed ethernet reset net name on page 26.
DMS Checkin #11001
2005/09/30 - 4261313 - Added placeholder connector for IR FFC connector.
2005/11/03 - 4310267 - Synced 6 pages from mlb_evt branch back to trunk.
(11.3.0)
2005/10/20 - 4310267 - Synced 4 pages from mlb_evt branch back to trunk.
2005/10/06 - 4227330 - Added ESD protection on top-case USB port.
Date - Radar # - Description
2005/10/12 - 4298905 - Changed ethernet VMAIN_AVLBL connection.
2005/10/12 - 4297684 - Split FW323 VSSA from VSS to reduce noise.
2005/10/11 - 4229560 - Changed SB GNT3#/GNT4# back to test points.
2005/08/28 - 4235179 - Changed PBUS net names to merge PBUS A & PBUS B.2005/08/28 - 4235179 - OMIT and table to change 8-pin DC-In connector to 6-pin.2005/08/28 - 4227322 - Changed FW323 PCI_VIOS pin from 3.3V S0 to 3.3V S3.
2005/08/28 - 4221973 - Added pull-up for SB GPIO22 (REQ4#).
2005/08/28 - 4232563 - Changed analog video from Y/C/Comp to G2/R2/B2.
2005/09/03 - 4227315 - Changed SMBus pull-ups to 4.7K.
2005/09/02 - 4240486 - Adjusted line/neck widths, changed J4931 to 518S0371.
(11.6.0)2005/09/29 - 4232826 - Swapped Vtt RPAK functions to free up unnecessary part.
2005/11/30 - 4331670 - Added CRITICAL flags to some more parts.
2005/11/22 - 4350840 - Swapped TMDS termination components for placement.
2005/09/28 - 4221965 - Added 2.2uF caps on SO-DIMM VREF pins.2005/09/28 - 4278828 - Adjusted P5VS5_PGOOD R’s, added cap on PM_RSMRST_L.
2005/09/30 - 4282162 - Changed GPU BBN supply to MAX1673.
2005/09/30 - 4282349 - Added CRITICAL flags to parts identified in scrub.
2005/10/04 - 4256409 - Changed fan CTL series R’s to 2N7002 level-shifter.
2005/12/02 - 4363870 - Removed M1a support from BOM.
2005/09/30 - 4248911 - Sync with M38 & M42.
2005/11/30 - 4351181 - Changed ITP connector BOM option.2005/11/30 - 4351196 - Changed IDE_RESET_L pull-down from 1K to 15K.2005/11/30 - 4358831 - Added pull-downs on two SB-to-SMC signals.
2005/12/01 - 4352020 - Changed 2.5V supply inductor to RoHS-compliant part.2005/10/04 - 4281394 - BOM option change to stuff right USB ESD protection part.
2005/11/30 - 4343864 - Added EMI/ESD parts at camera connector.
2005/12/01 - 4362404 - Changed TMDS diff term from 100-ohm to 180-ohm.
2005/12/01 - 4227340 - Changed supply for 1.8V S3 current sense amp.2005/12/01 - 4362566 - Restructured BOM for thick/thin PCB versions.2005/12/01 - 4347845 - RPAK pinswaps to LVDS pull-downs for PCB layout.
DMS Checkin #11003
2005/12/12 - 4235898 - Changes to LVDS net names to support mux option.2005/10/09 - 4214494 - Changed GPU VCore supply enable to use 1.2V/2.5V S3 PGOODs.
Date - Radar # - Description
2005/12/02 - 4363848 - Removed M56 GPU die rev B13 support from BOM.
(13.1.0)
2005/09/26 - 4239505 - Updated J4200 (old part no longer exists in library).
2005/09/16 - 4256660 - Updated FUNC_TEST property for merged PBUS.2005/09/08 - 4229560 - First implementation of Physical Security Guidelines.
2005/09/08 - 4248911 - Sync with M38 & M42.
2005/09/06 - 4246683 - Removed NO STUFF option from R8805 per ATI request.
2005/08/31 - 4240257 - Swapped some top & bottom EMC connections at DVI connector.
2005/11/19 - 4340256 - Changed topcase flex trackpad power from 3.3V to 5V.
2005/11/19 - 4346184 - Fixed location of SATA R2D common-mode choke.
DMS Release #A000 (PVT Release)
2006/01/21 - 4414757 - Changed 138S0552 to 138S0580 & 138S0553 to 138S0581.2006/01/21 - 4412882 - Changed R7623 from 1.33K to 931 ohms.
2005/11/19 - 4292165 - Refreshed schematic symbol for U3750 (library update).
2005/11/19 - 4350840 - Simplified TMDS filtering to allow movement of filter.
2005/11/19 - 4350849 - Added option to connect SB_GPIO30 to ENET_LOM_DIS_L.2005/11/19 - 4229560 - Changed FW chip back to REQ/GNT3.
2005/11/19 - 4347717 - Changed SMS self-test pull-up to pull-down.
2005/11/16 - 4227333 - Fixed single-pin nets caused by SMC net name updates.
2005/11/16 - 4343202 - Changed USB overcurrent switch to TPS2051B, added OC* RC.
2005/10/12 - 4214493 - Consolidated 0.22uF caps in design.2005/10/12 - 4247941 - Added properties to resolve a PCB constraint issue.
(A.1.0)
DMS Release #A000 (Ramp Config Update)
(B.0.0)
2006/03/03 - 4457745 - Added 128S0094 & 128S0095 as alternates for 128S0060.
2005/10/12 - 4214494 - Implemented circuit to power down ethernet in S3 on battery.
2006/02/17 - 4449123 - Changed C7537: 4.7nF -> 47pF, R7537: 3.57K -> 4.42K.
DMS Release #B000 (PVT BOM Roll-In)2006/02/13 - 4431947 - Removed NO STUFF option from C3309.
2006/02/13 - 4420815 - Added 128S0077 as alternate for 128S0086.
2006/03/03 - 4466770 - Changed R7920 from 5% to 1% to reduce variation.2006/03/03 - 4399085 - Changed C7532 from 10nF to 15nF to slow CPU slew rate.2006/03/03 - 4424175 - Changed 8 VRAM strap resistors to enable ICT testing.
DMS Release #C000 (Ramp BOM Update)
DMS Release #D000 (Ramp BOM Update)
(C.0.0)
(D.0.0)
051-7099 D
104100
DSYNC_MASTER=N/A SYNC_DATE=N/A
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
ELECTRICAL_CONSTRAINT_SET SPACING
NET_TYPE
PHYSICAL
I70
I71
I72
I73
SYNC_DATE=(MASTER)
M1 Net Properties
051-7099 D
104104
SYNC_MASTER=(MASTER)
TMDS_DATA_F_N<2..0>TMDSCONNTMDSCONN
TMDS_DATA_F_N<5..3>TMDSCONNTMDSCONNTMDS_DATA_F_P<2..0>TMDSCONNTMDSCONN
TMDS_DATA_F_P<5..3>TMDSCONNTMDSCONN
TMDS_DATA_N<2..0>TMDSTMDS
TMDS_DATA_N<5..3>TMDSTMDSTMDS_DATA_P<2..0>TMDSTMDS
TMDS_DATA_P<5..3>TMDSTMDS
TMDS_CLK_F_PTMDSCONNTMDSCONNTMDS_CLK_F_NTMDSCONNTMDSCONN
FSB_LOCK_LFSB_COMMONFSB_55S
MEM_DQS MEM_85D
FB_CLK FB_75D
SATA SATA_100D
ENET ENET_100D
CPU_COMP<1>CPU_COMPCPU_55S
SMB SMB_55S
FSB_BPRI_LFSB_COMMONFSB_55S
CPU_XDP_CLK_NCPU_ITPCLK_FSB_100D
IMVP6_VSEN_PCPU_VCCSENSECPU_27P4S
CPU_INTRCPU_55S
FSB_ADSTB_L<3..0>FSB_ADSTBFSB_55S
FSB_D_L<63..0>FSB_DATAFSB_55S
FSB_DRDY_LFSB_COMMONFSB_55S
FSB_RS_L<2..0>FSB_COMMONFSB_55S
USB2 USB2_90D
FW FW_110D
CLK_FSB CLK_FSB_100D
FSB_TRDY_LFSB_COMMONFSB_55SFSB_CPURST_LFSB_COMMONFSB_55S
FSB_DBSY_LFSB_COMMONFSB_55S
FSB_DSTBP_L<3..0>FSB_DSTBFSB_55S
FSB_DINV_L<3..0>FSB_DATAFSB_55S
FSB_DSTBN_L<3..0>FSB_DSTBFSB_55S
CPU_COMP<2>CPU_COMPCPU_27P4S
CPU_COMP<3>CPU_COMPCPU_55S
CPU_GTLREFCPU_GTLREFCPU_55S
PM_DPRSLPVRCPU_2TO1CPU_55S
CPU_IGNNE_LCPU_55S
CPU_DPSLP_LCPU_55S
CPU_A20M_LCPU_55S
CPU_NMICPU_55S
CPU_PWRGDCPU_55S
IMVP_DPRSLPVRCPU_2TO1CPU_55S
FSB_FERR_LCPU_55S
FSB_A_L<31..3>FSB_ADDRFSB_55S
CPU_VCCSENSE_NTHERM CPU_VCCSENSECPU_27P4S
IMVP6_VSEN_NCPU_VCCSENSECPU_27P4S
CPU_COMP<0>CPU_COMPCPU_27P4S
CPU_XDP_CLK_PCPU_ITPCLK_FSB_100D
XDP_BPM_L<5..0>CPU_ITPCPU_55S
FSB_BREQ0_LFSB_COMMONFSB_55S
FSB_ADS_LFSB_COMMONFSB_55S
MEM_CMD MEM_55S
MEM_CLK MEM_70D
MEM_CTRL MEM_45S
MEM_DATA MEM_55S
CPU_SMI_LCPU_55S
CPU_INIT_LCPU_55S
FB_ADCTRL FB_55S
FB_ADCTRL FB_35S_TO_55S
FB_DATA FB_40S
DMI DMI_100D
FSB_IERR_LCPU_55S
CPU_THERMTRIP_LCPU_2TO1CPU_55S
FSB_HIT_LFSB_COMMONFSB_55S
IDE IDE_55S
CLK_PCIE CLK_PCIE_100D
CLK_MED CLK_MED_55S
SB_ACZ_RST_LAUDIOAUDIO_55SACZ_RST_LAUDIOAUDIO_55S
ACZ_SDATAOUTAUDIOAUDIO_55S
SB_ACZ_SDATAOUTAUDIOAUDIO_55S
ACZ_SDATAIN<0>AUDIOAUDIO_55S
ACZ_SYNCAUDIOAUDIO_55S
TMDS_CLK_NTMDSTMDS
SB_ACZ_SYNCAUDIOAUDIO_55S
FSB_DEFER_LFSB_COMMONFSB_55S
FSB_HITM_LFSB_COMMONFSB_55S
FSB_BNR_LFSB_COMMONFSB_55S
TMDS_CLK_PTMDSTMDS
PCIE PCIE_100D
TMDS TMDS_100D
LVDS LVDS_100D
VGA VGA_75S
CPU_STPCLK_LCPU_55S
FSB_REQ_L<4..0>FSB_ADDRFSB_55S
FSB_DPWR_LFSB_COMMONFSB_55S
SPI SPI_55S
CLK_SLOW CLK_SLOW_55S
ACZ_BITCLKAUDIOAUDIO_55S
SB_ACZ_BITCLKAUDIOAUDIO_55S
CPU_VCCSENSE_PTHERM CPU_VCCSENSECPU_27P4S
CPU_VID<6..0>CPU_2TO1CPU_55S
CPU_VID<6..0>CPU_2TO1CPU_55S
ITPRESET_LCPU_ITPCPU_55S
75
75
75
75
12
12
12
12
12
12
12
12
12
57
12
12
12
12
45
45
45
45
75
12
12
75
12
45
79
79
74
74
74
74
7
12
34
21
7
7
7
12
12
11
7
7
7
7
23
21
21
21
21
21
7
57
34
11
7
7
21
21
7
21
21
21
21
74
12
7
7
74
21
7
12
21
57
9
9
75
75
75
75
73
73
73
73
75
75
5
7
7
11
57
7
5
5
5
7
7
7
5
5
5
5
7
7
7
14
7
7
7
7
7
57
5
8
57
7
11
7
5
5
7
7
7
5
21
5
5
21
5
5
73
21
7
5
5
73
7
5
7
5
21
8
8
8
11