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(LRP)(MCA)(2012-13/ODD)(2012-2015)
MC9211– Computer Organisation
Unit 2: Combinational and Sequential
Circuits
Lesson 2 of 3 : Synchronous Sequential
Logic
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Sequential CircuitsSequential Circuits
Combinational
CircuitMemory
Elements
Inputs Outputs
�Asynchronous
�Synchronous
Combinational
Circuit
Flip-flops
Inputs Outputs
Clock
(LRP)(MCA)(2012-13/ODD)(2012-2015)
FlipFlip--FlopsFlops
�A flip-flop circuit can maintain a binary state
indefinitely until directed by an input signal to
switch states
�There are many types of flip-flops and the major
difference between them is the number of inputs
they posses and the manner they affect the output
�Basic flip-flop can be constructed with cross
coupled NOR or NAND gates
�Each flip-flop has two outputs Q (normal) and Q’
(complement) and two inputs set and reset
(LRP)(MCA)(2012-13/ODD)(2012-2015)
LatchesLatches
�SR LatchQ’
0 0 0
QS R Q0
0
1
0
0
10 Q = Q0
Initial Value
(LRP)(MCA)(2012-13/ODD)(2012-2015)
LatchesLatches
�SR Latch
1
Q’
0 0 1
00 0 0
QS R Q0
1
0
0
0
01 Q = Q0
Q = Q0
(LRP)(MCA)(2012-13/ODD)(2012-2015)
LatchesLatches
�SR Latch
0
1
Q’
00 1 0
10 0 1
00 0 0
QS R Q0
0
1
1
0
1 Q = 0
Q = Q0
(LRP)(MCA)(2012-13/ODD)(2012-2015)
LatchesLatches
�SR Latch
1
0
1
Q’
0 1 1
00 1 0
10 0 1
00 0 0
QS R Q0
1
0
1
0
10
Q = 0
Q = Q0
Q = 0
(LRP)(MCA)(2012-13/ODD)(2012-2015)
LatchesLatches
�SR Latch
1
1
0
1
Q’
1 0 0
00 1 1
00 1 0
10 0 1
00 0 0
QS R Q0
0
1
0
1
01
Q = 0
Q = Q0
Q = 1
(LRP)(MCA)(2012-13/ODD)(2012-2015)
LatchesLatches
�SR Latch
0
1
1
0
1
Q’
1 0 1
11 0 0
00 1 1
00 1 0
10 0 1
00 0 0
QS R Q0
1
0
0
1
01
Q = 0
Q = Q0
Q = 1
Q = 1
(LRP)(MCA)(2012-13/ODD)(2012-2015)
LatchesLatches
�SR Latch
0
0
1
1
0
1
Q’
1 1 0
11 0 1
11 0 0
00 1 1
00 1 0
10 0 1
00 0 0
QS R Q0
0
1
1
1
00
Q = 0
Q = Q0
Q = 1
Q = Q’
0
(LRP)(MCA)(2012-13/ODD)(2012-2015)
LatchesLatches
�SR Latch
0
0
0
1
1
0
1
Q’
1 1 1
01 1 0
11 0 1
11 0 0
00 1 1
00 1 0
10 0 1
00 0 0
QS R Q0
1
0
1
1
00
Q = 0
Q = Q0
Q = 1
Q = Q’
0
Q = Q’
(LRP)(MCA)(2012-13/ODD)(2012-2015)
LatchesLatches
�SR Latch
1 1
1 0
0 1
0 0
S R
Q=Q’=0
1
0
Q0
Q
No change
Reset
Set
Invalid
S
R
Q
Q1 1
1 0
0 1
0 0
S R
Q0
0
1
Q=Q’=1
Q
Invalid
Set
Reset
No change
(LRP)(MCA)(2012-13/ODD)(2012-2015)
LatchesLatches
�SR Latch
1 1
1 0
0 1
0 0
S R
Q=Q’=0
1
0
Q0
Q
No change
Reset
Set
Invalid
1 1
1 0
0 1
0 0
S’ R’
Q0
0
1
Q=Q’=1
Q
Invalid
Set
Reset
No change
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Controlled LatchesControlled Latches
�SR Latch with Control Input
Q01 0 0
1 1 1
1 1 0
1 0 1
0 x x
C S R
Q=Q’
1
0
Q0
Q
No change
No change
Reset
Set
Invalid
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Clocked RS FlipClocked RS Flip--FlopFlop
Logic Diagram
Characteristic Table
S
C
R
Q
Q’
Graphic Symbol
Characteristic Equation
Q( t + 1) = S + R’Q
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Clocked RS FlipClocked RS Flip--Flop (contd..)Flop (contd..)
� The clocked SR flip-flop consists of a basic NOR flip-flop and two AND gates
� The outputs of the two AND gates remain at 0 as long as the clock pulse (or CP) is 0, regardless of the S and R input values
�When the clock pulse goes to 1, information from the S and R inputs passes through to the basic flip-flop
�With both S=1 and R=1, the occurrence of a clock pulse causes both outputs to momentarily go to 0
�When the pulse is removed, the state of the flip-flop is indeterminate, ie., either state may result, depending on whether the set or reset input of the flip-flop remains a 1 longer than the transition to 0 at the end of the pulse
(LRP)(MCA)(2012-13/ODD)(2012-2015)
D FlipD Flip--FlopFlop
Logic Diagram with NAND gates
111
001
110
000
Q(t+1)DQ(t)
1
1
0 1
0
1
D
Q
Q (t + 1) = D
Characteristic
Equation
Characteristic Table
Graphic Symbol
(LRP)(MCA)(2012-13/ODD)(2012-2015)
D FlipD Flip--FlopFlop
�The D flip-flop is a modification of the clocked SR
flip-flop
�The D input goes directly into the S input and the
complement of the D input goes to the R input
�The D input is sampled during the occurrence of a
clock pulse
�If it is 1, the flip-flop is switched to the set state
(unless it was already set)
�If it is 0, the flip-flop switches to the clear state
(LRP)(MCA)(2012-13/ODD)(2012-2015)
J K FlipJ K Flip-- FlopFlop
1 1
1 1
00 01 11 10
0
1
Q
JK
Logic Diagram
Characteristic
Table
Characteristic Equation
Q( t + 1 ) = JQ’ + K’QGraphic Symbol
(LRP)(MCA)(2012-13/ODD)(2012-2015)
J K FlipJ K Flip--Flop (contd..)Flop (contd..)
�A JK flip-flop is a refinement of the SR flip-flop in
that the indeterminate state of the SR type is
defined in the JK type
�Inputs J and K behave like inputs S and R to set
and clear the flip-flop (note that in a JK flip-flop,
the letter J is for set and the letter K is for clear)
�When logic 1 inputs are applied to both J and K
simultaneously, the flip-flop switches to its
complement state, ie., if Q=1, it switches to Q=0
and vice versa
(LRP)(MCA)(2012-13/ODD)(2012-2015)
J K FlipJ K Flip--Flop (contd..)Flop (contd..)
�A clocked JK flip-flop is shown in previous slide
�Output Q is ANDed with K and CP inputs so that
the flip-flop is cleared during a clock pulse only if
Q was previously 1
�Similarly, ouput Q' is ANDed with J and CP inputs
so that the flip-flop is set with a clock pulse only if
Q' was previously 1
(LRP)(MCA)(2012-13/ODD)(2012-2015)
J K FlipJ K Flip--Flop (contd..)Flop (contd..)
�Note that because of the feedback connection in the
JK flip-flop, a CP signal which remains a 1 (while
J=K=1) after the outputs have been complemented
once, will cause repeated and continuous
transitions of the outputs
�To avoid this, the clock pulses must have a time
duration less than the propagation delay through
the flip-flop
�The restriction on the pulse width can be
eliminated with a master-slave or edge-triggered
construction
(LRP)(MCA)(2012-13/ODD)(2012-2015)
T FlipT Flip--FlopFlop
1
1
T
Q 0 1
0
1
Logic Diagram
Characteristic
Table
Characteristic Equation
Q(t+1) = TQ’ + T’QGraphic Symbol
(LRP)(MCA)(2012-13/ODD)(2012-2015)
T FlipT Flip--Flop (contd..)Flop (contd..)
�The T flip-flop is a single input version of the JK
flip-flop
�The T flip-flop is obtained from the JK type if both
inputs are tied together
�The output of the T flip-flop "toggles" with each
clock pulse
(LRP)(MCA)(2012-13/ODD)(2012-2015)
FlipFlip--FlopsFlops
�Controlled latches are level-triggered
�Flip-Flops are edge-triggered
C
CLK Positive Edge
CLK Negative Edge
(LRP)(MCA)(2012-13/ODD)(2012-2015)
MasterMaster--Slave FlipSlave Flip--FlopFlop
� A master-slave flip-flop is constructed from two separate flip-flops
� One circuit serves as a master and the other as a slave
� The logic diagram of an SR flip-flop is shown in next slide
� The master flip-flop is enabled on the positive edge of the clock pulse CP and the slave flip-flop is disabled by the inverter
� The information at the external R and S inputs is transmitted to the master flip-flop
�When the pulse returns to 0, the master flip-flop is disabled and the slave flip-flop is enabled
� The slave flip-flop then goes to the same state as the master flip-flop
(LRP)(MCA)(2012-13/ODD)(2012-2015)
FlipFlip--FlopsFlops
�Master-Slave D Flip-Flop
D Latch
(Master)
D
C
QD Latch
(Slave)
D
C
Q QD
CLK
(LRP)(MCA)(2012-13/ODD)(2012-2015)
FlipFlip--Flop Characteristic TablesFlop Characteristic Tables
D Q
Q 11
00
Q(t+1)D
Reset
Set
Q’(t)11
101
010
Q(t)00
Q(t+1)KJNo change
Reset
Set
Toggle
J Q
QK
T Q
QQ’(t)1
Q(t)0
Q(t+1)T
No change
Toggle
(LRP)(MCA)(2012-13/ODD)(2012-2015)
FlipFlip--Flop Characteristic EquationsFlop Characteristic Equations
D Q
Q 11
00
Q(t+1)D
Q(t+1) = D
Q’(t)11
101
010
Q(t)00
Q(t+1)KJ
Q(t+1) = JQ’ + K’Q
J Q
QK
T Q
QQ’(t)1
Q(t)0
Q(t+1)T
Q(t+1) = T ⊕⊕⊕⊕ Q
(LRP)(MCA)(2012-13/ODD)(2012-2015)
FlipFlip--Flop Characteristic EquationsFlop Characteristic Equations
�Analysis / Derivation
J Q
QK
010
110
001
101
1
1
0
0
K
11
01
110
000
Q(t+1)Q(t)J
No change
Reset
Set
Toggle
(LRP)(MCA)(2012-13/ODD)(2012-2015)
FlipFlip--Flop Characteristic EquationsFlop Characteristic Equations
�Analysis / Derivation
J Q
QK
0010
0110
001
101
1
1
0
0
K
11
01
110
000
Q(t+1)Q(t)J
No change
Reset
Set
Toggle
(LRP)(MCA)(2012-13/ODD)(2012-2015)
FlipFlip--Flop Characteristic EquationsFlop Characteristic Equations
�Analysis / Derivation
J Q
QK
0010
0110
1001
1101
1
1
0
0
K
11
01
110
000
Q(t+1)Q(t)J
No change
Reset
Set
Toggle
(LRP)(MCA)(2012-13/ODD)(2012-2015)
FlipFlip--Flop Characteristic EquationsFlop Characteristic Equations
�Analysis / Derivation
J Q
QK
0010
0110
1001
1101
1
1
0
0
K
011
101
110
000
Q(t+1)Q(t)J
No change
Reset
Set
Toggle
(LRP)(MCA)(2012-13/ODD)(2012-2015)
FlipFlip--Flop Characteristic EquationsFlop Characteristic Equations
�Analysis / Derivation
J Q
QK
0010
0110
1001
1101
1
1
0
0
K
011
101
110
000
Q(t+1)Q(t)J
Q
1
0
0
0
K
J 11
10
Q(t+1) = JQ’ + K’Q
(LRP)(MCA)(2012-13/ODD)(2012-2015)
State Diagrams and MinimizationState Diagrams and Minimization
�Analysis of a sequential circuit consists of
obtaining a table or a diagram for the time
sequence of inputs, outputs and internal states
�It is also possible to write Boolean expressions that
describe the behavior of sequential circuit
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Clocked RS FlipClocked RS Flip--FlopFlop
R
S
Q’
Q
clk
S R Q(t+1)
0 0 Q(t) No Change
0 1 0 Clear to 0
1 0 1 Set to 1
1 1 ? Indeterminate
Graphic Symbol
Characteristic Table
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Clocked JClocked J--K Flip FlopK Flip Flop
K
J
Q’
Q
clk
J K Q(t+1)
0 0 Q(t) No Change
0 1 0 Clear to 0
1 0 1 Set to 1
1 1 Q’(t) Complement
Graphic Symbol Characteristic Table
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Clocked D FlipClocked D Flip--FlopFlop
D
Q’
Q
clk
D Q(t+1)
0 0 Clear to 0
1 1 Set to 1
Graphic Symbol
Characteristic Table
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Clocked T FlipClocked T Flip--FlopFlop
T
Q’
Q
clk
T Q(t+1)
0 Q(t) No Change
1 Q’(t) Complement
Graphic Symbol Truth Table
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Excitation TablesExcitation Tables
�The characteristic tables of flip-flops specify the
next state when the inputs and the present states
are known
�During the design of sequential circuits we usually
know the required transition from present state to
next state and wish to find the flip-flop input
conditions that will cause the required transition
�The table that lists the required input
combinations for a given change of state is called
Excitation table
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Excitation Tables Excitation Tables (contd..)(contd..)
�The symbol X indicates that it is don’t care condition ,
which means it does not matter whether it is 0 or 1
�Reason for don’t care conditions in the excitation
tables is that there are two ways of achieving required
transition
�Ex: In JK flip-flop transition from present state of 0 to
next state of 0 can be achieved by having J and K
inputs equal to 0 or by J=0 and K=1. In both cases J
must be 0 but K can be either 0 or 1 ( don’t care)
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
�The State
State = Values of all Flip-Flops
Example
A B = 0 0
D Q
Q
CLK
D Q
Q
A
B
y
x
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
�State Equations
D Q
Q
CLK
D Q
Q
A
B
y
x
A(t+1) = DA
= A(t) x(t)+B(t) x(t)
= A x + B x
B(t+1) = DB
= A’(t) x(t)
= A’ x
y(t) = [A(t)+ B(t)] x’(t)
= (A + B) x’
(LRP)(MCA)(2012-13/ODD)(2012-2015)
State TableState Table
� A sequential circuit is specified by a state table that
relates outputs and next states as a function of inputs
and present states
� State table consists of four sections – present state,
input, next state, and output
1. Present state: shows states of flip-flops A and B at any given
time t
2. Input : gives a value of x for each possible present state
3. Next State: shows the states of flip-flops one clock period
later at a time t + 1
4. Output: gives the value of y for each present state and input
condition
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
�State Table (Transition Table)
D Q
Q
CLK
D Q
Q
A
B
y
x
A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
111
011
101
001
110
010
100
000
yBAxBA
OutputNext
StateInput
Present
State
t+1 tt
0 0 0
0 1 0
0 0 1
1 1 0
0 0 1
1 0 0
0 0 1
1 0 0
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
�State Table (Transition Table)
D Q
Q
CLK
D Q
Q
A
B
y
x
A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
x = 1
0
0
0
0
yx = 0x = 1x = 0
0
0
0
0
A
Next State
0
0
0
0
B
10111
10101
11110
01000
yBABA
OutputPresent
State
t+1 tt
(LRP)(MCA)(2012-13/ODD)(2012-2015)
State Table State Table (contd..)(contd..)
� In general, a sequential circuit with m flip-flops, n
input variables , and p output variables will contain m
columns for present state, n columns for inputs, m
columns for next state and p columns for outputs
�The present state and input columns are combined and
we list 2m+n binary combinations ( from 0 to 2m+n – 1)
�The next state and output columns are functions of the
present state and input values and are derived directly
from the circuit or Boolean equations
(LRP)(MCA)(2012-13/ODD)(2012-2015)
State DiagramState Diagram
�The information available in a state table can be
represented graphically in a state diagram
�In state diagram , a state is represented by a circle,
and the transition between states is indicated by
directed lines connecting the circles
�The state diagram of the given sequential circuit is
shown on the next slide
�The state diagram provides the same information
as the state table and is obtained form the state
table
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
� State Diagram
D Q
Q
CLK
D Q
Q
A
B
y
x
0 0 1 0
0 1 1 1
0/0
0/1
1/0
1/0
1/0
1/0 0/1
0/1
AB input/output
x = 1
0
0
0
0
y
x = 0x = 1x = 0
0
0
0
0
A
Next State
0
0
0
0
B
10111
10101
11110
01000
yBABA
OutputPresent
State
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
�D Flip-Flops
Example:D Q
Q
x
CLK
yA
1
0
1
0
1
0
1
0
y
11
11
01
01
10
10
00
00
AxA
Next
StateInput
Present
State
0
1
1
0
1
0
0
1
0 100,11 00,11
01,10
01,10
A(t+1) = DA = A ⊕⊕⊕⊕ x ⊕⊕⊕⊕ y
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
�JK Flip-Flops
Example:
J Q
QK
CLK
J Q
QK
x
A
B
JA = B KA = B x’
JB = x’ KB = A ⊕⊕⊕⊕ x
A(t+1) = JA Q’A + K’A QA
= A’B + AB’ + Ax
B(t+1) = JB Q’B + K’B QB
= B’x’ + ABx + A’Bx’111
011
101
001
110
010
100
000
KBJBKAJABAxBA
Flip-Flop
Inputs
Next
StateI/P
Present
State
0 0 1 0
0 0 0 1
1 1 1 0
1 0 0 1
0 0 1 1
0 0 0 0
1 1 1 1
1 0 0 0
0 1
0 0
1 1
1 0
1 1
1 0
0 0
1 1
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
�JK Flip-Flops
Example:
J Q
QK
CLK
J Q
QK
x
A
B
111
011
101
001
110
010
100
000
KBJBKAJABAxBA
Flip-Flop
Inputs
Next
StateI/P
Present
State
0 0 1 0
0 0 0 1
1 1 1 0
1 0 0 1
0 0 1 1
0 0 0 0
1 1 1 1
1 0 0 0
0 1
0 0
1 1
1 0
1 1
1 0
0 0
1 1
0 0 1 1
0 1 1 0
1 0 1
0
1
00
1
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
�T Flip-Flops
Example:
TA = B x TB = x
y = A B
A(t+1) = TA Q’A + T’A QA= AB’ + Ax’ + A’Bx
B(t+1) = TB Q’B + T’B QB= x ⊕⊕⊕⊕ B
O/P
111
011
101
001
110
010
100
000
yTBTABAxBA
F.F
Inputs
Next
StateI/P
Present
State
0 0
0 1
0 0
1 1
0 0
0 1
0 0
1 1
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0
0
0
0
0
0
1
1
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Analysis of Clocked Sequential CircuitsAnalysis of Clocked Sequential Circuits
�T Flip-Flops
Example:
O/P
111
011
101
001
110
010
100
000
yTBTABAxBA
F.F
Inputs
Next
StateI/P
Present
State
0 0
0 1
0 0
1 1
0 0
0 1
0 0
1 1
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0
0
0
0
0
0
1
1
0 0 0 1
1 1 1 0
0/0
1/0
0/0
1/0
1/0
1/1
0/00/1
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Mealy and Moore ModelsMealy and Moore Models
001111
100011
001101
100001
011110
100010
010100
000000
yBAxBA
O/PNext
StateI/P
Present
State
MealyMealy
For the same statestate,the outputoutput changes with the inputinput
100111
111011
011101
001001
001110
010010
010100
000000
yBAxBA
O/PNext
StateI/P
Present
State
MooreMoore
For the same statestate,the outputoutput does not change with the inputinput
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Moore State DiagramMoore State Diagram
State / Output
0 0 / 0 0 1 / 0
1 1 / 1 1 0 / 0
0
1
1
1
00
0
1
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Design of Clocked Sequential CircuitsDesign of Clocked Sequential Circuits
�Example:
Detect 3 or more consecutive 1’s
111
011
101
001
110
010
100
000
yBAxBA
OutputNext
StateInput
Present
State
0 0 0
0 1 0
0 0 0
1 0 0
0 0 0
1 1 0
0 0 1
1 1 1
A(t+1) = DA (A, B, x)
= ∑ (3, 5, 7)
B(t+1) = DB (A, B, x)
= ∑ (1, 5, 7)
y (A, B, x) = ∑ (6, 7)
Synthesis using DD Flip-Flops
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with DD F.F.F.F.
�Example:
Detect 3 or more consecutive 1’s
DA (A, B, x) = ∑ (3, 5, 7)
= A x + B x
DB (A, B, x) = ∑ (1, 5, 7)
= A x + B’ x
y (A, B, x) = ∑ (6, 7)
= A B
Synthesis using DD Flip-Flops
x
0
0
1
1
B
A 10
00
x
0
0
1
0
B
A 10
10
x
1
0
1
0
B
A 00
00
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with DD F.F.F.F.
�Example:
Detect 3 or more consecutive 1’s
DA = A x + B x
DB = A x + B’ x
y = A B
Synthesis using DD Flip-Flops
(LRP)(MCA)(2012-13/ODD)(2012-2015)
FlipFlip--Flop Excitation TablesFlop Excitation Tables
11
01
10
00
DQ(t+1)Q(t)
F.F.
Input
Next
State
Present
State
K
11
01
10
00
JQ(t+1)Q(t)
F.F.
Input
Next
State
Present
State
0 0 (No change)0 1 (Reset)
0 x
1 x
x 1
x 0
0
1
0
1
1 0 (Set)1 1 (Toggle)
0 1 (Reset)1 1 (Toggle)
0 0 (No change)1 0 (Set)
11
01
10
00
TQ(t+1)Q(t)
0
1
1
0
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with JKJK F.F.F.F.
�Example:
Detect 3 or more consecutive 1’s
JA
Flip-Flop
Inputs
KA KB
11111
00011
11101
00001
01110
00010
10100
00000
JBBAxBA
Next
StateInput
Present
State
0 x
0 x
0 x
1 x
x 1
x 0
x 1
x 0
JA (A, B, x) = ∑ (3)
dJA (A, B, x) = ∑ (4,5,6,7)
KA (A, B, x) = ∑ (4, 6)
dKA (A, B, x) = ∑ (0,1,2,3)
JB (A, B, x) = ∑ (1, 5)
dJB (A, B, x) = ∑ (2,3,6,7)
KB (A, B, x) = ∑ (2, 3, 6)
dKB (A, B, x) = ∑ (0,1,4,5)
Synthesis using JKJK F.F.
0 x
1 x
x 1
x 1
0 x
1 x
x 1
x 0
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with JKJK F.F.F.F.
�Example:
Detect 3 or more consecutive 1’s
JA = B x KA = x’
JB = x KB = A’ + x’
Synthesis using JKJK Flip-Flops
x
x
0
x
1
B
A xx
00
x
1
x
0
x
B
A 01
xx
x
x
x
x
x
B
A 10
10
x
1
1
0
1
B
A xx
xx
CLK
J Q
QK
x
A
B
J Q
QK y
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with TT F.F.F.F.
�Example:
Detect 3 or more consecutive 1’s
11111
00011
11101
00001
01110
00010
10100
00000
TA TBBAxBA
F.F.
Input
Next
StateInput
Present
State
0
0
0
1
1
0
1
0
Synthesis using TT Flip-Flops
0
1
1
1
0
1
1
0
TA (A, B, x) = ∑ (3, 4, 6)
TB (A, B, x) = ∑ (1, 2, 3, 5, 6)
(LRP)(MCA)(2012-13/ODD)(2012-2015)
Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with TT F.F.F.F.
�Example:
Detect 3 or more consecutive 1’s
TA = A x’ + A’ B x
TB = A’ B + B ⊕⊕⊕⊕ x
Synthesis using TT Flip-Flops
x
1
0
0
1
B
A 01
00
x
1
1
0
1
B
A 10
10
(LRP)(MCA)(2012-13/ODD)(2012-2015)
HomeworkHomework
The D latch is constructed with four NAND gates and an
inverter. Consider the following three other ways for
obtaining a D latch. In each case, draw the logic diagram
and verify the circuit operation.
(a) Use NOR gates for the SR latch part and AND gates
for the other two. An inverter may be needed.
(b) Use NOR gates for all four gates. Inverters may be
needed.
(c) Use four NAND gates only (without an inverter). This
can be done by connecting the output of the upper gate
that goes to the SR latch to the input of the lower gate
instead of the inverter output.
5-1
(LRP)(MCA)(2012-13/ODD)(2012-2015)
HomeworkHomework
A sequential circuit with two D flip-flops, A and B; two
inputs, x and y; and one output, z, is specified by the
following next-state and output equations:
A(t+1) = x’ y + x A
B(t+1) = x’ B + x A
z = B
(a) Draw the logic diagram of the circuit.
(b) List the state table for the sequential circuit.
(c) Draw the corresponding state diagram.
5-6
Show that the characteristic equation for the complement
output of a JK flip-flop is
Q’(t+1) = J’Q + K Q
5-3
(LRP)(MCA)(2012-13/ODD)(2012-2015)
HomeworkHomework
Derive the state table and the state diagram of the
sequential shown circuit. Explain the function that the
circuit performs.
5-8
(LRP)(MCA)(2012-13/ODD)(2012-2015)
HomeworkHomework
A sequential circuit has two JK flip-flops A and B and one
input x. The circuit is described by the following flip-flop
input equations:
JA = x KA = B’
JB = x KB = A
(a) Derive the state equations A(t+1) and B(t+1) by
substituting the input equations for the J and K
variables.
(b) Draw the state diagram of the circuit.
5-9