6 Interrupts (1) · 2019-12-10 · • Each Peripheral in lpc2148 has only 1 IRQ associated with...

transcript

LPC2148 - Interrupts

Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.eduDepartment of EIE / PEC

Dr.R.SundaramurthyDepartment of EIE

Pondicherry Engineering College

sundar@pec.edu

Interrupts , IRQs , ISRs

• Interrupt : “An interrupt is a signal sent to the CPU which indicates that a system event has a occurred which needs immediate attention“.

• Interrupt ReQuest (IRQ) can be thought of as a special request to the CPU to execute a function(small piece of code) when an interrupt occurs.

interrupt occurs.

• ISR : This function or ‘small piece of code’ is technically called an ‘Interrupt Service Routine‘ or ‘ISR‘.

• So when an IRQ arrives to the CPU , it stops executing the code current code and start executing the ISR. After the ISR execution has finished the CPU gets back to where it had stopped.

How We classify them ?

We Classify them as 2 types :

• Fast IRQs or FIQs

• Normal IRQs or IRQs which can be further

classified as :

– Vectored IRQ

– Non-Vectored IRQ.

Normal IRQ

Vectored IRQ

Non Vectored IRQ

Interrupts

Types of Interrupts in LPC2148

Interrupts are Handled by Vectored Interrupt Controller(VIC)

Types of Interrupts in LPC2148

• Fast Interrupt Request i.e FIQ : which has highest priority

• Vectored Interrupt Request i.e Vectored IRQ : which has ‘middle’ or priority between FIQ and Non-Vectored IRQ.

• Non-Vectored IRQ : which has the lowest priority.

What does Vectored mean ?• ‘Vectored‘ means that the CPU is aware of the address of

the ISR when the interrupt occurs

• Non-Vectored means that CPU doesn’t know the address of the ISR (nor) the source of the IRQ when the interrupt occurs.

• For Non – Vectored interrupts , CPU needs to be supplied by the ISR address.

• For the Vectored interrupts , the System internally maintains a table called IVT or Interrupt Vector Table which contains the information about Interrupts sources and their corresponding ISR address.

How Non-Vectored Interrupts are

handled?• Non-Vectored ISRs doesn’t point to a unique ISR

• The CPU needs to be supplied with the address of the ‘default’ or a ‘common’ ISR that needs to be executed when the interrupt occurs.

when the interrupt occurs.

• In LPC2148 this is facilitated by a register called ‘VICDefVectAddr‘.

• The user must assign the address of the default ISR to this register for handling Non-Vectored IRQs.

In a Nut Shell

• Vectored IRQ(VIRQ) has dedicated IRQ service

routine for each interrupt source

• Non-Vectored IRQ(NVIRQ) has the same IRQ

service routine for all Non-Vectored

Interrupts.

How Many Possible Interrupt Sources are there ?

• There are 22 Interrupt Sources in LPC2148

• But there are only 16 Slots in in the Vectored

Interrupt Controller (VIC) �� 0 to 15.

• These 22 possible sources have to be shared by using

Slots 0 to 15 of VIC

• Slot 0 �� Highest Priority

Slot 0 Highest Priority

• Slot 15 �� Lowest Priority

SFRs Involved

• VICIntSelect (R/W) � 0 = IRQ, 1 = FIQ

• VICIntEnable (R/W) � Enable Selective Interrupt Source

• VICIntEnClr (R/W) � Disable Selective Interrupt Source

• VICIRQStatus (R) � to know the status of enabled interrupt

• VICFIQStatus (R) � to know the status of enabled FIQ

• VICSoftInt � to trigger a software interrupt

• VICSoftIntClear � to clear software interrupt

• VICVectCntl0 to VICVectCntl15 � Assign interrupt source

• VICVectAddr0 to VICVectAddr15 � Assign interrupt address

• VICVectAddr� Holds the address of currently active interrupt

• VICDefVectAddr � Holds the addressof Non-Vectored ISR

VICIntSelect (R/W)• This register is used to select an interrupt as IRQ or as

• Writing a 0 at a given bit location will make the corresponding interrupt as IRQ

• Writing a 1 will make it FIQ.

• For e.g if you make Bit 4 as 0 then the corresponding interrupt source i.e TIMER0 will be IRQ else if you make Bit 4 as 1 it will be FIQ instead.

Bit 4 as 1 it will be FIQ instead.

• By default all interrupts are selected as IRQ. Note that here IRQ applies for both Vectored and Non-Vectored IRQs.

VICIntEnable (R/W)

• This is used to enable interrupts.

• Writing a 1 at a given bit location will make

the corresponding interrupt Enabled.

• If this register is read then 1′s will indicated

enabled interrupts and 0′s as disabled

interrupts.

• Writing 0′s has no effect.

VICIntEnClr (R/W)• This register is used to disable interrupts.

• This is similar to VICIntEnable expect writing a

1 here will disabled the corresponding

Interrupt.

• This has an effect on VICIntEnable since

writing at bit given location will clear the

corresponding bit in the VICIntEnable Register.

• Writing 0′s has no effect

VICIRQStatus (R)

• This register is used for reading the current

status of the enabled IRQ interrupts.

• If a bit location is read as 1 then it means that

the corresponding interrupt is enabled and

active.

VICFIQStatus (R)

• This register is used for reading the current

status of the enabled FIQ interrupts.

• If a bit location is read as 1 then it means that

active.

VICSoftInt• This register is used to generate interrupts

using software i.e manually generating

interrupts using code

• If you write a 1 at any bit location then the

correspoding interrupt is triggered i.e. it forces

the interrupt to occur.

• Writing 0 here has no effect.

VICSoftIntClear

• This register is used to clear the interrupt

request that was triggered(forced) using

VICSoftInt.

• Writing a 1 will release(or clear) the forcing of

the corresponding interrupt.

VICVectCntl0 to VICVectCntl15

• These are the Vector Control registers.

• These are used to assign a particular interrupt source to a particular slot.

• As mentioned before slot 0 i.e VICVectCntl0 has highest priority and VICVectCntl15 has the lowest.

• Each of this registers can be divided into 3 parts : {Bit0 to bit4} , {Bit 5} , {and rest of the bits}.

to bit4} , {Bit 5} , {and rest of the bits}.

• The first 5 bits i.e Bit 0 to Bit 4 contain the number of the interrupt request which is assigned to this slot. The interrupt source numbers are given in the table below :

• The 5th bit is used to enable the vectored IRQ slot by writing a 1

31 . . . 6 EN N4 N3 N2 N1 N0

Important Note

• Note that if the vectored IRQ slot is disabled it will not disable

the interrupt but will change the corresponding interrupt to

Non-Vectored IRQ.

• Enabling the slot here means that it can generate the address

of the ‘dedicated Interrupt handling function (ISR)’

• Disabling it will generate the address of the ‘common/default

Interrupt handling function (ISR)’ which is for Non-Vectored

• In simple words if the slot is enabled it points to ‘specific and

dedicated interrupt handling function’ and if its disable it will

point to the ‘default function’.

VICVectAddr0 to VICVectAddr15

(16 registers in all)

• For Vectored IRQs these register store the

address of the function that must be called

when an interrupt occurs.

• Note – If you assign slot 3 for TIMER0 IRQ then

care must be taken that you assign the

address of the interrupt function to

corresponding address register .. i.e

VICVectAddr3 in this example.

VICVectAddr

• This must not be confused with the above set of 16 VICVecAddrX registers.

• When an interrupt is Triggered this register holds the address of the associated ISR i.e the one which is currently active.

• Writing a value i.e dummy write to this register

• Writing a value i.e dummy write to this register indicates to the VIC that current Interrupt has finished execution.

• The only place we’ll use this register .. is at the end of the ISR to signal end of ISR execution.

VICDefVectAddr

• This register stores the address of the

“default/common” ISR that must be called

when a Non-Vectored IRQ occurs.

How to Write an ISR

Method – 1

__irq void myISR (void)

Method – 2

void myISR (void) __irq

For 8051

void myISR (void) interrupt 1{...}

A Simple 3 Step Process to Enable a

Vectored IRQ

• Step – 1 : Enable the IRQ by setting the

appropriate bit of VICIntEnable to ’1′.

• Step-2 : Identify the interrupt source number

and assign it to VICVectCntlX.

• Step-3 : Assign the address of the related ISR

to VICVectAddrX.

Example – Enabling Timer0 Interrupt

• First we need to enable the TIMER0 IRQ itself! Hence , from Table we get the bit number to Enable TIMER0 Interrupt which is Bit number 4. Hence we must make bit 4 in VICIntEnable to ’1′.

• Next , from Table we get the interrupt source number for TIMER0 which is decimal 4 and OR it

number for TIMER0 which is decimal 4 and OR it with (1<<5) [i.e 5th bit=1 which enables the slot] and assign it to VICVectCntlX.

• Next assign the address of the related ISR to VICVectAddrX.

Template Code

VICIntEnable |= (1<<Y) ;

VICVectCntlX = (1<<5) | Y ;

VICVectAddrX = (unsigned) myISR;

Assigning TIMER0 Interrupt to Slot0

VICIntEnable |= (1<<4) ; // Enable TIMER0 IRQ

VICVectCntl0 = (1<<5) | 4 ; //5th bit must 1 to

enable the slot

VICVectAddr0 = (unsigned) myISR;

//Vectored-IRQ for TIMER0 has been configured

• First when we have only one ‘internal’ source of interrupt in TIMER0 i.e an MR0 match event which raises an IRQ.

__irq void myISR(void){

long int regVal;regVal = T0IR; // read the current value in T0's Interrupt

regVal = T0IR; // read the current value in T0's Interrupt Register

//... MR0 match event has occured .. do something here

T0IR = regval; // write back to clear the interrupt flagVICVectAddr = 0x0; // The ISR has finished!

Important Note• Each Peripheral in lpc2148 has only 1 IRQ associated with it.

• But inside each device there may be different sources which can raise

an interrupt

• Like the TIMER0 peripheral has 4 match + 4 capture registers and any

one or more of them can be configured to trigger an interrupt.

• Hence such devices have a dedicated interrupt register which contains

a flag bit for each of these source(For Timer block its ‘T0IR‘).

• So , when the ISR is called first we need to identify the actual source of

the interrupt using the Interrupt Register and then proceed

accordingly.

• Also just before , when the main ISR code is finished we also need to

acknowledge or signal that the ISR has finished executing for the

current IRQ which triggered it.

• This is done by clearing the flag(i.e the particular bit) in the device’s

interrupt register and then by writing a zero to VICVectAddr register

which signifies that interrupt has ISR has finished execution

successfully.

Interrupt Examples

Timer0 Match Interrupts

Interrupt Enable register

(VICIntEnable)

Vector Control registers

(VICVectCntl0)

Problem-1

• Design a LPC2148 based system to perform

the following tasks.

• Task1 �Blink an LED at P1.31 using software

delay.

• Task2 � Generate a square wave at 1KHz @

P1.25 using Timer0 Match Interrupt

Timer – Match0 Interrupt

XTAL162

XTAL261

P0.0/TxD0/PWM119

P0.1/RxD0/PWM3/EINT021

P0.2/SCL0/CAP0.022

P0.3/SDA0/MAT0..0/EINT126

P0.4/SCK0/CAP0.1/AD0.627

P0.5/MISO0/MAT0.1/AD0.729

P0.6/MOSI0/CAP0.2/AD1.030

P0.7/SSEL0/PWM2/EINT231

P0.8/TxD1/PWM4/AD1.133

P0.10/RTS1/CAP1.0/AD1.235

P0.11/CTS1/CAP1.1/SCL137

P0.12/DSR1/MAT1.0/AD1.338

P0.13/DTR1/MAT1.1/AD1.439

P0.14/DCD1/EINT1/SDA141

P0.15/RI1/EINT2/AD1.545

P0.16/EINT0/MAT0.2/CAP0.246

P0.17/CAP1.2/SCK1/MAT1.247

P0.18/CAP1.3/MISO1/MAT1.353

P0.19/MAT1.2/MOSI1/CAP1.254

P0.20/MAT1.3/SSEL1/EINT355

P0.21/PWM5/AD1.6/CAP1.31

P0.22/AD1.7/CAP0.0/MAT0.02

P0.2358

P0.25/AD0.4/AOUT9

RTXC13

RTXC25

P0.27/AD0.0/CAP0.1/MAT0.111

P0.28/AD0.1/CAP0.2/MAT0.213

P0.29/AD0.2/CAP0.3/MAT0.314

P0.30/AD0.3/EINT3/CAP0.015

VREF63

VSSA59

P1.16/TRACEPKT016

P1.17/TRACEPKT112

P1.18/TRACEPKT28

P1.19/TRACEPKT34

P1.20/TRACESYNC48

P1.21/PIPESTAT044

P1.22/PIPESTAT140

P1.23/PIPESTAT236

P1.24/TRACECLK32

P1.25/EXTIN028

P1.26/RTCK24

P1.27/TDO64

P1.28/TDI60

P1.29/TCK56

P1.30/TMS52

P1.31/TRST20

VBAT49

P0.3117

P0.26/AD0.510

LPC2138

C5100pF

LED-YELLOW

void initInterrupt(void) { VICVectCntl0 = (0x01 << 5) | 4 ; //(i.e bit5 = 1) -> to enable Vectored IRQ slot VICVectAddr0 = (unsigned) T0ISR;

VICVectAddr0 = (unsigned) T0ISR; //Pointer Interrupt Function (ISR) VICIntEnable = 0x01 << 4; //Enable timer0 int }

void initTimer0(void) { T0PR = 60-1; // Pclk = 60MHz, ft = 1MHz , // Div = 60x10^6/1x10^6 = 60 T0CTCR = 0x00; // Configure as Timer T0TCR = 0x02; // Clear TC and PC T0MR0 = 500-1; // 500us

Method -1

Reset Timer after Match

T0MR0 = 500-1; // 500us T0MCR |= 0x03 ; // Reset after Match //Set bit0 & Bit1 to High which is //Interrupt on MR0, & RESET ON MR0 T0TCR = 0x01; // Enable TC }

void T0ISR(void) __irq { long int temp; temp = T0IR ; if (temp & 0x01) // MR0 Interrupt { Squarewave = ~( Squarewave);

Squarewave = ~( Squarewave); writepin(25, Squarewave); } T0IR = temp; // Clear T0IR VICVectAddr = 0x00; // Dummy Write }

void initTimer0(void) { T0PR = 60-1; // Pclk = 60MHz, ft = 1MHz , // Div = 60x10^6/1x10^6 = 60 T0CTCR = 0x00; // Configure as Timer T0TCR = 0x02; // Clear TC and PC T0MR0 = 500-1; // 500us

Method -2

Don’t Reset Timer after Match

T0MR0 = 500-1; // 500us T0MCR |= 0x01 ; //No Reset. //Set bit0 & Bit1 to High which is //Interrupt on MR0, T0TCR = 0x01; // Enable TC }

void T0ISR(void) __irq { long int temp; temp = T0IR ; if (temp & 0x01) // MR0 Interrupt { T0MR0 = T0MR0 + 500;// Increment! Squarewave = ~( Squarewave);

Squarewave = ~( Squarewave); writepin(25, Squarewave); } T0IR = temp; // Clear T0IR VICVectAddr = 0x00; // Dummy Write }

#include<lpc214x.h> #include "GPIO.h" #include "timer.h" #include "UART.h" #include "timerinterrupt.h" int main(void) { initPLL(); // 60 MHz Pclk initInterrupt(); initTimer0();

while(1) { writepin(31,1); // Background Task delay(); writepin(31,0); delay(); } }

Problem-2

• Design a LPC2148 based system to perform the following tasks.

• Task1 � Blink an LED at P1.31 using software delay.

• Task2 � Generate a square wave at 500Hz @ P1.25using Timer0 Match Interrupt

using Timer0 Match Interrupt

• Task3 � Generate a square wave at 1KHz @ P1.26 using Timer0 Match Interrupt

• Task4 � Generate a square wave at 2KHz @ P1.27using Timer0 Match Interrupt

• Task5 � Generate a square wave at 4KHz @ P1.28 using Timer0 Match Interrupt

XTAL162

XTAL261

P0.0/TxD0/PWM119

P0.2/SCL0/CAP0.022

P0.4/SCK0/CAP0.1/AD0.627

P0.10/RTS1/CAP1.0/AD1.235

P0.12/DSR1/MAT1.0/AD1.338

P0.13/DTR1/MAT1.1/AD1.439

P0.15/RI1/EINT2/AD1.545

P0.17/CAP1.2/SCK1/MAT1.247

P0.21/PWM5/AD1.6/CAP1.31

P0.22/AD1.7/CAP0.0/MAT0.02

RTXC13

RTXC25

Schematic

P0.22/AD1.7/CAP0.0/MAT0.0

P0.2358

P0.25/AD0.4/AOUT9

P0.27/AD0.0/CAP0.1/MAT0.111

P0.28/AD0.1/CAP0.2/MAT0.213

P0.29/AD0.2/CAP0.3/MAT0.314

P0.30/AD0.3/EINT3/CAP0.015

VREF63

VSSA59

P1.16/TRACEPKT016

P1.17/TRACEPKT112

P1.18/TRACEPKT28

P1.19/TRACEPKT34

P1.20/TRACESYNC48

P1.21/PIPESTAT044

P1.22/PIPESTAT140

P1.23/PIPESTAT236

P1.24/TRACECLK32

P1.25/EXTIN028

P1.26/RTCK24

P1.27/TDO64

P1.28/TDI60

P1.29/TCK56

P1.30/TMS52

P1.31/TRST20

VBAT49

P0.3117

P0.26/AD0.510

LPC2138

C5100pF

LED-YELLOW

Output

void initTimer0(void) { T0PR = 60-1;// Pclk = 60MHz, ft = 1MHz , Div = 60x10^6/1x10^6 = 60 T0CTCR = 0x00; // Configure as Timer T0TCR = 0x02; // Clear TC and PC T0MR0 = 1000-1; // 2000us = 500 HZ T0MR1 = 500-1; // 1000us = 1KHz T0MR2 = 250-1; // 500us = 2KHz T0MR3 = 125-1; // 250us = 4KHz

T0MR3 = 125-1; // 250us = 4KHz T0MCR |= (0x01 << 0)| (0x01 << 3)| (0x01 << 6)| (0x01 << 9) ; //Set bit0 High which is to : Interrupt on MR0,MR1,MR2,MR3 T0TCR = 0x01; // Enable TC }

void T0ISR(void) __irq { long int temp; temp = T0IR ; if (temp & 0x01) // MR0 Interrupt { T0MR0 = T0MR0 + 1000; sq500hz = ~(sq500hz); writepin(25,sq500hz); } if (temp & 0x02) // MR1 Interrupt { T0MR1 = T0MR1 + 500; sq1kz = ~(sq1kz); writepin(26,sq1kz); }

if (temp & 0x04) // MR2 Interrupt { T0MR2 = T0MR2 + 250; sq2kz = ~(sq2kz); writepin(27,sq2kz); } if (temp & 0x08) // MR3 Interrupt { T0MR3 = T0MR3 + 125; sq4kz = ~(sq4kz); writepin(28,sq4kz); } T0IR = temp; VICVectAddr = 0x00; }

External Interrupts

External Interrupt Mode register

(EXTMODE)

External Interrupt Polarity register

(EXTPOLAR)

External Interrupt Flag register

(EXTINT)

Pin function Select register 1

(PINSEL1)

Problem-3

delay.

• Task2 � Read a switch @ EINT0 and Turn a

Load @ P1.25 when count exceeds 10.

Schematic

XTAL162

XTAL261

P0.0/TxD0/PWM119

P0.2/SCL0/CAP0.022

P0.4/SCK0/CAP0.1/AD0.627

P0.10/RTS1/CAP1.0/AD1.235

P0.12/DSR1/MAT1.0/AD1.338

P0.13/DTR1/MAT1.1/AD1.439

P0.15/RI1/EINT2/AD1.545

P0.17/CAP1.2/SCK1/MAT1.247

RTXC13

RTXC25

P0.21/PWM5/AD1.6/CAP1.31

P0.22/AD1.7/CAP0.0/MAT0.02

P0.2358

P0.25/AD0.4/AOUT9

P0.27/AD0.0/CAP0.1/MAT0.111

P0.28/AD0.1/CAP0.2/MAT0.213

P0.29/AD0.2/CAP0.3/MAT0.314

P0.30/AD0.3/EINT3/CAP0.015

VREF63

VSSA59

P1.16/TRACEPKT016

P1.17/TRACEPKT112

P1.18/TRACEPKT28

P1.19/TRACEPKT34

P1.20/TRACESYNC48

P1.21/PIPESTAT044

P1.22/PIPESTAT140

P1.23/PIPESTAT236

P1.24/TRACECLK32

P1.25/EXTIN028

P1.26/RTCK24

P1.27/TDO64

P1.28/TDI60

P1.29/TCK56

P1.30/TMS52

P1.31/TRST20

VBAT49

P0.3117

P0.26/AD0.510

LPC2138

C5100pF

LED-YELLOW

void initInterrupt(void) { VICVectCntl0 = (0x01 << 5) | 14 ; // (bit5 = 1) -> to enable Vectored IRQ slot VICVectAddr0 = (unsigned) INT0ISR; //Pointer Interrupt Function (ISR) VICIntEnable = 0x01 << 14; //0x10; //Enable EINT0 interrupt

// INT0 SPECIFIC PINSEL1 |= 0x01 ;// P0.16 = INT0 EXTMODE |= 0x01 ;// INT0 = Edge Sensitive EXTPOLAR |= 0x00 ; // INT0 = Falling Edge }

void INT0ISR(void) __irq { long int temp; temp = EXTINT ; if (temp & 0x01) // EINT0 { if (mycount > 10) writepin(25,1); // Load ON else

{ mycount ++; writepin(25,0); // Load OFF } } EXTINT = temp; // clear interrupt VICVectAddr = 0x00; }

#include<lpc214x.h> #include "GPIO.h" #include "timer.h" #include "UART.h" #include "extinterrupt.h" int main(void) { initPLL(); // 60 MHz Pclk initInterrupt();

while(1) { writepin(31,1); delay(); writepin(31,0); delay(); } }

Problem-4

delay.

• Task2 � Read a switch @ EINT0 and Turn a

Load @ P1.25 when count exceeds 10.

• Task3 � Read a switch @ EINT1 and Toggle a

Load @ P1.26

XTAL162

XTAL261

P0.0/TxD0/PWM119

P0.2/SCL0/CAP0.022

P0.4/SCK0/CAP0.1/AD0.627

P0.10/RTS1/CAP1.0/AD1.235

P0.12/DSR1/MAT1.0/AD1.338

P0.13/DTR1/MAT1.1/AD1.439

P0.15/RI1/EINT2/AD1.545

P0.17/CAP1.2/SCK1/MAT1.247

P0.21/PWM5/AD1.6/CAP1.31

P0.22/AD1.7/CAP0.0/MAT0.02

P0.2358

RTXC13

RTXC25

Schematic

P0.25/AD0.4/AOUT9

P0.27/AD0.0/CAP0.1/MAT0.111

P0.28/AD0.1/CAP0.2/MAT0.213

P0.29/AD0.2/CAP0.3/MAT0.314

P0.30/AD0.3/EINT3/CAP0.015

VREF63

VSSA59

P1.16/TRACEPKT016

P1.17/TRACEPKT112

P1.18/TRACEPKT28

P1.19/TRACEPKT34

P1.20/TRACESYNC48

P1.21/PIPESTAT044

P1.22/PIPESTAT140

P1.23/PIPESTAT236

P1.24/TRACECLK32

P1.25/EXTIN028

P1.26/RTCK24

P1.27/TDO64

P1.28/TDI60

P1.29/TCK56

P1.30/TMS52

P1.31/TRST20

VBAT49

P0.3117

P0.26/AD0.510

LPC2138

C5100pF

LED-YELLOW

LED-YELLOWD1

LED-YELLOW

void initInterrupt(void) { // EINT1 15 # EINT0 14 # VICVectCntl0 = (0x01 << 5) | 14 ; //0x20 (i.e bit5 = 1) -> to enable Vectored IRQ slot VICVectAddr0 = (unsigned) INT0ISR; //Pointer Interrupt Function (ISR) VICIntEnable |= 0x01 << 14; //0x10; //Enable EINT0 int VICVectCntl1 = (0x01 << 5) | 15 ; //0x20 (i.e bit5 = 1) -> to enable Vectored IRQ slot VICVectAddr1 = (unsigned) INT1ISR; //Pointer Interrupt Function (ISR) VICIntEnable |= 0x01 << 15; //0x10; //Enable EINT1 int

VICIntEnable |= 0x01 << 15; //0x10; //Enable EINT1 int // EINT SPECIFIC PINSEL1 |= 0x01 << 0 ; // P0.16 = INT0, 1st Altrnate Function(01) EXTMODE |= 0x01 << 0 ; // INT0 = Edge Sensitive, Bit0 EXTPOLAR |= 0x00 << 0 ; // INT0 = Falling Edge, Bit0 PINSEL0 |= 0x03 << 6 ; // P0.3, 3rd Alternate Function(11) EXTMODE |= 0x01 << 1 ; // INT1 = Edge Sensitive, Bit1 EXTPOLAR |= 0x00 << 1 ; // INT1 = Falling Edge, Bit0 }

void INT0ISR(void) __irq { long int temp; temp = EXTINT ; if (temp & 0x01) // EINT0 { if (mycount > 5) writepin(25,1); // Load ON else

{ mycount ++; writepin(25,0); // Load OFF } } EXTINT = temp; // clear interrupt VICVectAddr = 0x00; }

void INT1ISR(void) __irq { long int temp; temp = EXTINT ; if (temp & 0x02) // EINT1 { LED = ~LED; writepin(26,LED); // Load OFF

} EXTINT = temp; // clear interrupt VICVectAddr = 0x00; }

#include<lpc214x.h> #include "GPIO.h" #include "timer.h" #include "UART.h" #include "extinterrupt1.h" int main(void) { initPLL(); // 60 MHz Pclk initInterrupt();

UART Interrupt

Problem-5

• Design a LPC2148 based system to perform the following tasks.

• Task1 � Blink an LED at P1.31 using software delay.

• Task2 � Receive commands from PC at 9600 Baud and control 2 Loads for the following commands.

control 2 Loads for the following commands.

• A � Load1 ON

• B � Load 1 Off

• C � Load 2 ON

• D � Load 2 OFF

Pin Function Select Register 0

(PINSEL0)

UART0 Line Control Register

(U0LCR)

UART0 Line Status Register (U0LSR)

UART0 Interrupt Enable Register(U0IER)

UART0 Interrupt Identification

Register (U0IIR)

Schematic

XTAL162

XTAL261

P0.0/TxD0/PWM119

P0.2/SCL0/CAP0.022

P0.4/SCK0/CAP0.1/AD0.627

P0.10/RTS1/CAP1.0/AD1.235

P0.12/DSR1/MAT1.0/AD1.338

P0.13/DTR1/MAT1.1/AD1.439

P0.15/RI1/EINT2/AD1.545

RTXC13

RTXC25

Xmodem, Ymodem, Zmodem

VT52, VT100, ANSIRXD

T1IN11

R1OUT12

T2IN10

R2OUT9

T1OUT14

R1IN13

T2OUT7

MAX232

P0.17/CAP1.2/SCK1/MAT1.247

P0.21/PWM5/AD1.6/CAP1.31

P0.22/AD1.7/CAP0.0/MAT0.02

P0.2358

P0.25/AD0.4/AOUT9

P0.27/AD0.0/CAP0.1/MAT0.111

P0.28/AD0.1/CAP0.2/MAT0.213

P0.29/AD0.2/CAP0.3/MAT0.314

P0.30/AD0.3/EINT3/CAP0.015

VREF63

VSSA59

P1.16/TRACEPKT016

P1.17/TRACEPKT112

P1.18/TRACEPKT28

P1.19/TRACEPKT34

P1.20/TRACESYNC48

P1.21/PIPESTAT044

P1.22/PIPESTAT140

P1.23/PIPESTAT236

P1.24/TRACECLK32

P1.25/EXTIN028

P1.26/RTCK24

P1.27/TDO64

P1.28/TDI60

P1.29/TCK56

P1.30/TMS52

P1.31/TRST20

VBAT49

P0.3117

P0.26/AD0.510

LPC2138

C5100pF

LED-YELLOW

#include<lpc214x.h> #include "GPIO.h" #include "timer.h" #include "UART.h" #include "UARTInterrupt.h" int main(void) { initPLL(); // 60 MHz Pclk initInterrupt(); initserial();

void initserial(void) { PINSEL0 =0X05; // P0.0 = TxD , P0.1 = RxD U0LCR = 0X83; // DLAB(7) = 1 , 8 Bit UART (1,0) = 1, U0DLL = 0X87; // = 60 x 10^6 / (9600 x 16) = 391 = 0x0187 U0DLM = 0X01; // 9600 Baud U0LCR = 0X03; // DLAB(7) = 0,8 Bit UART (1,0) = 1,

U0LCR = 0X03; // DLAB(7) = 0,8 Bit UART (1,0) = 1, }

void initInterrupt(void) { /

// UART0 06 # VICVectCntl0 = (0x01 << 5) | 6 ; //0x20 (i.e bit5 = 1) -> to enable Vectored IRQ slot VICVectAddr0 = (unsigned) UART0ISR; //Pointer Interrupt Function (ISR)

//Pointer Interrupt Function (ISR) VICIntEnable = 0x01 << 6; //0x10; //Enable UART0 interrupt // UART SPECIFIC U0IER = 0X01 ; // Enables the Receive Data Available interrupt }

void UART0ISR(void) __irq { long int temp; temp = U0IIR ; // Reading Clears this Register if (temp & 0x04) // Receive Data Available (RDA) = "0100" { mydata = U0RBR ; if (mydata == 'A') writepin(25,1); else if (mydata == 'B') writepin(25,0); else if (mydata == 'C')

else if (mydata == 'C') writepin(26,1); else if (mydata == 'D') writepin(26,0); else { writepin(25,0); writepin(26,0); } } VICVectAddr = 0x00; }

End of Session

sundar@pec.edu

6 Interrupts (1) · 2019-12-10 · • Each Peripheral in lpc2148 has only 1 IRQ associated with...

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