64 bit Kogge-Stone 64 bit Kogge-Stone Adders in different logic Adders in different logic

styles – A studystyles – A studyRob McNishRob McNish

Satyanand NalamSatyanand Nalam

ObjectivesObjectives To compare speed and power dissipation To compare speed and power dissipation

of 64-bit Kogge Stone Adder in 3 logic of 64-bit Kogge Stone Adder in 3 logic styles:styles:

Static CMOSStatic CMOS Dynamic LogicDynamic Logic Static Output Prediction Logic (OPL)Static Output Prediction Logic (OPL)

To reduce leakage power dissipation in To reduce leakage power dissipation in OPL circuits using MTCMOS techniques.OPL circuits using MTCMOS techniques.

The AdderThe Adder Technology used – 90nm PTMTechnology used – 90nm PTM Hierarchical designHierarchical design Inverting sub-blocks (dot and square) Inverting sub-blocks (dot and square)

to implement the nodes of the Kogge-to implement the nodes of the Kogge-Stone treeStone tree

Implement the basic sub-blocks in Implement the basic sub-blocks in static, dynamic and OPL-static stylesstatic, dynamic and OPL-static styles

Minimal changes to the tree netlist to Minimal changes to the tree netlist to construct the 3 addersconstruct the 3 adders

Schematic for 16 bit adder is shown. Schematic for 16 bit adder is shown. Can be extended for a 64 bit adder.Can be extended for a 64 bit adder.

Schematic for 16 bit adderSchematic for 16 bit adder

Output Prediction Logic (OPL)Output Prediction Logic (OPL) Logic style that can be applied to different Logic style that can be applied to different

logic styles to increase speedlogic styles to increase speed Retains attributes of the underlying family Retains attributes of the underlying family

(e.g Static, Dynamic, Pseudo-nmos etc.)(e.g Static, Dynamic, Pseudo-nmos etc.) Relies on alternating nature of logical Relies on alternating nature of logical

output values of a critical path, i.e, for any output values of a critical path, i.e, for any critical path the outputs of the gates along critical path the outputs of the gates along the paths will be alternating zeros and the paths will be alternating zeros and ones.ones.

OPL ConceptOPL Concept OPL predicts that every OPL predicts that every

output will be 1 after the output will be 1 after the transitions are completedtransitions are completed

Since all gates are Since all gates are inverting, the predictions inverting, the predictions will be correct one half of will be correct one half of the time => at least 2X the time => at least 2X speedupspeedup

Problem: One at the Problem: One at the output of every inverting output of every inverting gate is not a stable stategate is not a stable state

OPL ExampleOPL Example Solution: Solution: tri-state each gate

with a clock => 1 at input and 1 output is possible.

Example shown – 3 input nor Example shown – 3 input nor gate in OPL-static, where gate in OPL-static, where the predicted value is a 1.the predicted value is a 1.

CLK=0 => gate is tristated, CLK=0 => gate is tristated, with output precharged to 1. with output precharged to 1. CLK=1 => conventional CLK=1 => conventional CMOS gateCMOS gate

OPL clocking: Chain of OPL gatesOPL clocking: Chain of OPL gates

OPL clockingOPL clocking Clock separation too less => heavy Clock separation too less => heavy

glitching and precharge value lostglitching and precharge value lost Clock separation too large => Clock separation too large =>

minimal glitching, but speedup minimal glitching, but speedup achieved is limited by the clock, not achieved is limited by the clock, not by the databy the data

Optimal Clock separation => limited Optimal Clock separation => limited glitching and circuit is not clock-glitching and circuit is not clock-blocked.blocked.

Delay Plot – Static CMOSDelay Plot – Static CMOS

Best case delay for the carry Best case delay for the carry tree is the path for C0 as this tree is the path for C0 as this consists entirely of inverters.consists entirely of inverters.

Best case delay distribution Best case delay distribution for the static cmos adder is for the static cmos adder is shown. The mean was 144 shown. The mean was 144 ps.ps.

The input vectors (in hex) The input vectors (in hex) are A=0000 0000 0000 0001 are A=0000 0000 0000 0001 B=0000 0000 0000 0000 -> B=0000 0000 0000 0000 -> 0000 0000 0000 00010000 0000 0000 0001

Delay Plot – Static CMOSDelay Plot – Static CMOS Delay plot for a Delay plot for a

random case is random case is shown.shown.

Input vectors are Input vectors are A=8000 0000 0000 A=8000 0000 0000 0000 B=0000 0000 0000 B=0000 0000 0000 0000 -> 8000 0000 0000 -> 8000 0000 0000 00000000 0000 0000

Delay Plot – Dynamic logicDelay Plot – Dynamic logic Delay plot for a Delay plot for a

random case is random case is shown.shown.

Input vectors are Input vectors are A=8000 0000 0000 A=8000 0000 0000 0000 B=0000 0000 0000 B=0000 0000 0000 0000 -> 8000 0000 0000 -> 8000 0000 0000 00000000 0000 0000

Power dissipationPower dissipation

Static CMOSStatic CMOS 0.19 mW0.19 mW

Dynamic LogicDynamic Logic 14.7 mW14.7 mW

OPLOPL 16.29 mW16.29 mW

Power dissipation was measured for the Power dissipation was measured for the three adders using spectre for the three adders using spectre for the

The novelty: Using a high VT footer to The novelty: Using a high VT footer to reduce leakage power in OPL gatesreduce leakage power in OPL gates

Added High VT footer transistor, in Added High VT footer transistor, in order to reduce leakage power in order to reduce leakage power in standby mode for the OPL adder.standby mode for the OPL adder.

Footers added to the basic sub-Footers added to the basic sub-blocks.blocks.

High VT transistor modeled by High VT transistor modeled by applying a negative voltage to the applying a negative voltage to the bulk of the footer transistor.bulk of the footer transistor.

Leakage power reductionLeakage power reduction 10x reduction in leakage power got by 10x reduction in leakage power got by

using the high VT footer in the OPL using the high VT footer in the OPL adder.adder.

w/o high w/o high VT footerVT footer

6.3 uW6.3 uW

With high With high VT footerVT footer

0.54 uW0.54 uW

ReferencesReferences1. A 0.5V, 400MHz, VDD-Hopping Processor with Zero-VTH FD-SOI TechnologyHiroshi Kawaguchi, Kouichi Kanda ISSCC 2003 / SESSION 6 / LOW-POWER

DIGITAL TECHNIQUES / PAPER 6.3

2. Output prediction logic: a high-performance CMOS design technique McMurchie, L.; Kio, S.; Yee, G.; Thorp, T.; Sechen, C.; Computer Design, 2000. Proceedings. 2000 International Conference on 17-20 Sept. 2000

Page(s):247 - 254 3. 409ps 4.7 FO4 64b adder based on output prediction logic in 0.18um CMOS

Sheng Sun; Yi Han; Xinyu Guo; Kian Haur Chong; McMurchie, L.; Sechen, C.; VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on 11-12 May 2005 Page(s):52 - 58