7-5 MicrooperationAn elementary operations performed on

data stored in registers or in memory.Transfer ArithmeticLogic: perform bit manipulation on data in

registerBitwise AND, Bitwise OR ….

Shift

Arithmetic Microoperations

Arithmetic Microoperations

The control variable X selects the operation, and the control variable K1 loads the result in to R1.

211:1 RRRKX

1211:1 RRRKX

Fig. 7.6 Implementation

Logic Microoperationsmanipulate the bits stored in a registerconsider each bit in register separately

Logic MicrooperationsMask: allow us to deal with some specific bits

R1: 10101101 10101011 (data)R2: 00000000 11111111 (mask) 00000000 10101011 <=R1

←R1^R2

Logic Microoperations

R1: 10101101 10101011 (data)R2: 11111111 00000000 (mask) 11111111 10101011 <=R1

←R1ˇR2

R1: 10101101 10101011 (data)R2: 11111111 00000000 (mask) 01010010 10101011 <=R1

←R1 R2

Shift Microoperationsshift left/shift rightincoming bit/outgoing bit

7-6 Microoperation on A single RegisterMultiplexer-based transferif (K1=1) then (R0 ← R1) else if (K2=1) then

(R0 ← R2)

K1: R0 ← R1, R0 ← R2:21KK

Multiplexer-based transfer

Multiplexer-based transfer •Generalization of Multiplexer selection for n sources

Shift RegistersSerial input (SI)Serial output (SO)

Shift Register with parallel load

Shift Register with Parallel Load

Bidirectional Shift Register

DQSS

QQSS

QQSS

:

sr:

sl:

01

01

01

One stage diagram

Bidirectional Shift Register

Ripple counterStructure similar to ripple adder

Synchronous Binary Counter -Serial gating

Synchronous Binary Counter -Parallel gating

Only one AND gate delay

Four AND gates delay

Up-Down Binary Counter

))((

))((

))((

21021033

101022

0011

00

ENSQQQSQQQQD

ENSQQSQQQD

ENSQSQQD

ENQD

A

A

A

A

Homework #1

Prove it and draw the logic diagram

S=0 up counter

S=1 down counter

Binary counter with parallel load

Fig. 7-14

It is a case of the up-down counter in the previous slide.

(why? what case?)

BCD counterA divide-by-N counter (modulo-N counter)

is a counter goes through a repeated sequence of N states

Fig. 7-15

Another BCD counter

81

4218188

2144

8122

11

)(

QQCOY

QQQQQQD

QQQD

QQQD

QD

Modulo 6 counter

CBD

CD

BAD

C

B

A

Modulo 6 counter

Homework #2Problem 7-15 with modified sequence

0,3,2,1,5,4,7Run the simulation for the designed circuit

by using Quartus IIDeal with the unused state as don’t care Test the circuit when the unused state

occurs (on paper)