9-6 The Control Word

Fig. 9-11

The selection variables for the datapath control the microoperations executed within datapath for any given clock pulse

Table 9-5

1321 RRRThe binary control word for this operation: 001_010_011_0_0101_0_1

Example:

Example of microoperation -- using symbolic notation

Example of microoperation -- using binary control word

SimulationFig. 9-12

Status_bits:

vector (V, C, N, Z)

9-7 A Simple Computer Architecture In programmable system, a portion of the input

to the processor consists of a sequence of instructions.

Instructions are usually stored in memory (ROM or RAM)

The address for the instruction to be executed is stored program counter (PC)

In non-programmable system, the control unit determines the (sequence of) operations to be perform based on only input and status bit.

In non-programmable system, the control unit is not responsible to any instruction.

9-7 A Simple Computer Architecture

Instruction set architectureProgram for specifying the operation

to be performedProgram is a list of instructionControl unit reads an instruction from

memory• decode and execute the instruction by

issuing a sequence of one or more microoperations

Instruction set architecture

Instruction set: a collection of instructions Instruction set architecture (ISA): a thorough

description of instruction setThree major components:

• Storage resource• Instruction formats• Instruction specifications

Storage resources

The instruction memory and data memory can be the same or be different memory depend on different standpoint of the CPU.

Instruction formats

If a branch occurs, new address is formed by PC contents + AD (6bits)

The 6 bits AD is referred to address offset (in signed 2s complement)

Sign extension is used to preserving 2s complement representation

Instruction specifications

zf: zero fill

se: sign extension

Mnemonic: symbolic representation for opcode

Assembler: a program converts the opcode symbol to binary

In memory

Why

PC < － PC – 20

in address 55?

Suppose R4 contains 70 and R5 contains 80

9-8 Single-Cycle Hardwired Control

A control unit that fetches and executes an instruction in a single clock cycle.

We refer to this computer as the single-cycle computer.

Fig. 9-15 Block diagram for a single-cycle computer

Instruction decoder

Fig. 9-16

1. PL=0,

PC is incremented (no jump or branch)

PL=1, JB=1 for jump,

JB=0 for branch

2. BC: for branch condition (Z or N)

3. For Branch on Zero, FS=0000 to pass reg. A . But bit 9 (FS0) is 1. (a contradiction)

How to solve?? (See text)

Truth table for instruction decoder You should refer to Table 9-8 for

realizing this table.

Six instruction

A program for 83-(2+3)

Suppose R3 contains 248Memory in location 248 contains 2Memory in location 249 contains 83The result will be placed in location

249

A program for 83-(2+3)

LD R1, R3 ADI R1, R1, 3 NOT R1,R1 INC R1, R1 INC R3, R3 LD R2, R3 ADD R2, R2, R1 INC R3, R3 ST R3, R2

Single-Cycle Computer Issues Shortcomings of single-cycle computer

When performing complex operation, f.g. binary multiplication, it can’t be accomplished by a microoperation that can be executed in a single clock cycle.

• The control organization that provides multiple clock cycle is needed

If single memory for instruction and data is used (at present, there are two distinct memory), at least two clocks, are required for obtaining and executing the instruction. First one is used to fetch instruction the second one is used to read/write data.

• This can easily be accomplished by multiple-cycle control.

Single-Cycle Computer Issues

Long worst-case delay path – lower limit on the clock period

• Example Fig. 9-17• 9.8ns delay => 102MHz

limited

End this lecture

We neglect the section 9-9 multiple-cycle hardwired control due to less of time.