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Abstract—To develop a small size and light weight DC-AC
inverter, a Fibonacci switched-capacitor (SC) DC-AC inverter using
power saving techniques is proposed in this paper. Unlike common SC
DC-AC inverters, the proposed inverter is controlled so that the
voltage ratio of capacitors becomes the ratio of a Fibonacci number.
By combining some of these capacitors in series, the proposed inverter
provides the staircase AC waveform with many steps. Furthermore, a
power saving technique is suggested to utilize the energy stored in
stray parasitic capacitances effectively. Therefore, the proposed
inverter can improve power efficiency, because the proposed inverter
can reduce parasitic power losses. Theoretical analysis and simulation
program with integrated circuit emphasis (SPICE) simulations show
the effectiveness of the proposed inverter. Moreover, there are
presented for theoretical analysis, including power efficiency, output
voltage, etc.
Keywords—DC-AC inverters, Fibonacci numbers, power saving
techniques, switched capacitor circuits.
I. INTRODUCTION
N mobile applications, the demand for a DC-AC inverter
realizing small volume and light weight is increasing to
develop multifunctional and portable products such as a power
inverter for a cigarette socket, a digital amplifier, and so on.
However, common DC-AC inverter containing transformers is
heavy and bulky. For this reason, in recent years, the DC-AC
inverter designed by switched-capacitor (SC) techniques
attracts many researchers’ attention. The main advantage of the
SC DC-AC inverters is that they can be implemented without
the use of magnetic components. Therefore, the SC technique
can achieve no flux of magnetic induction, small size, light
Kei Eguchi is with the Department of Information Electronics, Fukuoka
Institute of Technology, 3-30-1 Wajirohigashi, Higashi-ku, Fukuoka, Japan (
phone:+81-92-606-3137; fax:+81-92-606-0726; e-mail: eguti@fit.ac.jp).
Yanan Zhang is with the Department of Information Electronics, Fukuoka
Institute of Technology, 3-30-1 Wajirohigashi, Higashi-ku, Fukuoka, Japan
(e-mail: eguchi@inass.org).
Kanji Abe is with the Department of Information Electronics, Fukuoka
Institute of Technology, 3-30-1 Wajirohigashi, Higashi-ku, Fukuoka, Japan
(e-mail: s11f1002@benefit.ac.jp).
Ichirou Oota is with the Department of Information and Communication,
Kumamoto National College of Technology, 2659-2, Suya, Koushi,
Kumamoto, Japan (e-mail: oota-i@kumamoto-nct.ac.jp).
Shinya Terada is with the Department of Control and Information Systems
Engineering, Kumamoto National College of Technology, 2659-2, Suya,
Koushi, Kumamoto, Japan (e-mail: terada@kumamoto-nct.ac.jp).
Hirofumi Sasaki is with Tokai University, 9-1-1 Toroku, Kumamoto, Japan.
He is now with Tokai University, 9-1-1 Toroku, Kumamoto, Japan. (e-mail:
hsasaki@ktmail.tokai-u.jp).
weight, and so on, though the output voltage of the SC DC-AC
inverter is realized in a staircase.
For this reason, several types of SC DC-AC inverters have
been proposed. In 1993, Ueno et al. suggested the voltage
equation type DC-AC inverter [1]-[3]. Following this, Oota et al.
and Chang proposed a parallel-connected DC-AC inverter [4],
[5]. To generate a staircase AC waveform, a series-parallel type
converter [6] has been utilized by these conventional SC
inverters. However, in the series-parallel type converter, the
number of steps is directly proportional to the number of
capacitors. Therefore, the conventional inverters require many
capacitors to generate the staircase waveform formed by many
steps. To overcome this problem, Eguchi et al. suggested the
DC-AC converter using a ring-type converter [7], [8]. Unlike
the series-parallel type converter, the ring-type converter can
achieve s/r ((r=1,2, …, N) and (s=1,2, … N)) step-up/step-down
conversion. Therefore, Eguchi’s DC-AC inverter can generate
the staircase waveform formed by many steps when the number
of capacitors, N, is large. However, it is difficult to realize a
large number of conversion ratios when the DC-AC inverter has
a small number of capacitors. To reduce the number of
capacitors, Chang proposed the multistage switched-capacitor-
voltage-multiplier (SCVM) DC-AC inverter [9], [10] and Zou
et al. designed the switched-capacitor-cell-based voltage
multiplier [11]. By connecting SC cells in series, these DC-AC
inverters can increase the number of steps of the staircase AC
waveform.
However, there is still room for improvement; 1. All
capacitor voltages are the same in the conventional inverters
[1]-[5], [7]-[11]. Therefore, the conventional inverter is still
difficult to provide the staircase waveform formed by many
steps. 2. Energy loss due to stray parasitic capacitances has not
been taken into account in previous studies. In the integrated
circuit (IC) design of power converters, reducing parasitic
power losses is one of the most important issues to improve
power efficiency.
In this paper, a Fibonacci switched-capacitor (SC) DC-AC
inverter using power saving techniques is proposed. Unlike
common SC DC-AC inverters, the proposed inverter is
controlled so that the voltage ratio of capacitors becomes the
ratio of a Fibonacci number [12]. By combining some of these
capacitors in series, the proposed inverter achieves larger
number of conversion ratios than common SC DC-AC inverters.
In other words, the proposed inverter can provide the staircase
AC waveform by the number of capacitors less than common
A Fibonacci Switched-Capacitor DC-AC
Inverter for Small Power Applications
Kei Eguchi, Ya-Nan Zhang, Kanji Abe, Ichirou Oota, Shinya Terada, and Hirofumi Sasaki
I
International conference on Innovative Engineering Technologies (ICIET’2014) Dec. 28-29, 2014 Bangkok (Thailand)
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SC DC-AC inverters. Furthermore, a power saving technique is
suggested to utilize the energy stored in stray parasitic
capacitances effectively. The proposed SC inverter reuses a part
of the electric charge in stray parasitic capacitances by
connecting stray parasitic capacitances at the end of each clock
cycle. By alleviating parasitic losses, the proposed inverter can
improve power efficiency. To show the effectiveness of the
proposed inverter, theoretical analysis and simulation program
with integrated circuit emphasis (SPICE) simulations are
performed.
Fig. 1 Conventional SC inverter using series-parallel type converters
II. CIRCUIT CONFIGURATION
A. Conventional Inverter
Fig. 1 shows the conventional SC DC-AC inverter using
series-parallel type converters [4]. As Fig.1 shows, the SC
inverter has no magnetic components. To generate a staircase
AC waveform, bi-directional switches are controlled like a
step-up DC-DC converter. Concretely, all the capacitor voltages
become Vin. Therefore, the output voltage Vo of each step is
expressed as
,ino mVV where 1,,2,1 Nm . (1)
In (1), N is the number of main capacitors. Concretely, in the
case of 3 stages, the conventional inverter of Fig.1 generates the
staircase waveform formed by 8 (=(3+1)×2) steps. The staircase
waveform Vout is obtained through the full bridge.
In previous studies, the existence of stray parasitic
capacitance has not been taken into account in the design of the
SC DC-AC inverters. When the SC inverter is integrated into an
IC form, the stray parasitic capacitance exists as shown in Fig.2.
In Fig.2, Ct denotes the stray parasitic capacitance between top
plate and substrate and Cb denotes the stray parasitic
capacitance between bottom plate and substrate. In
conventional SC inverters, the electric charge stored in stray
parasitic capacitance is consumed idly when the main capacitor
Cij ((i=1, 2, …, N) and (j=1, 2)) is connected to the ground.
Fig. 2 Stray parasitic capacitance
Fig. 3 Proposed SC inverter using power saving techniques
B. Proposed Inverter
Fig. 3 shows the proposed Fibonacci SC DC-AC inverter. In
Fig.3, Cij ((i=1, 2, …, N) and (j=1, 2)) is the main capacitor, Cti
j
(=αCij) denotes the i-th stray parasitic capacitance between top
plate and substrate, and Cbij (=βCi
j) denotes the i-th stray
parasitic capacitance between bottom plate and substrate.
Unlike conventional inverters, the voltage ratio of capacitors
becomes the ratio of a Fibonacci number. Concretely, the
voltage of i-th (i=1, 2, 3) capacitor is i×Vin in the case 3 stages.
In the proposed inverter with 3 stages, the output voltage Vo of
each step is expressed as
,ino nVV where 7,,2,1 n . (2)
As (2) shows, the proposed inverter generates the staircase
waveform formed by 14 (=7×2) steps in the case of 3 stages.
Therefore, the proposed inverter can provide the staircase AC
waveform by a smaller number of capacitors. Furthermore,
unlike the conventional inverter of Fig.1, the inverter blocks are
connected mutually through the bi-directional switches Sc’s in
order to utilize the energy stored in stray parasitic capacitances
effectively.
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TABLE I
SETTING OF CLOCK PULSES IN THE CASE OF THE 7X STEP-UP
State On Off
T1 S1p1, S
1g1, S
1s2, S
1p3, S
1g3, S
2s1, S
2s2, S
2s3, S
2o4 Others
T2 Sc Others
T3 S1s1, S
1s2, S
1s3, S
1o4, S
2p1, S
2g1, S
2s2, S
2p3, S
2g3 Others
T4 Sc Others
T5 S1s1, S
1p2, S
1g2, S
1s3, S
2s1, S
2s2, S
2s3, S
2o4 Others
T6 Sc Others
T7 S1s1, S
1s2, S
1s3, S
1o4, S
2s1, S
2p2, S
2g2, S
2s3 Others
T8 Sc Others
(a)
(b)
(c)
(d)
Fig. 4 Instantaneous equivalent circuits in the case of the 7x step-up;
(a) State-T1, (b) State-T3, (c) State-T5, and (d) State-T7
For easy understanding, the circuit operation in the case of
the 7x step-up is described in the following. Table I shows an
example of the timing of clock pulses. As Table I shows, the
proposed inverter has the following processes: 1) Charging and
transferring process and 2) Charge reusing process. In Table I,
T1, T3, T5, T7, and T9 are the charging and transferring process
and T2, T4, T6, T8, and T10 are the charge reusing process. In the
charging and transferring process, the n× (n={1,2, …, 7})
stepped-up voltage is obtained by combing some of main
capacitors in series. Concretely, to obtain the 7x stepped-up
voltage, C1j, C2
j, C3
j (j=1, 2), and the input voltage are connected
in series. On the other hand, in the charge reusing process, the
electric charges stored in Cbij ((i=1, 2, 3) and (j=1, 2)) are
equalized through the bi-directional switch Sc before the electric
charge is consumed idly. In other words, the power dissipation
of the input can be reduced by the equalization of electric
charges in Cbij. Therefore, owing to the charge reusing process,
power efficiency can be improved.
III. THEORETICAL ANALYSIS
Concerning power efficiency and output voltage, theoretical
analysis is performed in this section. To evaluate the maximum
power efficiency and the maximum output voltage, we assume
that 1) Parasitic elements are negligibly small; and 2) Time
constant is much larger than the period of clock pulses.
First, the behavior of the inverter block-1 is discussed. To
save space, theoretical analysis is performed concerning the
proposed inverter of Fig.3. In the case of the 7x step-up, the
instantaneous equivalent circuits of the proposed inverter are
expressed by Fig.4, where the bi-directional switch is modeled
by an ideal switch with the on-resistance Ron. In Fig.4, the
instantaneous equivalent circuits of State-T2, T4, T6, and T8 are
omitted, because the charge transfer is not caused in these states.
In the proposed SC inverter, the differential value of the
electric charge in Cij ((i=1, 2, 3, o) and (j=1, 2)) satisfies
8
1
0k
i
Tkq , (3)
where
8
1k
kTT , sTTTTT 7531 ,
and TTTTT 8642 .
In (3), ΔqTki denotes the electric charge of the i-th capacitor in
State-Tk, Ts is the interval of the charging and transferring
process, and δT is the interval of the charge reusing process. In
the steady state of the inverter block-1, the differential values of
electric charges in Vi and Vo, ΔqTk,Vi and ΔqTk,Vo, are expressed as
State-T1: ,21
, 111 TTVT qqqi
,11 ,
o
TVT qqo
and ,32
11 TT qq (4)
State-T2: ,0,, 22
oi VTVT qq (5)
State-T3: ,1
, 33 TVT qqi
,333
3
,
o
TTVT qqqo
International conference on Innovative Engineering Technologies (ICIET’2014) Dec. 28-29, 2014 Bangkok (Thailand)
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and ,321
333 TTT qqq (6)
State-T4: ,0,, 44
oi VTVT qq (7)
State-T5: ,1
, 55 TVT qqi
,55 ,
o
TVT qqo
,21
55 TT qq and ,03
5 Tq (8)
State-T6: ,0,, 66
oi VTVT qq (9)
State-T7: ,1
, 77 TVT qqi
,777
3
,
o
TTVT qqqo
and .321
777 TTT qqq (10)
State-T8: ,0,, 88
oi VTVT qq (11)
Using (4) – (11), the average input current and the average
output current can be obtained as
T
TI i
ik
V
k
VTi
8
1
,
1
and ,1 8
1
,T
TI o
ok
V
k
VTo
(12)
where ΔqVi and ΔqVo are electric charges in the input and output,
respectively. Substituting (3) – (11) into (12), we have the
relation between the input current and output current as follows:
,7 oi II
where 3
314 TV qq
i and .2 3
3TV qqo
(13)
Next, let us consider the consumed energy in one period. In
the instantaneous equivalent circuits of Fig.4, energy is
consumed by the resistor Ron. Therefore, using (3) – (11), the
consumed energy of the inverter block can be expressed as
8
1k
TT kWW
,
41
168 2
oVon qT
R
where
21221
1111 T
s
onTT
s
onT q
T
Rqq
T
RW
,3 22
1T
s
on qT
R
,4 21
33 T
s
onT q
T
RW
,2 2221
555 T
s
onT
s
onT q
T
Rq
T
RW
,4 21
77 T
s
onT q
T
RW
and .08642 TTTT WWWW (14)
Fig. 5 General equivalent circuit of the SC DC-DC converter
Here, it is known that the general equivalent circuit of the SC
DC-DC converter is given by Fig.5 [13]. In Fig.5, RSC is called
the SC resistance and m is the ratio of an ideal transformer.
Since the proposed SC inverter is controlled like a step-up
DC-DC converter, the equivalent circuit of the proposed SC
inverter can be expressed by using Fig.5. In the general
equivalent circuit of Fig.5, the consumed energy WT can be
defined as
TRT
qW SC
V
TO
2
: . (15)
Therefore, using (14) and (15), the SC resistance RSC of the
inverter block is obtained as
41
168
on
SC
RR . (16)
Finally, by combining (13) and (16), the equivalent circuit of
the inverter block is expressed by the following Kettenmatrix:
o
oSC
i
i
I
VR
I
V
10
1
70
07
1
. (17)
As Fig.3 shows, the proposed SC inverter consists of two
inverter blocks. Therefore, the equivalent circuit of the
proposed SC inverter can be expressed as Fig.6. From Fig.6, we
have the maximum efficiency η and the maximum output
voltage Vout as follows:
International conference on Innovative Engineering Technologies (ICIET’2014) Dec. 28-29, 2014 Bangkok (Thailand)
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2SCL
L
RR
R
and ,72
in
SCL
Lout V
RR
RV
(18)
because the equivalent circuit of the proposed SC inverter can
be expressed as
.10
21
70
07
1
out
outSC
in
in
I
VR
I
V (19)
Of course, other step-up modes can be analyzed in the same
way. Table II shows the summary of theoretical results.
Fig. 6 Equivalent circuit of the proposed SC inverter in the case of the
7x step-up
TABLE II
SUMMARY OF THEORETICAL RESULTS
Gain On resistance RSC
1 x 412 onR
2 x 4112 onR
3 x 4126 onR
4 x 4150 onR
5 x 41118 onR
6 x 41120 onR
7 x 41168 onR
Fig. 7 Simulated staircase waveform of the proposed inverter
Fig. 8 Simulated staircase waveform of the conventional inverter
IV. SIMULATION
Concerning the proposed SC DC-AC inverter of Fig.3, the
SPICE simulation is performed under conditions that Vin=20V,
C1j=…= C3
j=100nF, Co
j=100pF, Ron=0.1Ω, T=0.4μs, Ts=70ns,
δT=30ns, Cb1j =…= Cb3
j = Ct1
j =…= Ct3
j=1pF, and Cbo
j = Cto
j
=1fF (α=β=10-5
). In the SPICE simulation, Cbij and Cti
j are
assumed to be the same value, because the value of the stray
parasitic capacitance changes according to a semi- conductor
process.
Fig.7 shows the simulated AC waveform of the proposed SC
DC-AC inverter and Fig.8 shows the simulated AC waveform of
the conventional SC DC-AC of Fig.1. To generate the staircase
100V@50Hz waveforms of Figs.7 and 8, the output load RL was
set to 1kΩ. As Fig.7 shows, the proposed inverter can provide
the staircase waveform with 14 steps. On the other hand, as
Fig.8 shows, the AC waveform of the conventional inverter has
only 9 steps. In other words, in order to generate the staircase
waveform with 14 steps, the conventional inverter suggested in
[4] requires 14 capacitors and 46 switches. On the other hand,
the proposed inverter requires only 8 capacitors and 33
switches. Therefore, the proposed inverter can achieve small
volume and light weight. The proposed inverter can reduce 6
capacitors and 13 switches from the conventional inverter.
Fig. 9 shows the simulated power efficiency as a function of
the output power. In Fig.9, the solid line shows the power
efficiency of the proposed inverter with power saving technique
and the broken line shows the power efficiency of the proposed
inverter without power saving technique. As Fig.9 shows, the
proposed inverter can achieve more than 85% efficiency in the
range from 0.3 to 30W. Furthermore, the proposed inverter can
alleviate the influence of the parasitic loss when the output
International conference on Innovative Engineering Technologies (ICIET’2014) Dec. 28-29, 2014 Bangkok (Thailand)
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power is a small value. Concretely, the proposed inverter can
improve the power efficiency more than 4.3% when the output
power is 1W.
However, the power efficiency and the output voltage
decrease when the output power is a small value. Fig.10 shows
the simulated output as a function of the output power. As Table
II and (19) show, the SC resistance becomes large due to the
interval of the charge reusing process δT. As a result, the power
efficiency and the output voltage decrease when the output load
RL is a small value. Therefore, as Figs.9 and 10 show, the
proposed power saving technique is effective for small power
DC-AC applications.
Fig. 9 Simulated power efficiency as a function of the output power
Fig. 10 Simulated output voltage as a function of the output power
V. CONCLUSION
For small power applications, a Fibonacci SC DC-AC
inverter using power saving techniques has been proposed in
this paper. Concerning power efficiency and output voltage,
theoretical analysis was performed to clarify the characteristics
of the proposed inverter. Furthermore, the validity of circuit
design was confirmed by SPICE simulations.
The simulation results showed the following results: 1) In the
case of the staircase AC waveform formed by 14 steps, the
proposed inverter can reduce 6 capacitors and 13 switches from
the conventional inverter. Therefore, the proposed inverter can
achieve smaller size than the conventional inverter; 2) In the
range from 0.3 to 30W, the proposed inverter can achieve more
than 85% efficiency; and 3) When the output power is 1W, the
proposed power saving technique can improve the power
efficiency more than 4.3%. The proposed power saving
technique is effective when the output power is a small value.
The experiment concerning the proposed SC DC-AC inverter
is left to a future study.
ACKNOWLEDGMENT
This work was supported by JSPS KAKENHI Grant Number
24531193.
REFERENCES
[1] F. Ueno, T. Inoue, I. Oota and I. Harada, “Novel type DC-AC converter
using a switched-capacitor transformer,” in Proc. 11th European
Conference on Circuit Theory and Design, Switzerland, 1993, pp.
1181-1184.
[2] F. Ueno, I. Oota, I. Harada, and K. Ishimatsu, “A DC-AC converter using
a tapped capacitors string for lighting electroluminescence,” in Proc.
1994 Symposium on Power Electronics Circuits, Hong Kong, 1994, pp.
5-8.
[3] K. Ishimatsu, I. Oota, and F. Ueno, “A DC-AC converter using a voltage
equational type switched-capacitor transformer,” in Proc. IEEE Applied
Power Electronics Conference and Exposition, vol.2, California, 1998,
pp. 603-606.
[4] M. Oota, S. Terada, K. Eguchi, and I. Oota, “Development of switched-
capacitor bi-directional DC-AC converter for inductive and capacitive
loads,” in Proc. 2009 IEEE International Symposium on Industrial
Electronics, Seoul, 2009, pp. 1618-1623.
http://dx.doi.org/10.1109/ISIE.2009.5222549
[5] Y. H. Chang, “Design and analysis of power-CMOS-gate-based
switched-capacitor boost DC–AC inverter,” IEEE Trans. Circuits and
Systems-I, vol. 51, no.10, Oct. 2004, pp. 1998–2016.
http://dx.doi.org/10.1109/TCSI.2004.835681
[6] Y. Beck and S. Singer, “Capacitive transposed series-parallel topology
with fine tuning capabilities,” IEEE Trans. Circuits and Systems-I, vol.
58, no.1, Jan. 2011, pp. 51–61.
http://dx.doi.org/10.1109/TCSI.2010.2055277
[7] K. Eguchi, I. Oota, S. Terada, and T. Inoue, “A design method of
switched-capacitor power converters by employing a ring-type power
converter,” International Journal of Innovative Computing, Information
and Control, vol. 4, no.10(A), Oct. 2009, pp. 2927–2938.
[8] S. Terada, I. Oota, K. Eguchi, and F. Ueno, “A ring type
switched-capacitor (SC) programmable converter with DC or AC input/
DC or AC output,” in Proc. 47th IEEE International Midwest Symposium
on Circuits and Systems, Hiroshima, 2004, pp. 29-32.
[9] Y. H. Chang, “Design and analysis of multistage multiphase
switched-capacitor boost DC–AC inverter,” IEEE Trans. Circuits and
Systems-I, vol. 58, no.1, Jan. 2011, pp. 205–218.
http://dx.doi.org/10.1109/TCSI.2010.2055294
[10] Y. H. Chang, “Modelling and analysis of multistage switched-capacitor-
voltage-multiplier boost DC-AC inverter,” in Proc. 2011 IEEE Ninth
International Conference on Power Electronics and Drive Systems,
Singapore, 2011, pp. 523-526.
http://dx.doi.org/10.1109/PEDS.2011.6147299
[11] K. Zou. M. J. Scott, and J. Wang, “Switched-capacitor-cell-based voltage
multipliers and DC–AC inverters,” IEEE Trans. Industry Applications,
vol. 48, no.5, Sep./Oct. 2012, pp. 1598–1609.
http://dx.doi.org/10.1109/TIA.2012.2209620
[12] K. Eguchi, S. Hirata, M. Shimoji, and H. Zhu, “Design of a
step-up/step-down k (=2,3, …)-Fibonacci DC-DC converter designed by
switched-capacitor techniques,” in Proc. 2012 Fifth International
Conference on Intelligent Networks and Intelligent Systems, Tianjin,
2012, pp. 170-173. http://dx.doi.org/10.1109/ICINIS.2012.67
[13] K. Eguchi, P. Julsereewong, A. Julsereewong, K. Fujimoto, and H.Sasaki,
“A Dickson-type adder/subtractor DC-DC converter realizing step-up/
step-down conversion,” International Journal of Innovative Computing,
Information and Control, vol. 9, no.1, Jan. 2013, pp. 123–138.
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