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中国科学院电子学研究所
A Survey of Open Source Processors for
FPGAs Rui Jia, Colin Yu Lin, Zhenhong Guo and Haigang Yang
System on Programmable Chip Research Department,
Institute of Electronics, Chinese Academy of Sciences, Beijing, China
Corresponding Author: yanghg@mail.ie.ac.cn
Institute of Electronics, Chinese Academy of Sciences, Beijing China
Motivation
Overview of Open Source Soft Processors
Selection of Open Source Processors
Implementations and Comparisons
Discussions and Conclusion
01 02 03 04 05
A Survey of Open Source Processors for
FPGAs CONTENTS
Institute of Electronics, Chinese Academy of Sciences, Beijing China
1
中国科学院电子学研究所
Institute of Electronics, Chinese Academy of Sciences, Beijing China
FPGA-based SoCs
FPGA-based SoCs have become a technology trend for reconfigurable
systems.
The most attractive and practical methodology for SOC designer is to
select reusable components and IPs
Processor should be designed, verified, tested and shared in module level.
How to choose suitable soft processors for FPGA-based SoCs?
Numerous open source processors make the selection process difficult.
Differences between existing vendor-provided and open source processors? 2
中国科学院电子学研究所
Open source soft core processor
Open source hardware improves the design productivity.
many open source processors are available.
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Totally 178 processors found
on OpenCores, soft
microprocessor and Wikipedia
9 processors are not designed
for FPGAs->169 processors
considered
Life cycle is categorized into
planning, pre-alpha, alpha,
beta, stable, and mature
stages
Only 68 in stable can be used
conveniently, in which processor
is feature-complete and has few
bugs
24
11
27
33
68
6
Planning
Pre-Alpha
Alpha
Beta
Stable
unknown
3
中国科学院电子学研究所
Institute of Electronics, Chinese Academy of Sciences, Beijing China
68 stable processors:
(a)License. (b)Instruction Set Architecture(ISA). (c)Compiler and assembler
(d)Verification (d)Design documentation . 4
中国科学院电子学研究所
Institute of Electronics, Chinese Academy of Sciences, Beijing China
License
The license of processors cover:
GNU General Public License (GPL),
GNU Lesser General Public License (LGPL)
Berkeley Software Division (BSD),
Creative Commons-Attribution (CC-BY). 5
中国科学院电子学研究所
Institute of Electronics, Chinese Academy of Sciences, Beijing China
Instruction Set Architecture (ISA)
In the table, most of the ISAs are property of
commercial corporations.
6
中国科学院电子学研究所
Provider NumberISA
ARM
Lattice Semiconductor
Open Cores
Sun Microsystems
ARMv2
LatticeMicro32
MIPS 16
DLX
OpenRISC
unnamed
SPARCv8
1
1
1
3
14
1
SPARCv9 4
Atmel
Hitachi
Intel
MIPS Technology
MOS Technology
Motorola
National Semiconductor
Synopsys
Texas Instruments
Xilinx
Microchip Technology
AVR
SuperH-2
8080
8088
80186
MCS-48
PIC-baseline family
MIPS I
MIPS 32
6502
6800
68000
68HC05
68HC11
68HC08
COP400
ARC
MSP430
MicroBlaze
Free
Zilog Z80
Proprietary
Total 68
5
1
2
3
1
1
5
6
1
4
3
1
1
1
1
1
1
3
1
1
4Only 35% of these ISAs are free and can be used without
infringements to the commercial corporations.
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Compiler and Assembler
38 processors have both compiler and assembler
7
中国科学院电子学研究所
12 processors only assembler
18 processors do not provide either
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Verification Design Documentation
about 68% processors have
been verified on FPGAs.
7 of the processors have also
been verified as ASIC.
Availability of design files and
documents weigh heavy.
About 43% processors have no
design documentation. 8
中国科学院电子学研究所
Institute of Electronics, Chinese Academy of Sciences, Beijing China
Summary Features of open source soft processors are summarized in Table below.
The table consists of 68 stable soft processors under open source license
8
中国科学院电子学研究所
9
Introduction
Overview of Open Source Soft Processors
Selection of Open Source Processors
Implementations and Comparisons
Discussions and Conclusion
01
02 03
04 05
A Survey of Open Source Processors for
FPGAs CONTENTS
Institute of Electronics, Chinese Academy of Sciences, Beijing China
10
中国科学院电子学研究所
中国科学院电子学研究所Institute of Electronics, Chinese Academy of Sciences, Beijing China
Selecting Method/Process
11
total 68 stable ones, 47 processors under
open source license are chosen.
choose 36 processors with available
compiler and assembler.
17 processors with free ISA are chosen.
11 processors with general ISA 3 multi-core processors
processor are not studied. 1 asynchronous
processor is not studied.
Selecting Method/Process They are Amber ,LatticeMicro32 (LM32), S1, Altor32, OpenRISC 1200 (OR1200), LEON2 and LEON3.
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Amber23 Amber25 LM32 S1 OR1200 LEON3Altor32 LEON2
Bit-width
Pipeline Depth
Multiplier
Divider
Register
Total Size/Kbytes
Instruction Cache/Kbytes
Data Cache/Kbytes
Sets
FPU
32
3
√N/A
N/A
15
8(d),12,16,32
8(d),12,16,32
256(d)
Byte-per-line/Bytes
Write policy
Replacement policy
Shared/Separate TLB
No. of Data TLB entries
No. of Shared TLB entries
No. of Instruction TLB entries
16
Write through
Read- miss
N/A
N/A
N/A
N/A
Wishbone
2(d),3,4 or 8
Pro
cess
or
Arc
hit
ectu
re
Co
mp
lex
Co
mp
uta
tio
n
Un
it
Ca
che
Associativity/Ways
Interface
MM
U
32
5
√N/A
N/A
15
16,24,32(d)
8,12,16(d),32
8,12,16(d),32
256(d)
16
Write through
Read- miss
N/A
N/A
N/A
N/A
Wishbone
2,3,4(d) or 8
32
6
Optional,√(d)
N/A
32
0,1,2,4(d),8
0,1,2(d),4,8
0,1,2(d),4,8
128,256,512(d),...
4(d),8,16
Write through
Read- miss
N/A
N/A
N/A
N/A
Wishbone
1(d),2
64
6
√
√
√640
32(d)
16(d)
16(d)
128(d)
32(d)
Write through
LRU
Separate
64
64
N/A
Wishbone
/Amba
4(d)
32
5
√N/A
N/A
32
16(d)
8(d)
8(d)
512(d)
16(d)
Write through
LRU
Separate
16,32,64(d),128
16,32,64(d),128
N/A
Wishbone
1(d)
32
7
√
√
√40-520,136(d)
0.008(d)-64
0.004(d)-32
0.004(d)-32
1(d)-256
4(d)-8
Write through
LRU,LRR,Random
N/A(d),Optional
2-32
2-32
2-32
Wishbone
/Amba
1(d)-4
32
5
√N/A
N/A
32
16(d)
8(d)
8(d)
256(d)
32
Write through
Read- miss
N/A
N/A
N/A
N/A
Wishbone
1(d)
Optional,√(d)
32
5
√
√
√40-520, 136(d)
8(d)
4(d)
4(d)
128(d)
32(d)
Write through
LRU,LRR,Random(d)
N/A(d),Optional
2-32,N/A(d)
2-32,N/A(d)
2-32,N/A(d)
Amba
1(d)-4
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中国科学院电子学研究所
Introduction
Overview of Open Source Soft Processors
Selection of Open Source Processors
Implementations and Comparisons
Discussions and Conclusion
01
02 03 04
05
A Survey of Open Source Processors for
FPGAs CONTENTS
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13
中国科学院电子学研究所
中国科学院电子学研究所Institute of Electronics, Chinese Academy of Sciences, Beijing China
Processor Descriptions Features of selected commercial processors
Three versions of Nios II cores are economic, standard and fast cores,
Nios II/e, Nios II/s and Nios II/f, respectively.
MicroBlaze is the most wildly used soft core provided by Xilinx.
Altera Xilinx
Bit-width
Pipeline Depth
Multiplier
Divider
Register
Total Size/Kbytes
Instruction Cache/KBytes
Data Cache/KBytes
Sets
FPU
32
N/A
N/A
N/A
N/A
32
N/A
N/A
N/A
N/A
Nios II/e
Byte-per-line/Bytes
Write policy
Replacement policy
Shared/Separate TLB
No. of Data TLB entries
No. of Shared TLB entries
No. of Instruction TLB entries
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Avalon
N/A
Pro
cess
or
Arc
hit
ectu
re
Co
mp
lex
Co
mp
uta
tio
n
Un
it
Ca
che
Associativity/Ways
Interface
MM
U
32
5
Optional,N/A(d)
Optional,N/A(d)
N/A
32
2(d),4,...
2(d),4
N/A
64(d),128
32(d)
N/A
unkown
N/A
N/A
N/A
N/A
Avalon
1(d)
32
6
Optional,√(d)
N/A
32
4(d),8,...
2(d),4,...
2(d),4,...
64(d),128,...
Nios II/f
4,16,32(d),...
Write through
unkown
Shared+Separate
6(d)
4(d)
128(d)
Avalon
1(d)
32
3/5(d)
Optional,√(d)
Optional,N/A(d)
Optional,N/A(d)
32
16,32,N/A(d)
8,16,N/A(d)
8,16,N/A(d)
512
MicroBlaze/single
16(d),32
Write through(d),Write Back
unkown
Separate+Shared
Optional,N/A(d)
Optional,N/A(d)
64,N/A(d)
PLB,AXI(d),LMB,FSL,XCL
1
Optional,√(d)
32
3/5(d)
Optional,√(d)
Optional,N/A(d)
Optional,N/A(d)
32
16,32,N/A(d)
8,16,N/A(d)
8,16,N/A(d)
512
MicroBlaze/dual
16(d),32
Write through(d),Write Back
unkown
Separate+Shared
Optional,N/A(d)
Optional,N/A(d)
64,N/A(d)
PLB,AXI(d),LMB,FSL,XCL
1
Nios II/s
14
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Implementations and Comparisons
Then two comparison works are presented:
I. All selected processors and three versions of Nios II cores provided by
Altera (economic, standard and fast cores, which are noted as Nios II/e,
Nios II/s and Nios II/f, respectively ) are implemented on an Altera Stratix
V FPGA, and the implementation results are compared and discussed.
II. The selected processors and MicroBlaze supplied by Xilinx are also
implemented on a Xilinx Virtex-7 FPGA, and the implementation results
are compared and discussed.
15
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Altera Stratix V FPGA
16
中国科学院电子学研究所
0 1000 2000 3000 4000 5000 6000
500
1000
1500
2000
2500
3000
3500
ALMs
Regs
0 1000 2000 3000 4000 5000 60000
20
40
60
80
100
0 2 4 6 8
50
100
150
200
250
300
350
400
Pipeline Depth
Fmax/MHz
0 5 10 15 20 25 30 35-0.5
0
0.5
1
1.5
2
2.5
3
3.5x 10
5
Amber23 Amber25 LEON3 Altor32
Nios II/e Nios II/s Nios II/f
LM32 OR1200
ALMs
PCD/mW
CacheSize
TBMBs/bits(a) Logic Resources Utilization (b) Pipeline depth and Fmax
(c) ALMs and PCD (d) Cache Size and TBMBs
(a) shows the resource
comparison results
Nios II/e/s/f can be implemented
with less ALMs and registers than
all the open source processors.
LEON3 needs the least resources
in all selected open source
processors.
The average ALMs and registers
of Nios II e/s/f is 19% and 29% of
the averages of all open source
processors.
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Altera Stratix V FPGA
17
中国科学院电子学研究所
0 1000 2000 3000 4000 5000 6000
500
1000
1500
2000
2500
3000
3500
ALMs
Regs
0 1000 2000 3000 4000 5000 60000
20
40
60
80
100
0 2 4 6 8
50
100
150
200
250
300
350
400
Pipeline Depth
Fmax/MHz
0 5 10 15 20 25 30 35-0.5
0
0.5
1
1.5
2
2.5
3
3.5x 10
5
Amber23 Amber25 LEON3 Altor32
Nios II/e Nios II/s Nios II/f
LM32 OR1200
ALMs
PCD/mW
CacheSize
TBMBs/bits(a) Logic Resources Utilization (b) Pipeline depth and Fmax
(c) ALMs and PCD (d) Cache Size and TBMBs
(b) compares the maximum
frequency vs. pipeline depth
Fmax of Nios II/e/s/f are higher
than all open source processors.
Fmax of Nios II/e is the highest and
Fmax of Nios II/s is the lowest in all
three versions of Nios II.
LEON3 with 7 stages of pipeline
and Amber23 with a 3-stage
pipeline achieve the highest and
the lowest frequencies in all open
source processors, respectively.
Fmax of open source processor is
proportionate to the pipeline
depth.
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Altera Stratix V FPGA
18
中国科学院电子学研究所
0 1000 2000 3000 4000 5000 6000
500
1000
1500
2000
2500
3000
3500
ALMs
Regs
0 1000 2000 3000 4000 5000 60000
20
40
60
80
100
0 2 4 6 8
50
100
150
200
250
300
350
400
Pipeline Depth
Fmax/MHz
0 5 10 15 20 25 30 35-0.5
0
0.5
1
1.5
2
2.5
3
3.5x 10
5
Amber23 Amber25 LEON3 Altor32
Nios II/e Nios II/s Nios II/f
LM32 OR1200
ALMs
PCD/mW
CacheSize
TBMBs/bits(a) Logic Resources Utilization (b) Pipeline depth and Fmax
(c) ALMs and PCD (d) Cache Size and TBMBs
The core static thermal power
dissipations PCS of all processors
are nearly the same, because they
are mainly decided by the chosen
FPGA device.
The core dynamic thermal power
dissipations PCD and the number of
ALMs are expressed in (c).
PCD is proportionate to ALMs
PCD of Nios II/e/s/f are less than
all open source processors.
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Altera Stratix V FPGA
19
中国科学院电子学研究所
0 1000 2000 3000 4000 5000 6000
500
1000
1500
2000
2500
3000
3500
ALMs
Regs
0 1000 2000 3000 4000 5000 60000
20
40
60
80
100
0 2 4 6 8
50
100
150
200
250
300
350
400
Pipeline Depth
Fmax/MHz
0 5 10 15 20 25 30 35-0.5
0
0.5
1
1.5
2
2.5
3
3.5x 10
5
Amber23 Amber25 LEON3 Altor32
Nios II/e Nios II/s Nios II/f
LM32 OR1200
ALMs
PCD/mW
CacheSize
TBMBs/bits(a) Logic Resources Utilization (b) Pipeline depth and Fmax
(c) ALMs and PCD (d) Cache Size and TBMBs
Total block memory bits (TBMBs)
are mainly decided by total cache
size.
(d) illustrates the relationship
between total block memory bits
(TBMBs) and the total cache size.
The values of TBMBs vary directly
with the total size of caches.
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(a) shows the resource
comparison results
MicroBlaze can be implemented
with less LUTs and Regs than all
open source processors.
LEON3 needs the least
resources in all selected open
source processors.
The LUTs and Regs of
MicroBlaze is 41% and 58% of the
averages of all open source
processors.
Xilinx Virtex-7 FPGA
20
中国科学院电子学研究所
1000 2000 3000 4000 5000 6000 7000500
1000
1500
2000
2500
3000
3500
1000 2000 3000 4000 5000 6000 70000
10
20
30
40
50
60
70
80
90
MicroBlaze
2 3 4 5 6 7 8100
150
200
250
0 5 10 15 20 25 30 35
0
10
20
30
40
50
Amber23 Amber25 LM32 OR1200 LEON3 Altor32
(a) Logic Resources Utilization (b) Pipeline depth and Fmax
LUTs
Regs
Pipeline
Depth
Fmax/MHz
LUTs
PCD/mW
Cache
Size
NR
(c) LUTs and Pd (d) Cache Size and NR
Institute of Electronics, Chinese Academy of Sciences, Beijing China
(b) compares the maximum
frequency vs. pipeline depth
The Fmax of MicroBlaze is higher
than all open source processors
except LEON3.
LEON3 with 7 stages of pipeline
and Amber23 with a 3-stage
pipeline achieve the highest and
lowest frequencies in all open
source processors, respectively.
Fmax of open source processor is
proportionate to the pipeline depth.
Xilinx Virtex-7 FPGA
21
中国科学院电子学研究所
1000 2000 3000 4000 5000 6000 7000500
1000
1500
2000
2500
3000
3500
1000 2000 3000 4000 5000 6000 70000
10
20
30
40
50
60
70
80
90
MicroBlaze
2 3 4 5 6 7 8100
150
200
250
0 5 10 15 20 25 30 35
0
10
20
30
40
50
Amber23 Amber25 LM32 OR1200 LEON3 Altor32
(a) Logic Resources Utilization (b) Pipeline depth and Fmax
LUTs
Regs
Pipeline
Depth
Fmax/MHz
LUTs
PCD/mW
Cache
Size
NR
(c) LUTs and Pd (d) Cache Size and NR
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the quiescent power (Ps) of all
processors are nearly the same,
because they are mainly decided
by the chosen FPGA device.
The core dynamic thermal power
dissipations PCD and the number of
LUTs are expressed in (c).
Pd is proportionate to LUTs, and
Pd of MicroBlaze is less than all
open source processors.
Xilinx Virtex-7 FPGA
22
中国科学院电子学研究所
1000 2000 3000 4000 5000 6000 7000500
1000
1500
2000
2500
3000
3500
1000 2000 3000 4000 5000 6000 70000
10
20
30
40
50
60
70
80
90
MicroBlaze
2 3 4 5 6 7 8100
150
200
250
0 5 10 15 20 25 30 35
0
10
20
30
40
50
Amber23 Amber25 LM32 OR1200 LEON3 Altor32
(a) Logic Resources Utilization (b) Pipeline depth and Fmax
LUTs
Regs
Pipeline
Depth
Fmax/MHz
LUTs
PCD/mW
Cache
Size
NR
(c) LUTs and Pd (d) Cache Size and NR
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The number of RAMB36E1’s
(NR36E1) and the number of
RAMB18E1’s (NR18E1) are mainly
decided by total cache size.
(d) illustrates the relationship
between equivalent RAM blocks
(NR) and the total cache size,
where NR = 2 × NR36E1 + NR18E1.
The values of NR vary directly
with the total size of caches.
Xilinx Virtex-7 FPGA
23
中国科学院电子学研究所
1000 2000 3000 4000 5000 6000 7000500
1000
1500
2000
2500
3000
3500
1000 2000 3000 4000 5000 6000 70000
10
20
30
40
50
60
70
80
90
MicroBlaze
2 3 4 5 6 7 8100
150
200
250
0 5 10 15 20 25 30 35
0
10
20
30
40
50
Amber23 Amber25 LM32 OR1200 LEON3 Altor32
(a) Logic Resources Utilization (b) Pipeline depth and Fmax
LUTs
Regs
Pipeline
Depth
Fmax/MHz
LUTs
PCD/mW
Cache
Size
NR
(c) LUTs and Pd (d) Cache Size and NR
Introduction
Overview of Open Source Soft Processors
Selection of Open Source Processors
Implementations and Comparisons
Discussions and Conclusion
01
02 03 04 05
A Survey of Open Source Processors for
FPGAs CONTENTS
Institute of Electronics, Chinese Academy of Sciences, Beijing China
24
中国科学院电子学研究所
Institute of Electronics, Chinese Academy of Sciences, Beijing China
Discussions: Based on the implementation results in last section, we discuss the two different categories of
processors, open source versus commercial.
1. Open Source or Not?
Commercial soft cores Commercial soft cores:
reduce logic utilization, dynamic
power consumption and CAD tool
run-time;
achieve high performance
The configuration of them is
flexible.
EDA tools from FPGA venders
provide many configuration choices
Open source processors free to access the source code
with excellent usability
explore the strategies of
optimizations for research and
engineering.
open source processors can be
chosen to accelerate applications
requiring deep customizations.
25
中国科学院电子学研究所
Institute of Electronics, Chinese Academy of Sciences, Beijing China
Discussions: Based on the implementation results in last section, we discuss the two different categories of
processors, open source versus commercial.
2. Implementation
26
中国科学院电子学研究所
Commercial soft cores are superior to open source processors
in logic utilization.
The maximum frequency of commercial soft cores which are
optimized by venders are higher than open source processors.
The on-chip memory utilization depends on the total cache size.
Institute of Electronics, Chinese Academy of Sciences, Beijing China
Discussions: Based on the implementation results in last section, we discuss the two different categories of
processors, open source versus commercial.
3. Configurability and Conveniency
Commercial soft cores
All designed using user-friendly
EDA tools from FPGA vendors.
Soft cores with great configurability
and lots of optimized IPs are avaiavle.
Systems can be constructed with a
suitable soft core, minimal peripherals
and highly optimized hardware.
Open source processors Advantages of customization and
exploration for optimization in
engineering and research.
Engineers and researchers can
experiment and verify any possible
methods for their deep customized
optimizations.
27
中国科学院电子学研究所
Institute of Electronics, Chinese Academy of Sciences, Beijing China
Conclusion :
Processor should be designed, verified, tested and shared in module
level to increase the design productivity.
From the points of usability and stability, a selection process of open
source processors is presented.
The selected open source processors and existing commercial soft
processors are implemented, compared and discussed.
Based on the optimization for their own FPGAs, commercial soft
cores are superior to open source processors in logic utilization and
performance.
Open source processors with excellent usability and flexibility can be
used to explore the strategies of optimizations for research and
engineering. 28
中国科学院电子学研究所
Institute of Electronics, Chinese Academy of Sciences, Beijing China
29
中国科学院电子学研究所
Suggestions and discussions are welcome by email:
yanghg@mail.ie.ac.cn
Thank you!
中国科学院电子学研究所Institute of Electronics, Chinese Academy of Sciences, Beijing China
Implementations and Comparisons on Altera Stratix V FPGA
S1 and LEON2 need much more ALMs, registers
and total block memory bits than all other processors,
and the maximum frequency of S1 is the lowest.
811
1347
44,544
297.89
288.68
1734.5
16.56
42.36
1793.42
35s
17min19s
Nios II/f
590
862
27,200
260.48
250.38
1733.87
12.28
42.50
1788.66
15s
16min12s
Nios II/s
25min35s
409
591
10,240
367.51
337.04
1733.48
10.46
41.91
1785.85
15s
Nios II/e
ALMs
REGs
TBMB / bits
Fmax(100℃)/MHz
PCS / mW
PCD / mW
PI/O / mW
Pt / mW
TA&S
TF
3073
1875
152,575
84.73
83.08
1738.22
48.44
36.13
1822.78
4min16s
20min35s
Fmax(-40℃)/MHz
Amber23
5278
3221
305,664
96.11
96.15
1744.96
90.38
62.51
1897.85
7min3s
23min19s
Amber25
2141
2468
52,736
179.92
171.14
1735.37
24.13
48.38
1807.87
1min22s
29min17s
LM32
39519
55061
270,432
52.32
56.15
1751.5
369.47
50.25
2171.22
12min52s
1h27min27s
S1
2428
1191
156,288
110.3
107.4
1737.05
30.22
56.56
1823.84
1min12s
20min45s
OR1200
1239
1272
8,704
212.27
209.95
1733.99
13.31
43.31
1790.61
38s
17min47s
LEON3
2014
1754
69,632
94.64
91.99
1735.08
17.71
43.98
1796.77
1min44s
29min35s
AltOR32
5678
10546
72704
158.5
158.55
1738.29
61.56
35.90
1835.75
1min35s
34min36s
LEON2
中国科学院电子学研究所Institute of Electronics, Chinese Academy of Sciences, Beijing China
Implementations and Comparisons on Xilinx Virtex-7 FPGA
Dual-core MicroBlaze needs almost twice of the
resources of the single-core version.
MicroBlaze can be implemented with less LUTs and
registers than all open source processors.
LEON3 needs the least resources in all selected
open source processors.
The LUTs and registers of MicroBlaze is 41% and
58% of the averages of all open source processors.
3507
2485
2
0
216.92
487
14
501
2min3s
4min3s
MicroBlaze/dual
1491
1114
2
0
233.1
487
12
499
1min8s
3min15s
MicroBlaze/single
LUTs
Regs
Mem
Ps / mW
Pd / mW
Pt/mW
TS&T
TF&P
3274
2306
8
4
114.59
429
23
452
1min20s
5min45s
Fmax(25℃)/MHz
Amber23
6592
3409
16
8
117.40
435
83
519
1min45s
7min57s
Amber25
3281
2233
4
0
204.3
428
18
446
15s
4min24s
LM32
56690
38028
48
17
65.77
476
489
965
11min41s
38min37s
S1
3669
1276
4
2
143.37
431
44
475
1min37s
6min15s
OR1200
2522
1144
0
2
238.83
431
44
474
1min20s
4min26s
LEON3
2742
1629
2
1
113.27
430
37
467
1min55s
7min39s
AltOR32
NR36E1
NR18E1
3674
1559
2
3
192.82
430
34
464
1min21s
4min42s
LEON2