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EC6311 Analog and Digital Lab
Semester 03 Department of ECE Rajalakshmi Institute of Technology Page 1
RAJALAKSHMI INSTITUTE OF TECHNOLOGY
CHENNAI 600 124
DEPARTMENT
of
ELECTRONICS AND COMMUNICATION ENGINEERING
Regulation 2013
Academic Year: 2014-2015
EC6311 ANALOG AND DIGITAL LABORATORY
STUDENT MANUAL
Faculty In-charge
Mr.S.Rajalingam /AP/ECE
Mr.L.Franklin Telfer/AP/ECE
Mr.V.S.Vignesh/AP/ECE
Lab Assistant
Ms.T.Jeevitha
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SYLLABUS
EC6311 ANALOG AND DIGITAL CIRCUITS LABORATORY
LIST OF EXPERIMENTS
LIST OF ANALOG EXPERIMENTS:
1. Frequency Response of CE / CB / CC amplifier
2. Frequency response of CS Amplifiers
3. Darlington Amplifier
4. Differential Amplifiers- Transfer characteristic.
5. CMRR Measurement
6. Cascode / Cascade amplifier
7. Determination of bandwidth of single stage and multistage amplifiers
8. Spice Simulation of Common Emitter and Common Source amplifiers
LIST OF DIGITAL EXPERIMENTS
9. Design and implementation of code converters using logic gates
(i) BCD to excess-3 code and vice versa (ii) Binary to gray and vice-versa
10. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483
11. Design and implementation of Multiplexer and De-multiplexer using logic gates
12. Design and implementation of encoder and decoder using logic gates
13. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters
14. Design and implementation of 3-bit synchronous up/down counter
15. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops
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SL NO LIST OF EXPERIMENTS
LIST OF ANALOG EXPERIMENTS
Introduction
- Study of electronic components [ Active and Passive]- Study of Signal Generator, CRO, Bread board and Regulated Power supply
- Study of transistor parameters using Transistor Data Sheets
1.
Design and Analysis of Common Emitter Amplifier
- To Determine a. DC characters tics b. AC characteristics c. Gain d. Bandwidth
e. Gain- Bandwidth Product f. SPICE Simulation of Amplifier(Additional)
2.
Design and Analysis of Common Collector Amplifier
- To Determine a. DC characteristics b. AC characteristics c. Gain d. Bandwidth
e. Gain- Bandwidth Product f. SPICE Simulation of Amplifier(Additional)
3.
Design and Analysis of Common Base Amplifier
- To Determine a. DC characteristics b. AC characteristics c. Gain d. Bandwidth
e. Gain- Bandwidth Product f. SPICE Simulation of Amplifier(Additional)
4.
Design and Analysis of Darlington Amplifier
- To Determine a. DC characteristics b. AC characteristics c. Gain d. Bandwidth
e. Gain- Bandwidth Product f. SPICE Simulation of Amplifier(Additional)
5.
Design and Analysis of Common Source Amplifier
- To Determine a. DC characteristics b. AC characteristics c. Gain d. Bandwidth
e. Gain- Bandwidth Product f. SPICE Simulation of Amplifier (Additional)
6.
Design and Analysis of Cascade Amplifier
- To Determine a. DC characteristics b. AC characteristics c. Gain d. Bandwidth
e. Gain- Bandwidth Product f. SPICE Simulation of Amplifier (Additional)
7.
Design and Analysis of Cascode Amplifier
- To Determine a. DC characteristics b. AC characteristics c. Gain d. Bandwidth
e. Gain- Bandwidth Product f. SPICE Simulation of Amplifier (Additional)
8.
Design and Analysis of Differential Amplifier
- To Determine a. Transfer characteristics b. CMRR
9.
Pspice Simulation of Common Emitter Amplifier
a. Gain b. Bandwidth
10.
Pspice Simulation of Common source Amplifier
a. Gain b. Bandwidth
LIST OF DIGITAL EXPERIMENTS
Introduction
- Study of Digital IC's using IC data sheets
- Study of IC trainer Kit
11.
Design and implementation of code converters using logic gates
(i) BCD to excess-3 code and vice versa (ii) Binary to gray and vice-versa
12. Design and implementation of 4 bit binary Adder/ Subtractor and
BCD adder using IC 7483
13.
Design and implementation of Multiplexer and De-multiplexer using logic gates
14. Design and implementation of encoder and decoder using logic gates
15.
Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters
16. Design and implementation of 3-bit synchronous up/down counter
17.
Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops
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INDEX
S.No Date Experiment Names Pg No Faculty Sign
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
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Common Emitter Amplifier circuit diagram
CE Amplifier without Feedback :
CE Amplifier with Feedback:
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COMMON EMITTER AMPLIFIER
EXPERIMENT: 01 DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using voltage divider bias and to
determine its:
a.
DC Characteristics
b.
Maximum Signal Handling Capacity
c. Gain of the amplifier
d. Bandwidth of the amplifier
e.
Gain -Bandwidth Product
2.
REQUIREMENTS:
S.no Requirement Name Range Quantity
1
Components
Transistor [Active] BC 107 1
2 Resistor [Passive]61kΩ, 10kΩ, 1kΩ,
4.7kΩ 1,1,1,2
3 Capacitor [Passive] 10µf, 100µf 2,1
4
Equipment
Signal Generator (0-3)MHz 1
5 CRO 30MHz 1
6Regulated power
supply(0-30)V 1
7
Accessories
Bread Board - 1
8 Connecting Wires Single strand as required
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DESIGN PROCEDURE:
Given specifications:
VCC= 10V, IC=1.2mA, AV= 30, hFE= 100
(i) To calculate RC:
The voltage gain is given by,
AV= -hfe (RC|| RF) / hie
h ie = β re
re = 26mV / IE = 26mV / 1.2mA = 21.6Ω
hie = 150 x 21.6 =3.2KΏ
Apply KVL to output loop,
VCC= IC RC + VCE+ IE RE ----- (1)
Where VE = IE RE (IC= IE)
VE= VCC / 10= 1V
Therefore RE= 1/1.2x10-3=0.8K= 1KΏ
VCE= VCC/2= 5V
From equation (1), RC= ( Vcc - VCE - IE RE / IC ) = ________
(ii) To calculate R1&R2:
S=1+ (RB/RE)Where RE = 1 KΏ and S = 9
RB= (S-1) RE= (R1 || R2) =1KΏ
RB=( R 1R2 ) /( R1+ R2) ------- (2)
VB= VBE + VE = 0.7+ 1= 1.7V
VB= VCC (R2 / R1+ R2 )------- (3)
Solving equation (2) & (3),
R1= ____ & R2= ______
(iii) Input coupling capacitor :
Xci= Rif / 10= 2.4 Ω (since XCi
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3. THEORY:
A common emitter amplifier is type of BJT amplifier which increases the voltage level of the
applied input signal Vin at output of collector.
The CE amplifier typically has a relatively high input resistance (1 - 10 KΩ) and a fairly high
output resistance. Therefore it is generally used to drive medium to high resistance loads. It is
typically used in applications where a small voltage signal needs to be amplified to a large
voltage signal like radio receivers.
The input signal Vin is applied to base emitter junction of the transistor and amplifier output
Vo is taken across collector terminal. Transistor is maintained at the active region by using the
resistors R1,R2 and Rc. A very small change in base current produces a much larger change in
collector current. The output Vo of the common emitter amplifier is 180 degrees out of phase
with the applied the input signal Vin.
4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CE amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier using AC analysis.
4. Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 0Hz to 1MHz in
incremental steps and note down the corresponding output voltage Vo for at least 20
different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi) dB
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking
frequency on x-axis and gain in dB on y-axis.,
Bandwidth, BW = f 2-f 1
where f 1 lower cut-off frequency
f 2 upper cut-off frequency
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a. DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
i)
Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
ii)
Open circuit the capacitors since it blocks DC voltage
iii) Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
iv)
Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
1. VBE : (forward bias)
2. VRC = ____________
3. VCE = _______ (REVERSE BIAS)
4. Ic( Ic = (Vcc – VCE ) / Rc) =________
Q point analysis:
It is the procedure to choose the opearating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
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b. Maximum signal handling capacity :
It is the process to find the maximum input voltage that can be handled by the
amplifier, so that it amplifies the input signal without any distortion.
Procedure:
i. Apply input signal Vin = 20 mV of 1Khz frequency to the amplifier using the
signal generator between base emitter junction of the transistor. Find the
sinusoidal output using CRO across RL.
ii. By increasing the amplitude of the input signal find maximum input voltage
V MSH across VBE at which the sinusoidal signal gets distorted during the
process which can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
MODEL GRAPH:
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5. TABULATION [Without Feedback ] :
Input voltage (Vin=V MSH/2) =____________V
S. NO FREQUENCY [Hz]OUTPUT VOLTAGE [ VO]
in Volts
GAIN= 20 log Vo/Vin
dB
1. 0
2. 100
3. 500
4. 600
5. 800
6. 900
7. 1 KHz
8. 100 KHz
9. 500 KHz
10. 600 KHz
11. 700 KHz
12. 800 KHz
13.
900 KHz
14. 1 MHz
15. 1.1 MHz
16. 1.5 MHz
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With Feedback :
Input voltage (Vin=V MSH/2) =____________ V
S. NO FREQUENCY [Hz] OUTPUT VOLTAGE [
VO] in Volts
GAIN= 20 log ( vo/vin )
dB
1.
0
2. 100
3. 500
4. 600
5. 800
6. 900
7. 1 KHz
8. 100 KHz
9. 500 KHz
10. 600 KHz
11. 700 KHz
12. 800 KHz
13.
900 KHz
14. 1 MHz
15. 1.1 MHz
16. 1.5 MHz
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WORKSHEET
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6.
RESULT:
INFERENCE:
The Common Emitter Amplifier was constructed and the following results were determined:
a) Gain of the amplifier :
b)
Bandwidth of the amplifier :
c) Gain-Bandwidth product :
CONCLUSION:
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Common Collector Amplifier Circuit Diagram:
MODEL GRAPH:
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COMMON COLLECTOR AMPLIFIER
EXPERIMENT: 02 DATE:
1. OBJECTIVE:
To Design and Construct a Common collector Amplifier and to determine its:
a. DC Characteristics
b.
Maximum Signal Handling Capacity
c.
Gain of the amplifier
d. Bandwidth of the amplifier
e. Gain -Bandwidth Product using frequency response curve
2. REQUIREMENTS:
S.No Requirement Name Range Quantity
1
Components
Transistor [Active] BC 107 1
2 Resistor [Passive]
3 Capacitor [Passive]
4
Equipment
Signal Generator 0-3MHz 1
5 CRO 0-30MHz 1
6 Regulated power supply 0-30 V 1
7
Accessories
Bread Board - 1
8 Connecting Wires Single strand as required
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Design of Common collector amplifier:
Given specifications:
VCC= 15V, IC=1.2mA, hie = 2.1kΩ hFE= 75 hib= 27.6Ω
(i)
To calculate Zb ( Device input impedance )
Zb = hie + hfe ( RE || RL)
Assume RE = 4.7 KΩ and RL= 3.3 KΩ
Zb = 2.1k + 75 (4.7 K || 3.3 K) = __________
(ii) To calculate Zi ( Input Impedance )
Zi = R1 || R2 || Zb
Assume R1= R2= 10k Ω
Zi = _______
(iii) To Calculate Voltage gain Av :
Av = [ ( RE || RL ) / ( hib + ( RE || RL) ) ]
Av = _____
3. THEORY:
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A common collector amplifier is a unity gain BJT amplifier used for impedance matching and as
a buffer amplifier.
Circuit Operation : When a positive half-cycle of the input signal is applied to Base emitter
junction of transistor the forward bias voltage Vbe is increased, which in turn increases the base
current Ib of transistor. Since emitter current Ie is directly proportional to Ib the voltage drop across
the Emitter Ve= IeRe is increased, hence, output voltage Vo is increased, thus, we get positive half-
cycle of the output. It means that a positive-going input signal results in a positive going output
signal and, consequently, the input and output signals are in phase with each other. Similarly the
negative half cycle of input signal produces negative going output signal.
Characteristics of a CC Amplifier
1. high input impedance (20-500 K Ω)
2. low output impedance (50-1000 Ω)
3. high current gain of (1 + β) i.e. 50 – 500
4. voltage gain of less than 1 (unity)
5. power gain of 10 to 20 dB
6. no phase reversal of the input signal
4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CE amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier using AC analysis.
3. Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 0Hz to 1MHz in
incremental steps and note down the corresponding output voltage Vo for at least 15
different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vin)
7. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking
frequency on x-axis and gain in dB on y-axis.,
Bandwidth, BW = f 2-f 1
Where f 1 - lower cut-off frequency
f 2 - upper cut-off frequency
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a. DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
i)
Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
ii) Open circuit the capacitors since it blocks DC voltage
iii)
Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
iv)
Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
1. VBE : (forward bias)
2. VRC = ____________
3. VCE = _______ (REVERSE BIAS)
4. Ic( Ic = (Vcc – VCE ) / Rc) =________
Q point analysis:
It is the procedure to choose the opearating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
b. Maximum signal handling capacity :
It is the process to find the maximum input voltage that can be handled by the
amplifier, so that it amplifies the input signal without any distortion.
Procedure:
i. Apply input signal Vin = 1 V of 1Khz frequency to the CC amplifier using the
signal generator between base emitter junction of the transistor. Find thesinusoidal output using CRO across RL.
ii. By increasing the amplitude of the input signal find maximum input voltage
V MSH across VBE at which the sinusoidal signal gets distorted during the
process which can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
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5. TABULATION
Input voltage (Vin=V MSH /2) =____________ volts
S. NO
FREQUENCY
[Hz]
OUTPUT VOLTAGE
[ VO] in VoltsGAIN= 20 log vo/vin dB
1. 0
2. 100
3. 500
4. 600
5. 800
6. 900
7. 1 KHz
8. 100 KHz
9.
500 KHz
10. 600 KHz
11. 700 KHz
12. 800 KHz
13. 900 KHz
14. 1 MHz
15. 1.1 MHz
16. 1.5 MHz
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WORKSHEET
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6. RESULT:
INFERENCE:
The common collector amplifier was constructed and input resistance and gain were determined.
The results are found to be as given below
a) Gain of the amplifier (in dB) :
b) Bandwidth of the amplifier (in Hz) :
c)
Gain-Bandwidth product (GBWP) :
CONCLUSION:
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Common Base Amplifier Circuit Diagram:
MODEL GRAPH:
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COMMON BASE AMPLIFIER
EXPERIMENT:03 DATE:
1.
OBJECTIVE:
To Design and Construct a Common Base Amplifier and to determine its:
a.
DC Characteristics
b. Maximum Signal Handling Capacity
c. Gain of the amplifier
d.
Bandwidth of the amplifier
e. Gain -Bandwidth Product using frequency response curve
2.
REQUIREMENTS:
S.No. Requirement Name Range Quantity
1
Components
Transistor [Active] BC 107 1
2 Resistor [Passive]
3 Capacitor [Passive]
4
Equipment
signal Generator (0-3)MHz 1
5 CRO 30MHz 1
6 Regulated power supply (0-30)V 1
7
Accessories
Bread Board - 1
8Connecting Wires Single strand as required
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DESIGN PROCEDURE:
Given Transistor specifications:
hie = 2.1kΩ ; hfe = 75 ; hfb =0.987
i) To find Device input impedance :
hib = ( hie / (1+ hfe))
hib = ____
ii) To find Circuit input impedance (Zi) :
Zi = hib || Re ,Where Re= 2.2 kΩ
Zi = _____
iii) To find Circuit output impedance (Zo) :
Zo = Rc ; where Rc = 4.7 kΩ
iv) To find Voltage Gain (Av) :
Av = [ hfb (Rc || RL) / hib ]
Where RL= 10kΩ
Av = _____
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3.
THEORY:
A common base amplifier is type of BJT amplifier which increases the voltage level of the
applied input signal Vin at output of collector.
The Common base amplifier typically has good voltage gain and relatively high output
impedance. But the Common base amplifier unlike CE amplifier has very low input impedance which
makes it unsuitable for most voltage amplifier. It is typically used used as an active load for a
cascode amplifier and also as a current follower circuit.
Circuit Opeartion:
A positive-going signal voltage at the input of a CB pushes the transistor emitter in a positive
direction while the base voltage remains fixed, hence Vbe reduces. The reduction in VBE results in
reduction in VRC
, consequently VCE
increases. The rise in collector voltage effectively rises the output
voltage. The positive going pulse at the input produces a positive-going output, hence the there is no
phase shift from input to output in CB circuit. In the same way the negative-going input produces a
negative-going output.
4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CB amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier using
AC analysis.
4.
Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 0Hz to 1MHz in
incremental steps and note down the corresponding output voltage Vo for atleast 20
different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi)
5. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking
frequency on x-axis and gain in dB on y-axis.,
Bandwidth, BW = f 2-f 1
where f 1 lower cut-off frequency
f 2 upper cut-off frequency
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a.
DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
i) Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
ii) Open circuit the capacitors since it blocks DC voltage
iii) Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
iv) Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
1. VBE : (forward bias)
2. VRC = ____________
3. VCE = _______ (REVERSE BIAS)
4. Ic( Ic = (Vcc – VCE ) / Rc) =________
Q point analysis:
It is the procedure to choose the opearating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
b. Maximum signal handling capacity :
It is the process to find the maximum input voltage that can be handled by the
amplifier, so that it amplifies the input signal without any distortion.
Procedure:
i. Apply input signal Vin = 20 mV of 1Khz frequency to the amplifier using the
signal generator between base emitter junction of the transistor. Find thesinusoidal output using CRO across RL.
ii. By increasing the amplitude of the input signal find maximum input voltage
V MSH across VBE at which the sinusoidal signal gets distorted during the
process which can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
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5. TABULATION
Input voltage (Vin=V MSH / 2) =____________V
S. NO FREQUENCY
[Hz]
OUTPUT VOLTAGE
[ VO] in Volts
GAIN= 20 log Vo/ vin
dB
17. 0
18. 100
19. 500
20. 600
21. 800
22. 900
23. 1 KHz
24. 100 KHz
25. 500 KHz
26. 600 KHz
27. 700 KHz
28. 800 KHz
29. 900 KHz
30. 1 MHz
31.
1.1 MHz
32. 1.5 MHz
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WORKSHEET
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6.
RESULT:
INFERENCE:
The Common base amplifier was constructed and input resistance and gain were determined. The
results are found to be as given below
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
CONCLUSION:
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Darlington Amplifier Circuit Diagram:
MODEL GRAPH:
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DARLINGTON AMPLIFIER
EXPERIMENT:04 DATE:
1.
OBJECTIVE:
To Design and Construct a BJT amplifier using Darlington pair and to determine its:
a.
DC Characteristics
b. Maximum Signal Handling Capacity
c. Gain of the amplifier
d.
Bandwidth of the amplifier
e. Gain -Bandwidth Product using frequency response curve
2. REQUIREMENTS:
S.No. Requirement Name Range Quantity
1
Components
Transistor [Active] BC 107 1
2 Resistor [Passive]
3 Capacitor [Passive]
4
Equipment
signal Generator (0-3)MHz 1
5 CRO 30MHz 1
6 Regulated power supply (0-30)V 1
7
Accessories
Bread Board - 1
8Connecting Wires Single strand as required
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DESIGN PROCEDURE:
Given specifications:
VCC= 12V, IC=1.2mA, AV= 30, f 1 = 300 HZ, f 2 = 500KHZ, hFE= 150
(i) To calculate RC:
Assume R2 = 10KΩ and Ic = 1mA.
Since voltage amplification is done in the Darlington transistor amplifier circuit, we assume
equal drops across VCE and load resistance RC. The ICQ = 1mA is assumed.
Drop across Re is assumed to be 1V.
The drop across VCE with a supply of 1.2 V is given by
12 – 1 = 1V.
It is equal to VRC & VCE = 5.5V x RC
Therefore, Rc = 5.5 KΩ (4.7 KΩ) ; IC = 1mA
(ii) To calculate R1&R2:
S=1+ (RB/RE)
RB= (S-1) RE= (R1 || R2) =1KΏ
RB=( R 1R2 ) /( R1+ R2) ------- (2)
VB= VBE + VE = 0.7+ 1= 1.7VVB= VCC (R2 / R1+ R2 )------- (3)
Solving equation (2) & (3),
Since R2=10kΩ , the other resistor is found to be, R1= 47kΩ
(iii) To Find Cin :
Cin = * 1 / 2πf 1 (Zi / 10) ]
Where Zi = ( RB || hie ) = 1.1KΩ and
f 1 = Lower cut-off frequency= 25HZ
= 57.9µF
(iv) To Find CO :
C0 = * 1 / 2πf 2 ( (RC + RL) / 10) ]
Where RC = 9KΩ; RL = 90KΩ and
f 2 = Upper cut-off frequency= 500KHZ
= 64 µF
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3. THEORY:
The Darlington transistor (often called a Darlington pair) is compound structure consisting of
two bipolar transistors connected in such a way that the First transistor does current
amplification of input signal and then it will be fed to the second transistor which performs
voltage amplification.
This configuration gives a much higher gain than each transistor taken separately and, in the
case of integrated devices, can take less space than two individual transistors because they can use
a shared collector. The Darlington amplifier typically has a relatively high input resistance (1 - 10 KΩ)
and a fairly high output resistance. Therefore it is generally used to drive medium to high resistance
loads. It is typically used in applications where a small voltage signal needs to be amplified to a large
voltage signal like radio receivers.
4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the Darlington amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to Darlington amplifier using AC
analysis.
4.
Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 0Hz to 1MHz in
incremental steps and note down the corresponding output voltage Vo for at least 20
different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi)
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking
frequency on x-axis and gain in dB on y-axis.,
Bandwidth, BW = f 2-f 1
where f 1 - lower cut-off frequency
f 2 - upper cut-off frequency
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http://en.wikipedia.org/wiki/Bipolar_transistorhttp://en.wikipedia.org/wiki/Gainhttp://en.wikipedia.org/wiki/Gainhttp://en.wikipedia.org/wiki/Bipolar_transistor
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a.
DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
i) Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
ii) Open circuit the capacitors since it blocks DC voltage
iii) Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
iv) Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
1. VBE : (forward bias)
2. VRC = ____________
3. VCE = _______ (REVERSE BIAS)
4. Ic( Ic = (Vcc – VCE ) / Rc) =________
Q point analysis:
It is the procedure to choose the opearating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
b. Maximum signal handling capacity :
It is the process to find the maximum input voltage that can be handled by the
amplifier, so that it amplifies the input signal without any distortion.
Procedure:
i. Apply input signal Vin = 20 mV of 1Khz frequency to the amplifier using the
signal generator between base emitter junction of the transistor. Find the
sinusoidal output using CRO across RL.
ii.
By increasing the amplitude of the input signal find maximum input voltage
V MSH across VBE at which the sinusoidal signal gets distorted during the
process which can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
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5. TABULATION
Input voltage (Vin=V MSH/2) =____________ V
S. NO FREQUENCY[Hz]
OUTPUT VOLTAGE
[ VO] in Volts
GAIN= 20 log Vo/Vin
dB
1. 0
2. 100
3. 500
4. 600
5. 800
6. 900
7. 1 KHz
8. 100 KHz
9. 500 KHz
10.
600 KHz
11. 700 KHz
12. 800 KHz
13. 900 KHz
14. 1 MHz
15. 1.1 MHz
16. 1.5 MHz
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WORKSHEET
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6. RESULT:
INFERENCE:
The Darlington amplifier was constructed and the results are found to be
a. Gain of the amplifier :
b.
Bandwidth of the amplifier :
c.
Gain-Bandwidth product :
CONCLUSION:
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Common Source Amplifier Circuit Diagram:
MODEL GRAPH:
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COMMON SOURCE AMPLIFIER
EXPERIMENT:05 DATE:
1. OBJECTIVE:
To Design and Construct a Common source amplifier using the bootstrapped gate resistance
and to determine its:
a. DC Characteristics
b.
Maximum Signal Handling Capacity
c. Gain of the amplifier
d. Bandwidth of the amplifier
e.
Gain -Bandwidth Product
2. REQUIREMENTS:
S.No. Requirement Name Range Quantity
1
Components
Transistor [Active] BFW10 1
2 Resistor [Passive]
3 Capacitor [Passive]
4
Equipment
signal Generator (0-3)MHz 1
5 CRO 30MHz 1
6 Regulated power supply (0-30)V 1
7
Accessories
Bread Board - 1
8Connecting Wires Single strand as required
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DESIGN ANALYSIS :
Given :
VDD = 20 V, IDSS = 5mA, ID = 1.5 mA,
i) To Find the voltage across the Gate-source region (VGS)
VGS = ID RS
Assume RS = 3.3KΩ,
VGS = 1.5mA x 3.3KΩ = _____
ii) To find Voltage Across Drain to Source (VDS)
VDS= VDD - ID ( RD + Rs) ; Where RD= 3.3 KΩ
= 20V – 1mA ( 3.3 KΩ + 3.3 KΩ)
= ________
iii) To Find input impedance :
Zi = RG ; Assume RG = 1MΩ
iv) To Find output impedance :
ZO = RD ||
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3. THEORY
There are three basic types of FET amplifier or FET transistor namely common source
amplifier, common gate amplifier and source follower amplifier.
The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a
voltage amplifier.
i) As a transconductance amplifier, the input voltage is seen as modulating the current going
to the load.
ii) As a voltage amplifier, input voltage modulates the amount of current flowing through the
FET, changing the voltage across the output resistance according to Ohm's law.
However, the FET device's output resistance typically is not high enough for a reasonable
transconductance amplifier (ideally infinite), nor low enough for a decent voltage amplifier (ideally
zero). Another major drawback is the amplifier's limited high-frequency response. Therefore, in
practice the output often is routed through either a voltage follower (common-drain or CD stage), or
a current follower (common-gate or CG stage), to obtain more favorable output and frequency
characteristics
4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CS amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier using
AC analysis.
4.
Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 0Hz to 1MHz in
incremental steps and note down the corresponding output voltage Vo for atleast 20
different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi)
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph takingfrequency on x-axis and gain in dB on y-axis.,
Bandwidth, BW = f 2-f 1
where f 1 - lower cut-off frequency
f 2 - upper cut-off frequency
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http://en.wikipedia.org/wiki/Ohm%27s_lawhttp://en.wikipedia.org/wiki/Electronic_amplifier#Input_and_output_variableshttp://en.wikipedia.org/wiki/Electronic_amplifier#Input_and_output_variableshttp://en.wikipedia.org/wiki/Electronic_amplifier#Input_and_output_variableshttp://en.wikipedia.org/wiki/Common-drainhttp://en.wikipedia.org/wiki/Common-gatehttp://en.wikipedia.org/wiki/Common-gatehttp://en.wikipedia.org/wiki/Common-drainhttp://en.wikipedia.org/wiki/Electronic_amplifier#Input_and_output_variableshttp://en.wikipedia.org/wiki/Electronic_amplifier#Input_and_output_variableshttp://en.wikipedia.org/wiki/Electronic_amplifier#Input_and_output_variableshttp://en.wikipedia.org/wiki/Ohm%27s_law
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a.
DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
i) Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
ii)
Open circuit the capacitors since it blocks DC voltage
iii) Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
iv) Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
1. VGS : = ____________
2. VDS = ____________
3 ID = _______
b. Maximum signal handling capacity :
It is the process to find the maximum input voltage that can be handled by the
amplifier, so that it amplifies the input signal without any distortion.
Procedure:
i. Apply input signal Vin = 1 V of 1Khz frequency to the CS amplifier using the
signal generator between base emitter junction of the transistor. Find the
sinusoidal output using CRO across RL.
ii. By increasing the amplitude of the input signal find maximum input voltage
V MSH across VBE at which the sinusoidal signal gets distorted during the
process which can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
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5.
TABULATION
Input voltage (Vin=V MSH/2) =____________V
S. NO FREQUENCY
[Hz]
OUTPUT VOLTAGE [
VO] in Volts
GAIN= 20 log Vo/Vin
dB
1. 0
2. 100
3. 500
4. 600
5. 800
6. 900
7. 1 KHz
8. 100 KHz
9. 500 KHz
10. 600 KHz
11. 700 KHz
12. 800 KHz
13. 900 KHz
14. 1 MHz
15.
1.1 MHz
16. 1.5 MHz
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WORKSHEET
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6. RESULT:
INFERENCE:
The common Source amplifier was constructed and input resistance and gain were determined. The
results are found to be as given below
a) Gain of the amplifier (in db) :
b) Bandwidth of the amplifier (in HZ) :
c) Gain-Bandwidth product (GBWP) :
CONCLUSION:
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Cascade amplifier Circuit Diagram:
MODEL GRAPH:
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CASCADE AMPLIFIER
EXPERIMENT:06 DATE:
1. OBJECTIVE:
To Design and Construct a Cascade Amplifier and to determine its:
a.
DC Characteristics
b. Maximum Signal Handling Capacity
c.
Gain of the amplifier
d. Bandwidth of the amplifier
e. Gain -Bandwidth Product
2. REQUIREMENTS:
S.No. Requirement Name Range Quantity
1
Components
Transistor [Active] BC 107 1
2 Resistor [Passive]
3 Capacitor [Passive]
4Equipment
signal Generator (0-3)MHz 1
5 CRO 30MHz 1
6 Regulated power supply (0-30)V 1
7
Accessories
Bread Board - 1
8
Connecting Wires Single strand as required
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DESIGN PROCEDURE:
Given specifications:
VCC= 14 V, IC1=1.2mA, RL = 40KΏ hFE= 100
(i) To calculate R5 :
Assume VE1 = 5V , VCE1 = VCE2 = 3V;
VB2 = VC1 = VE1 + VCE1 = 5V + 3V = 8V
VE2 = VB2 – VBE = 8V – 0.7V = 7.3V
VR5 = Vcc – VE2 – VCE2 = 14V – 7.3V – 3V = 3.7V
Choose R5 = R
L / 10 = 40KΩ / 10 = 4KΩ ;
IC2 = ( VR5 / R5 ) = 3.7V / 3.9KΩ = 1000µA
(ii) To calculate R6 :
VR6 = VE2 / IC2 = 7.7KΩ;
IC2 = VE2 / R6 = 7.3V / 8.2 KΩ = 890µA
(iii) To calculate R1, R2 , R3 & R4:
Voltage across resistor R3 is given by
VR3 = Vcc – VC1 = 14V – 8V = 6V
R3 = VR3 / IC1 = 6V / 1mA = 6KΩ
R4 = VE1 / IC1 = 5V/ 1mA = 4.7KΩ
Voltage across resistor R2 is given by
VR2 = VE1 – VBE = 5V + 0.7V =5.7V
R2 = 10 R4 = 4.7 KΩ
VR1 = VCC – VB1 = 14V + 5.7V =8.3V
R1 = [ VR1 x R2 / VR2] = 68.4 KΩ
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3. THEORY:
A cascade is type of multistage amplifier where two or more single stage amplifiers are
connected serially. Many times the primary requirement of the amplifier cannot be achieved with
single stage amplifier, because Of the limitation of the transistor parameters. In such situations morethan one amplifier stages are cascaded such that input and output stages provide impedance
matching requirements with some amplification and remaining middle stages provide most of the
amplification. These types of amplifier circuits are employed in designing microphone and
loudspeaker.
4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to amplifier using AC analysis.
4.
Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 0Hz to 1MHz in
incremental steps and note down the corresponding output voltage Vo for atleast 20
different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi)
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking
frequency on x-axis and gain in dB on y-axis.,
Bandwidth, BW = f 2-f 1
where f 1 - lower cut-off frequency
f 2 - upper cut-off frequency
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a.
DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
v) Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
vi) Open circuit the capacitors since it blocks DC voltage
vii) Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
viii) Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
1. VBE : (forward bias)
2. VRC = ____________
3. VCE = _______ (REVERSE BIAS)
4. Ic( Ic = (Vcc – VCE ) / Rc) =________
Q point analysis:
It is the procedure to choose the opearating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
b. Maximum signal handling capacity :
It is the process to find the maximum input voltage that can be handled by the
amplifier, so that it amplifies the input signal without any distortion.
Procedure:
iii. Apply input signal Vin = 20 mV of 1Khz frequency to the amplifier using the
signal generator between base emitter junction of the transistor.Find the
sinusoidal output using CRO across RL.
iv.
By increasing the amplitude of the input signal find maximum input voltage
V MSH across VBE at which the sinusoidal signal gets distorted during the
processwhich can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
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5.
TABULATION
Input voltage (Vin=V MSH/2) =____________ volts
S. NO FREQUENCY
[Hz]
OUTPUT VOLTAGE
[ VO] in Volts
GAIN= 20 log Vo/Vin
dB
1. 0
2. 100
3. 500
4. 600
5. 800
6. 900
7. 1 KHz
8. 100 KHz
9. 500 KHz
10. 600 KHz
11.
700 KHz
12. 800 KHz
13. 900 KHz
14. 1 MHz
15. 1.1 MHz
16.
1.5 MHz
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WORKSHEET
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6. RESULT:
INFERENCE:
The Cascade amplifier was constructed and input resistance and gain were determined. The results
are found to be as given below
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
CONCLUSION:
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Cascode amplifier Circuit Diagram:
MODEL GRAPH:
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CASCODE AMPLIFIER
EXPERIMENT: 07 DATE:
1. OBJECTIVE:
To Design and Construct a Cascode Amplifier and to determine its:
a.
DC Characteristics
b. Maximum Signal Handling Capacity
c.
Gain of the amplifier
d. Bandwidth of the amplifier
e. Gain -Bandwidth Product
2. REQUIREMENTS:
S.No. Requirement Name Range Quantity
1
Components
Transistor [Active] BC 107 1
2 Resistor [Passive] 61kΩ, 10kΩ, 1kΩ,
4.7kΩ
1,1,1,2
3 Capacitor [Passive] 10µf, 100µf 2,1
4Equipment
signal Generator (0-3)MHz 1
5 CRO 30MHz 1
6 Regulated power supply (0-30)V 1
7
Accessories
Bread Board - 1
8
Connecting Wires Single strand as required
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DESIGN PROCEDURE:
Given specifications:
VCC= 20V, IC =1.2mA, AV= 30, , RL = 90KΏ ;
Transistor Parameters: hFE= 50 , hie = 1.2KΏ and hib= 24Ώ
(i) To calculate RC:
Rc = RL / 10 = 90kΏ / 10 = 9KΏ
(ii) To calculate RE:
Assume VCE1 = VCE2 = 3V, and VE = 5V;
The voltage drop across collector resistor is given by,
VRC = VCC - VCE1 - VCE2 – VE
= 20V – 3V – 3V- 5V
VRC = 9V
RE = VE / IE ; Where IE = Ic = 1.1mARE = 4.5K
(iii) To Calculate Bias Resistors R1, R2, R3 :
a.
R3 = 10 RE = 47KΩ
b. Voltage Across the base of Transistor 1 is given by,
VB1 = VBE + VE
VB1 = 5V + 0.7V = 5.7V
I3 = (VB1/ R3) = 5.7V / 47KΏ = 121 µA
c. Voltage Across the base of Transistor 2 is given by
VB2 = VBE2 + VE + VBE2
= 5V + 3V + 0.7V
= 8.7V
d. Voltage across resistor R2 is given by
VR2 = VB2 - VB1
VR2 = 8.7V – 5.7V = 3V
e.
The resistor R2 is given by R2 = (VR2 / I3 ) = (3V / 121µA)
R2 = 24.8KΩ
f. Resistor R1 = [VCC - VB2 / I3 ]
= [ 20V – 8.7V / 121 µA]
= 93.4 KΏ
Determination of Capacitor Values:
To Find C1 :
C1 = * 1 / 2πf 1 (Zi / 10) ]
Where Zi = ( R3 || R2 ) = 1.1KΩ and
f 1 = Lower cut-off frequency= 25HZ
= 57.9µF
To Find C2 :
C2 = * 1 / 2πf 1 (hie2 / 10) ] = 53 µF
Where hie2= 1.2 KΩ and f 1 = Lower cut-off frequency= 25HZ;
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To Find C3 :
C3 = * 1 / 2πf 1hib ]
Where hib= 24Ω and
f 1 = Lower cut-off frequency= 25HZ
= 256µF
To Find C4 :
C4 = * 1 / 2πf 1 ( (RC + RL) / 10) ]
Where RC = 9KΩ; RL = 90KΩ and
f 1 = Lower cut-off frequency= 25HZ
= 0.64 µF
THEORY:
The cascode configuration has one of two configurations of multistage amplifier. In each case
the collector of the leading transistor is connected to the emitter of the following transistor. The
arrangement of the two transistors is shown in the circuit diagram. The cascode amplifier consists of
CE stage connected in series with CB stage. The arrangement provides a relatively high input
impedance with low voltage gain for the first stage to ensure the input miller capacitance is at a
minimum, whereas the following CB stage provides an excellent high frequency response.
Features:
1. It provides high voltage gain and has high input impedance.
2.
It provides high stability and has high output impedance
PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CE amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier using AC analysis.
4. Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 0Hz to 1MHz in
incremental steps and note down the corresponding output voltage Vo for atleast 20 different
values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi)
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking frequency on x-
axis and gain in dB on y-axis.,
Bandwidth, BW = f 2-f 1
where f 1 - lower cut-off frequency
f 2 - upper cut-off frequency
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a.
DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
ix)
Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
x) Open circuit the capacitors since it blocks DC voltage
xi)
Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
xii) Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
1. VBE : (forward bias)
2. VRC = ____________
3. VCE = _______ (REVERSE BIAS)
4. Ic( Ic = (Vcc – VCE ) / Rc) =________
Q point analysis:
It is the procedure to choose the opearating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
b.
Maximum signal handling capacity :
It is the process to find the maximum input voltage that can be handled by the
amplifier, so that it amplifies the input signal without any distortion.
Procedure:
v. Apply input signal Vin = 20 mV of 1Khz frequency to the amplifier using the
signal generator between base emitter junction of the transistor.Find the
sinusoidal output using CRO across RL.
vi.
By increasing the amplitude of the input signal find maximum input voltageV MSH across VBE at which the sinusoidal signal gets distorted during the
processwhich can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
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5. TABULATION
Input voltage (Vin=V MSH/2) =____________ V
S. NO FREQUENCY
[Hz]
OUTPUT VOLTAGE
[ VO] in Volts
GAIN= 20 log Vo/Vin
dB
1. 0
2. 100
3. 500
4. 600
5. 800
6. 900
7. 1 KHz
8. 100 KHz
9. 500 KHz
10. 600 KHz
11. 700 KHz
12. 800 KHz
13. 900 KHz
14.
1 MHz
15. 1.1 MHz
16. 1.5 MHz
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6. RESULT:
INFERENCE:
The Cascode amplifier was constructed and input resistance and gain were determined. The resultsare found to be as given below
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
CONCLUSION:
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Differential amplifier Circuit Diagram:
Common Mode :
Differential Mode :
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DIFFERENTIAL AMPLIFIER
EXPERIMENT: 08 DATE:
1. OBJECTIVE:
To Design and Construct a Differential Amplifier using BJT and to determine its:
a.
Transfer Characteristics
b. Gain of the amplifier in common mode
c.
Gain of the amplifier in differential mode
d. CMRR (Common Mode Rejection Ratio)
2. REQUIREMENTS:
3. THEORY:
A differential amplifier is a type of electronic amplifier that amplifies the difference
between two voltages but does not amplify the particular voltages. The need for differential
amplifier arises in many physical measurements where response from D.C to many MHZ is
required. It is also used in input stage of integrated amplifier.
S.No. Requirement Name Range Quantity
1
Components
Transistor [Active] BC 107 2
2 Resistor [Passive]
3 Capacitor [Passive]
4
Equipment
signal Generator (0-3)MHz 2
5 CRO 30MHz 1
6 Regulated power supply (0-30)V 1
7
Accessories
Bread Board - 1
8Connecting Wires Single strand as required
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DESIGN PROCEDURE:
Given specifications:
VCC= 12V, IC=1.2mA, VCE = 5V
Assume Q1 = Q2
Where Q1 = Transistor 1 and Q2 = Transistor 2.
The Collector resistance Rc1 is given by using KVL at the transistor 1
Vcc = IcRc1 – VCE – Ie1Re1
Rc1 = (Vcc + VCE + Ie1Re1 ) / Ic,
Where VCE = 5V and Ic = 1.2mA, Ie1 = Ic/10 and assume Re1 = 470Ω
Now Rc1 = 1kΩ .
MODEL GRAPH:
Differential amplifier – Transfer Characteristics:
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The output signal in differential amplifier is proportional to the difference between the two
input signals.
Vo = Ad (V1 – V2 ).
Where V1,V2 are the input voltages and Ad is the differential gain.
If V1 = V2, then output voltage is zero. A non zero output voltage is obtained if V1 and V2
are not equal.
i) The difference mode input voltage is defined as Vd = (V1-V2)
ii) The common mode input voltage is defined as the Vcm= (V1+V2)/2
iii) The CMRR is defined as the ratio of the differential gain Ad to common mode gain
Ac and is generally expressed in dB.
CMRR= 20 log10 ( Ad / Ac)
4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the Differential amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to amplifier using
AC analysis.
4. Determine the Transfer characteristics of Differential amplifier by plotting the graph for
normalized differential input voltage [ (Vb1 – Vb2) / VT ] vs. Normalized collector current [ Ic / Io].
5. Calculate the voltage gain of differential amplifier for differential mode
as Ad = 20log (V0/Vi) , Where Vi = V1 – V2
6. Calculate the voltage gain of differential amplifier for Common mode
as AC = 20log (V0/Vi) , Where Vi = (V1+ V2 / 2 )
7.
Find the Common mode rejection ratio of differential amplifier using the formula given
below.
CMRR= 20 log10 ( Ad/Ac)
Where Ad- Differential mode gain in dB
Ac – Common Mode gain in dB
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a.
DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
i) Set Vin = 0 by reducing the amplitude of the input signal from signal
generator
ii) Open circuit the capacitors since it blocks DC voltage
iii) Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage
across Collector- Emitter Junction VCE and Voltage drop across base emitter
junction. VBE
iv) Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
1. VBE : (forward bias)
2. VRC = ____________
3. VCE = _______ (REVERSE BIAS)
4. Ic( Ic = (Vcc – VCE ) / Rc) =________
Q point analysis:
It is the procedure to choose the operating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
b.
Maximum signal handling capacity :
It is the process to find the maximum input voltage that can be handled by the
amplifier, so that it amplifies the input signal without any distortion.
Procedure:
vii.
Apply input signal Vin = 20 mV of 1Khz frequency to the amplifier using the
signal generator between base emitter junction of the transistor. Find the
sinusoidal output using CRO across RL.
viii.
By increasing the amplitude of the input signal find maximum input voltage
V MSH across VBE at which the sinusoidal signal gets distorted during the
process which can be seen in the CRO. The amplitude obtained at this point
is maximum voltage that can be applied to the transistor for efficient
operating of transistor.
V MSH = _________ volts
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5. TABULATION
a. Transfer Characteristics Calculation:
S.no Input Voltage
Vi = (Vb1 – Vb2) in Volts
Output Current
Ic2 in Ampere
1.
2.
3.
4.
5.
6.
b. CMRR Calculation:
To Find Differential Gain (Ad ) :
S. NO INPUT
VOLTAGE
in volts
OUTPUT VOLTAGE [ VO] in
Volts
Differntial gain in dB
Ad = 20log (V0/Vi)
Where Vi = Vi1 – Vi2
33. Vi1
34. Vi2
To Find Common Mode Gain (AC ) :
S. NO INPUT
VOLTAGE
in volts
OUTPUT VOLTAGE [ VO]
in Volts
Common mode gain in dB
AC = 20log (V0/Vi)
where Vi = (V1+ V2 / 2 )
1. Vi1
2. Vi2
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6. RESULT:
INFERENCE:
The Differential amplifier was constructed and input resistance and gain were determined. The
results are found to be as given below
d) Trans-Conductance of Differential amplifier ( in millisiemens) :
e)
Differential mode gain in dB :
f)
Common Mode Gain in dB :
g)
CMRR in dB :
CONCLUSION:
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SPICE SIMULATION USING PSPICE
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Common Emitter Amplifier circuit diagram
CE Amplifier without Feedback :
CE Amplifier with Feedback:
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COMMON EMITTER AMPLIFIER
EXPERIMENT: 01 DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using Pspice simulation tool and to
determine its:
a.
Gain of the amplifier
b.
Bandwidth of the amplifier
c. Gain -Bandwidth Product
2.
REQUIREMENTS:
THEORY:
A common emitter amplifer is type of BJT amplifier which increases the voltage level of the
applied input signal Vin at output of collector.
The CE amplifier typically has a relatively high input resistance (1 - 10 KΩ) and a fairly high
output resistance. Therefore it is generally used to drive medium to high resistance loads. It is
typically used in applications where a small voltage signal needs to be amplified to a large
voltage signal like radio receivers.
The input signal Vin is applied to base emitter junction of the transistor and amplifier output
Vo is taken across collector terminal. Transistor is maintained at the active region by using the
resistors R1,R2 and Rc. A very small change in base current produces a much larger change in
collector current. The output Vo of the common emitter amplifier is 180 degrees out of phase
with the applied the input signal Vin.
S.no Requirements Quantity
1 PC 1
2 Pspice Software -
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3. PROCEDURE:
1. Click on the start menu and select the pspice simulation software
2. Select the parts required for the circuit from the parts menu and place
them in the work space
3. Connect the parts using wires
4. Save the file and select the appropriate analysis
5. Simulate the circuit and observe the corresponding output waveforms
MODEL GRAPH:
4.RESULT:
INFERENCE:
The Common Emitter Amplifier was simulated and the following results were determined:
a)
Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
CONCLUSION:
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Common source Amplifier circuit diagram
CS Amplifier:
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COMMON SOURCE AMPLIFIER
EXPERIMENT: 02 DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using Pspice simulation tool and to
determine its:
a.
Gain of the amplifier
b.
Bandwidth of the amplifier
c. Gain -Bandwidth Product
2.
REQUIREMENTS:
THEORY:
There are three basic types of FET amplifier or FET transistor namely common source
amplifier, common gate amplifier and source follower amplifier.
The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a
voltage amplifier.
i) As a transconductance amplifier, the input voltage is seen as modulating the current going
to the load.
ii) As a voltage amplifier, input voltage modulates the amount of current flowing through theFET, changing the voltage across the output resistance according to Ohm's law.
However, the FET device's output resistance typically is not high enough for a reasonable
transconductance amplifier (ideally infinite), nor low enough for a decent voltage amplifier (ideally
zero). Another major drawback is the amplifier's limited high-frequency response. Therefore, in
practice the output often is routed through either a voltage follower (common-drain or CD stage), or
a current follower (common-gate or CG stage), to obtain more favorable output and frequency
characteristics
S.no Requirements Quantity
1 PC 1
2 Pspice Software -
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http://en.wikipedia.org/wiki/Ohm%27s_lawhttp://en.wikipedia.org/wiki/Electronic_amplifier#Input_and_output_variableshttp://en.wikipedia.org/wiki/Electronic_amplifier#Input_and_output_variableshttp://en.wikipedia.org/wiki/Electronic_amplifier#Input_and_output_variableshttp://en.wikipedia.org/wiki/Common-drainhttp://en.wikipedia.org/wiki/Common-gatehttp://en.wikipedia.org/wiki/Common-gatehttp://en.wikipedia.org/wiki/Common-drainhttp://en.wikipedia.org/wiki/Electronic_amplifier#Input_and_output_variableshttp://en.wikipedia.org/wiki/Electronic_amplifier#Input_and_output_variableshttp://en.wikipedia.org/wiki/Electronic_amplifier#Input_and_output_variableshttp://en.wikipedia.org/wiki/Ohm%27s_law
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3. PROCEDURE:
1. Click on the start menu and select the pspice simulation software
2. Select the parts required for the circuit from the parts menu and place
them in the work space
3. Connect the parts using wires
4. Save the file and select the appropriate analysis
5. Simulate the circuit and observe the corresponding output waveforms
MODEL GRAPH:
4.RESULT:
INFERENCE:
The Common Emitter Amplifier was simulated and the following results were determined:
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c)
Gain-Bandwidth product :
CONCLUSION:
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DIGITAL EXPERIMENTS
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DESIGN AND IMPLEMENTATION OF CODE CONVERTERS
EXPERIMENT: DATE:
1. OBJECTIVE:
To design and verify the truth table of the following code converters
a.
Binary to Gray converter
b. Gray to Binary converter &
c. BCD to Excess3 &
d. Excess3 to BCD.
2. REQUIREMENTS:
S. No. Components / Equipments Specifications Quantity
1.
2.
Digital IC trainer
NOT, AND, OR, Ex-OR Gate
---
IC7404,7408,7432,7486
1
1 in each
3. THEORY:
Binary to GRAY Converter:
By representing the ten decimal digits with a four bit Gray code, we have another form
of BCD code. The Gray code however can be extended to any number of bits and conversion
between binary code and Gray code is sometimes useful. The following rules apply for conversion:
1. The MSB in the Gray code is the same as the corresponding bit in the binary number.
2. Going from left to right, add each adjacent pair of binary bits to get the next Gray code bit.
Disregard carries.
GRAY to Binary Converter:
To convert from Gray code to binary code, A similar method is used, at there are some
differences. The following rules apply:
1. The MSB in the binary code is the same as the corresponding digit in the Gray code
2. Add each binary digit generated to the gray digit in the next adjacent position Disregard
carries.
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TRUTH TABLE FOR BINARY TO GRAY CODE CONVERTER:
| Binary input | Gray code output
B3 B2 B1 B0 G3 G2 G1 G0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
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K-Map for G3:
G3 = B3
K-Map for G2:
K-Map for G1:
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K-Map for G0:
Binary to GRAY Logic Diagram :
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TRUTH TABLE FOR GRAY CODE TO BINARY CONVERTOR:
| Gray Code | Binary Code
G3 G2 G1 G0 B3 B2 B1 B0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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K-Map for B3:
B3 = G3
K-Map for B2:
K-Map for B1:
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K-Map for B0:
GRAY to Binary LOGIC DIAGRAM
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TRUTH TABLE FOR BCD TO EXCESS-3 CONVERTOR:
| BCD input | Excess – 3 output |
B3 B2 B1 B0 G3 G2 G1 G0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
1
x
x
x
x
x
x
0
1
1
1
1
0
0
0
0
1
x
x
x
x
x
x
1
0
0
1
1
0
0
1
1
0
x
x
x
x
x
x
1
0
1
0
1
0
1
0
1
0
x
x
x
x
x
x
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K-Map for E3:
E3 = B3 + B2 (B0 + B1)
K-Map for E2:
K-Map for E1:
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K-Map for E0:
BCD TO EXCESS-3 Convertor Logic Diagram
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TRUTH TABLE FOR EXCESS-3 TO BCD CONVERTOR:
| Excess – 3 Input | BCD Output |
B3 B2 B1 B0 G3 G2 G1 G0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0