“It is all about time” -...

transcript

“It is all about time” metrics, implementation and applications of timing systems in integrated circuits

Roberto Nonis – Clocking and Interface Systems (CIS) group –

Infineon – Design Center Villach, Austria

18/06/2015

Roberto Nonis

Outline

Introduction

Ideal clock signals Vs real clock signals

Accuracy

Circuit applications

On-chip clock generation: Phase Locked Loops (PLLs)

Analog PLLs

Digital PLLs

… and the locations …

Application examples

ADAS: Advance Driver Assistance Systems

Time-of-Flight (ToF) 3D Imaging

Roberto Nonis

Long history of time measurement…

Latitude: observe stars' positions

Longitude: observe local time (sun position) and keep reference timing (Greenwich meridian from 1884 on) by a clock positioning is a matter of timing

the earth makes a revolution in 24h 40000Km/24h=1666km/h at the equator

1714 -British government - 20k pounds price - 30 nautical miles (55km) - 6 weeks voyage –precision of 3 sec/day (0,0034% or 34ppm) John Harrison’s chronometer

How does this compares with requirements for timing in today’s systems?

Is this kind of “accuracy” the only important parameter we have in our systems?

…what is the enabling technology behind our systems?

Roberto Nonis

Integrated electronics: small chips for big complexity

Roberto Nonis

Digital Signal Processing (DSP) chip: a complex system

Complex systems requires multiple clocks at different frequencies

The quality of the clock has different metrics for different parts of the system:

… ADC clocking

… digital core clocking

… high speed serial data interface

… and what about wireless transmission?

Roberto Nonis

What do we really mean with “clock”…

… a “clock signal”

Ideal clock signals Vs

real clock signals

Roberto Nonis

Accuracy (and stability): refers normally to “long term accuracy”: how precise the frequency is and stays close to the target frequency over (long) time

Noise: refers normally to “short term accuracy”

Accuracy Vs Noise

Stable and accurate

…but still noisy

Stable,

but not accurate

Noise on top of the accuracy error

Not accurate, not stable

Accuracy

Roberto Nonis

Accuracy requirements for different applications

1ppm timer has the precision of 86.4ms per day

1 second after 11,5 days

1ppb timer has the precision of 86.4us per day

second after 31,5 years

100000

• 10000ppm=1%

Crystal

oscillators

(0,5$~100$)

Atomic

oscillators

(>2000$)

Roberto Nonis

Noise in circuits

noiseless Noisy

Many types of noise:

Thermal noise - thermal motion of carriers in a conductor

Flicker noise - carrier density fluctuation (=R fluctuation)

Shot noise – discrete nature of electric charge

Voltage and current noise have zero mean.

The instantaneous value of voltage or current noise is not known, and not of interest, it is random.

Noise is described via its statistical characteristics.

Power Spectral Density (PSD) Sx(f): how much power the noise signal X carries in a unit bandwidth around frequency f.

― Units: [V2/Hz] or [A2/Hz]

Ideal noiseless voltage or current

signals do not exist.

Roberto Nonis

Noise on timing: Phase noise and Jitter

TIME DOMAIN

Noiseless clock signal

FREQUENCY DOMAIN

defined time instant

Jitter: the time instant is uncertain, only statistically defined

Skirts in voltage spectrum

due to Phase noise

Noisy clock signal

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Voltage Spectrum to Phase Noise PSD

))(Sin()( 0 ttAtV

Assumptions: No AM, small angle modulation

PSD is Single Side Band

of PSDCarrier ofPower

Carrier from @ BW Hz 1in Power

OFFSET

Roberto Nonis

Absolute jitter := Time difference between real and ideal edges

Absolute Jitter: a time-domain definition

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Phase Noise to Absolute Jitter

TIME DOMAIN

FREQUENCY DOMAIN

Skirts in voltage spectrum

due to Phase noise

ffLABS d)(2

Roberto Nonis

The jitter of one edge relative to the Nth previous edge is called Accumulated Jitter on N Cycles, jACC(N)

The Accumulated Jitter on 1 cycle is commonly called Period Jitter, jPER (or Edge-to-Edge Jitter)

In a free running oscillator, jACC(N) grows indefinitely with N:

More jitter types: Period jitter and Accumulated jitter

jPER jACC (N)

PERACC NN )(

Circuit applications

Roberto Nonis

Analog-to-Digital (ADC) conversion

In the digital domain the time information of the sampling instant is lost

The implicit assumption is that the samples are taken on the edges of an ideal clock

SlopePP

ABSANA

ABSJITTER

JITTERERROR

SIGNAL

1log20

:frequency with signal sinusoidal aFor

Example: SNR=65dB for an ADC converting a 10MHz bandwidth signal

requires a clock with 9ps of rms absolute jitter

What counts is “absolute jitter”

Roberto Nonis

Digital core: sequential digital circuit

a = CK to Q delay of the FF

b = delay of combinatorial logic

For correct operation: c > setup time of the FF

Constraint set on minimum duration of the clock period T (from edge to egde)

What counts is the “period jitter”

jPER,pk

Roberto Nonis

Wireline transmission

The sampler must be able to sample the receiver data in the center of the eye diagram

The more open is the eye, the less the probability of error (Bit Error Rate)

“Absolute jitter” closes the eye diagram

2.5Gb/s

2.5GHz

20bits @ 125Mb/s

For a BER=1e-12 at 2.5Gbps the jitter requirement on the total jitter pk-pk of 140ps, which implies the random absolute jitter of the clock to be below 4ps rms

Roberto Nonis

Wireless transmission (RX example)

Receiv

thesiz

Desired

Signal Unwanted

signals

Receiv

Desired

signal at if or

baseband

LORFIF fff f

noise Signal power away from the carrier down

converts (in receivers) and up-converts (in transmitters) unwanted signals

Unwanted signal becomes undistinguishable from desired signal

Noise distribution over frequency counts, jitter does not carry enough information

“Phase noise” is the right measurement of clock quality

On-chip clock generation:

Phase Locked Loops (PLLs)

Roberto Nonis

On-chip clock generation: Phase Locked Loops (PLLs)

From crystal oscillator

The crystal is off-chip

Example:

frequency = 25MHz

stability =300ppm

Phase noise @ 100kHz offset = -140dBc

Example:

Frequency=1GHz

stability: locked to the reference 300ppm

Phase noise: function of reference noise, PLL building blocks noise, PLL dynamics.

Crystal oscillators are not sufficient

Maximum frequency ~100MHz

Fixed frequency

usable as time references

Roberto Nonis

Type 2 Analog PLL, integer-N.

Lock condition:

DTchp 0

NTv= Tr

i.e. fout=Nfref

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Linear model for dynamics analysis and noise performance calculation

ndivonvconFilter

ncpnrefndivrnout

HSHSHSsS

vcoFilterV

Icpirefdiv

sourceH is the closed-loop transfer function from the noise

source to the PLL output

sourceS is the Power Spectral Density (PSD) of the noise

source

PFD + CP LPF VCO

cp,n Vfilter,n vco,n div_o,n

div_r,n

Kd F (s)LPF

[ ] [ ]

2 2 2 2 2

Roberto Nonis

Phase noise calculation and measurement

DIGITAL PLLs

Roberto Nonis

What is a digital PLL?

… a PLL where the control loop is implemented in the digital domain, i.e. numerically rather than with continuous-time analog signals

go digital

Roberto Nonis

Why digital PLLs ?

Analog RingO-PLL for D-PHI interface, fvco=800MHz

35ps rms integrated jitter (10kHz-fref/2)

130nm CMOS

1300um X 700um

Analog LC-PLL for PCI-e interface, fvco=5GHz

4ps rms integrated jitter (10kHz-fref/2)

65nm CMOS

500um X 300um

Roberto Nonis

Very short history of Digital PLLs

Digital PLL concept invented and implemented in first attempts already in 1970

First patent in 1990: Perrott et al, US Patent 6630868

Industrial spread of DPLL only recently, with nm-CMOS techs. First successful implementation: Staszewski‘s (2004)

High performance but very complex system, relying on TDC (Time-to-Digital converter), a sophisticated mixed-signal circuit.

TDC-less architectures are today’s cutting edge structures and research area.

Roberto Nonis

TDC-less multi-phase oscillator (DCRO) Digital PLL: ISSCC 2010

TDC operation is replaced by multi-phase ring oscillator which gives natively a

(low-resolution) period partitioning

Simple, small, low power, sufficient jitter performance for digital clocking

Roberto Nonis

PLL digital part

PLL analog part

Examples of digital PLLs in 65nm CMOS (for very different applications)

TDC DCO

TDC-LC-DCO Digital PLL 2.5Gb/s I/O

660um X 720um

10ps rms abs jitter

TDC-less DCRO Digital PLL for digital clocking

194um X 240um

25ps rms abs jitter

choose the right complexity for the right application!

Design innovation!

Roberto Nonis

What about a digital PLL, which has

low complexity, but very good

phase noise performance,

fractional operation, with also FSK

capability for low-data rate

wireless transmission?

Roberto Nonis

digPLL-Lite: TDC-less digital PLL, with Multi-Output Bang-

Bang Phase detector and Phase-Interpolator-based Fractional N divider. ISSCC 2013, JSSC 2013

Roberto Nonis

Examples of digital PLLs in 65nm and 40nm CMOS (for the very same application: 2.5Gb/s I/O)

PLL digital part

PLL analog part

TDC DCO

TDC-LC-DCO Digital for PLL 2.5Gb/s

I/O in 65nm CMOS

675um X 375um

10ps rms abs jitter

PLL analog part

PLL digital part

Digital PLL-Lite for 2.5Gb/s I/O in 40nm CMOS

370um X 150um

4ps rms abs jitter

choose the right complexity for the right application!

Design innovation!

…and the locations…

PhD 2003-2006

Allentown, Pennsylvania, US

2006-2007

Villach, Austria

2007- now

Roberto Nonis

Infineon facts, as of January 2015

~34,000 employees ww

32 R&D locations

20 manufacturing locations

R&D locations in Europe

R&D locations outside Europe

Roberto Nonis

Infineon Villach facts, as of January 2015

~3,000 employees

~300 in R&D

~80 PhD students

Roberto Nonis

What do we do at Infineon

Segments Applications

Roberto Nonis

Clock and Interfaces Systems (CIS) group, June 2015

US (10)

Team lead (1)

Analog/Mixed Signal design (6 people)

AMS Verification (2)

PhD student (1)

AMS Layout (3)

Digital design (4)

Lab validation (3)

PJM (1)

Our Goals

DEVELOP IPs ON

• Frequency generation • Oscillators • PLLs • DLLs • …

• HSIOs (data links)

IP development includes:

Concept Design Layout Lab validation Production test support Integration support Documentation

INNOVATION

• Keep state-of-the-art overview

• Invest in new solutions • Protect new ideas via

Patents

Our partners (11)

Our Customers

ATV MC

ATV SC

PMM DC-DC

… to be expanded

PMM AC-DC

PMM RFS

Application examples

Roberto Nonis

ADAS: Advance Driver Assistance Systems

https://www.youtube.com/watch?v=yBdqvpu48Gc

Roberto Nonis

Automotive microcontrollers

Audo Family

90nm CMOS

Aurix Family

65nm CMOS

AurixPlus Family

40nm CMOS

Aurix3G Family

Provided by CIS:

System and ADC clock PLL

Peripheral clock PLL

640Mbps HSCT serial interface and 200Mbps SRIF interface

2.5Gb/s serial interface

100MHz high precision back-up oscillator

Roberto Nonis

Time-of-Flight (ToF) 3D Imaging 100 000 pixels in the photonic

mixing device (PMD) 3D imaging sensor

Roberto Nonis

Just an example …

Provided by CIS:

Modulator PLL to drive the illuminator

System and ADC clock PLL

1.6Gpbs DPHY serial data interface

Roberto Nonis

“They always say time changes

things, but you actually have to

change them yourself ”

Andy Warhol

“It is all about time” -...

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