Post on 30-Dec-2015
description
transcript
1
Ch 6 Interrupt
제 41 강 : Interrupt(I)
2
CPU & Interrupt
3
Interrupt v.s. Exception
enable,disable CPU
PC←PC+4
Interruptrequest
bit
Instr. fetch
Instr. decode
Execution
Read data
Write BackPC ← address of
interrupt handler
Save register
CPU
Exception
illegal address
illegal opcode
divide by zero
4
interrupts v.s. exceptions
Interrupt ExceptionCause: external to CPU Cause: CPU internal
while executing instructions
eg I/O devices, timer eg Programming error Anomalous conditions
Current instruction completes
Current instruction may not complete
Asynchronous to clock Synchronous to clock
5
`
Many I/O devices – Interrupt Controller
PC←PC+4
Instr. fetch
Instr. decode
Execution
Read data
Write Back
zero
PC ← interrupt handler addr
Save register
set
CPU
interruptrequest
InterruptController
6
Interrupt Controller
7
1. IMR: – If not masked process IRQ
2. IRR:– Hold all requested IRQ’s until – they are eventually processed
3. Priority register:– Selects highest priority IRQ line
4. ISR– IRQ currently in service
5. Encode IRQ line # to vector #6. Send interrupt signal to CPU7. Waits for ack from CPU (PIC & device controller is blocked in the meantime)
• Many IRQ signals simultaneously
PIC(Programmable Interrupt Controller)
IMR (Interrupt Mask Register)
IRR (Interrupt Request Register)
ISR (In Service Register)
IRQ Lines
INTR
Priority Register
vectorACK
8
Ack
• PIC assigns vector number per each IRQ line
• Both PIC & device controller remain blocked until Ack from CPU (Bovet p. 122)
• Kernel must send Ack quickly to release PIC & device controller from blocked state as soon as possible (maximize I/O throughput)
• When CPU sends Ack, PIC & device go back to work. PIC can issue further interrupts.
9
PIC History(Master/Slave PIC)
1. XT CPU had only one INTR line2. Each PIC had only 8 IRQ lines
• XT had only one PIC
3. Many more I/O devices appears4. Connect 2nd PIC (slave PIC) to 1st PIC5. Master/Slave PIC
• Upward compatible
p. 112 Bovet
Master PIC
IRQ
INTR Pin
CPU
Slave PIC
INTR Pin
10
`
Many IRQ lines per PIC
PC←PC+4
Instr. fetch
Instr. decode
Execution
Read data
Write Back
zero
PC ← interrupt handler addr
Save registerset
CPU
INTR
VECTOR
INTR
PIC
Interrupt line
(IRQn)
Interrupt line
(IRQm)Interrupt line
(IRQ1)
. . .
Many IRQ lines per PICMask (Enable/Disable) each IRQ linePIC is blocked after INTRAck from CPU releases this PIC
vector number is assigned per IRQ line
11
`
Many devices per IRQ line
PC←PC+4
Instr. fetch
Instr. decode
Execution
Read data
Write Back
zero
PC ← interrupt handler addr
Save register
set
CPU
INTR
VECTOR
INTRPIC
Interrupt line
(IRQn)
Interrupt line
(IRQm)Interrupt line
(IRQ1)
. . .
Many devices per IRQ lineEach device has status registerCPU can access device status register
12
Interrupt Handlingin
Multiprocessor
13
Local & multi-APIC
• Local APIC– one per each CPU in SMP (CPU local)– Timer interrupt– All local APICs are connected to (external) APIC
• APIC (Advanced PIC) or multi-APIC– for multiprocessor – When a device raises IRQ, – multi-APIC selects a CPU, – delivers signal to corresponding local APIC, – which in turn interrupts CPU
bus
IRQ from I/O devices
CPU #1CPU #0
Timer
multiAPIC
LocalAPICTimer Local
APIC
14
SMP (Symmetric Multiprocessing)
Interrupt line
(IRQ0)
Interrupt line
(IRQ1)
. . .
CPU 0 CPU 1 CPU 2 CPU 3
Timer
APIC
Interrupt line
(IRQk)
Interrupt line
(IRQm)
Which CPU should receive this IRQm
signal?
signal from IRQm
15
IRQ distribution architecture
• Message distribution method depends on processor– The P6 family and Pentium processors
•pass messages through serial APIC bus•APIC bus arbitration
– The Pentium 4 and Intel Xeon processors•pass messages through system bus•system bus arbitration
(Ref) Intel Architecture Software Developer’s Manual
16
IRQ distribution algorithm
• IRQ distribution in two ways– static distribution– dynamic distribution
• Static distribution– use static table (Redirection Table)
• Dynamic distribution– use process priority – arbitration if same priority
17
Dynamic IRQ distribution algorithm
• Deliver IRQ to CPU running lowest priority process
• Tie? Arbitration algorithm – each processor maintains a counter (for
process)– Deliver IRQ to CPU with Maximum counter value
• counter 0 if IRQ is delivered (selected CPU)• counter++ if IRQ is not delivered (rest of the
CPU’s)
18
OSKernel
PIC
CPU #1Master CPU CPU #2
ppt
hwp
Shared Memory
All I/O Devices
PC=100 PC=3000
LocalMemory
- Only the master CPU can run OS kernel (1) slave asks master to run system call function (2) master queues all system call requests (3) master executes sys call one by one (4) I/O data are transferred from disk to shared memory
Asymmetric Multiprocessing
user codekernel code
19
Data Structure for
Interrupt Handling
20
Information about each IRQ line
Status
Handler
Lock
action
WhichPIC?
Each IRQ lineIRQm line
Interrupt service routines (ISR) device specific operations
IRQ_DISABLED - interrupt not allowed (masked or not)IRQ_WAITING - (interrupt allowed but) interrupt not been raisedIRQ_PENDING - (interrupt raised and Ack’ed). but not serviced by kernel yetIRQ_INPROGRESS – kernel is executing ISR
PIC
Interrupt line
(IRQn)
Interrupt line
(IRQm). . .
21
Status
Handler
Lock
action
Status
Handler
Lock
action
[0]
[1]
[2]
WhichPIC?
Interrupt service routines (ISR)
irqaction
Flags describing status of IRQ line
lock it, since many CPU’s access this data concurrently
irq_desc[]
dev name
dev handler
dev area
next
irqactionirqaction
dev name
dev handler
dev area
next
dev name
dev handler
dev area
next
Status
Handler
Lock
action
multiple devices can share a single IRQ device specific operationseach irqaction corresponds to a specific device
PIC
Interrupt line
(IRQn)
Interrupt line
(IRQm). . .