Post on 28-Jun-2018
transcript
Challenges of Fan-Out WLP and Solution
Alternatives
John AlmiranezAdvanced Packaging Business Development Asia
Introduction to Fan-Out WLP
Introduction
• World of mobile gadgetry
continues to rapidly evolve
• Products getting thinner and
lighter with higher performance
• Components inside must
deliver more performance,
memory and sustained power
in a smaller form factor
• Wafer-level packaging is an
essential vehicle to achieve
these goals
Introduction
• Wafer level packaging involves thin dies, thin and flexible substrates and tiny passive components, creating many challenges
• Assembly equipment must adapt to support these challenges, including:
– Unique substrate handling
– Efficient die attach
– Combining passives & multiple die
– Stacking die (2.5D/3D die attach)
• In this paper, we will address some of these challenges by providing a packaging technique focusing on die attach
Level of Interconnection
• 1st Level: Die on Substrate
• 2nd Level: Component on Circuit Board
• 3rd Level: Board to Board
• Unable to deliver the fit, form and function to meet next-generation devices
Second Level Packaging
e.g Card
First Level Packaging
e.g IC, CSP, BGA
Process assembly that involves die attachment,
wire bonding and encapsulation. Usually called
semiconductor process assembly.
Process assembly that involves solder paste
printing, component mounting and soldering.
Commonly called PCBA or SMT assembly.
IC Component Evolution
The component manufacturers are now fully aware that the evolution is driven by required size,
form, device capability and power
Solid state transistors integration into one package
Fan-Out WLP Process
Wafer Level Packaging Technique
• Wafer preparation & sawing – Place wafer into dicing tape, singulate the die
• Metal carrier preparation – Clean and remove contaminants from carrier
• Adhesive lamination – Pressure activate adhesive film
• Wafer reconstruction – Pick and place of dies from wafer into the metal carrier
• Molding – Encapsulate carrier in molding compound
• Carrier removal – Remove molded reconstructed dies from carrier
• Patterning and re-routing – RDL to provide metallization to create I/O pads
• Bumping – Bumps are made to form the external I/O terminals
• Singulation – Separate the molded package into its final form
Wafer Reconstruction
• Wafer reconstruction is the process of die mounting from wafer into a metal carrier
• All mounted dies are known good dies (KGD)
• Die attach or pick and place machine receives metal carrier with laminated film
• Feed with sawed wafer
• Pick die
• Inspect and place accurately into an arrayed form.
Fan-Out WLP Challenges &
Solutions
Die Mounting Challenges
• Placement accuracy – Typical target +/- 10 μm
x-y positional accuracy
• Die rotation – Can be critical for processes such
as patterning and redistribution layer, and if die
stacking will be required. Nominally, less than
0.15° is required.
• Die orientation – 0°, 90°, 180°, mirror orientation
• Die handling and packaging – Die sizes range
from 1mm square to 10mm square depending on
application
• Top alignment – Accuracy relies on the pattern
present at the top of dies
• Die stacking – Combining ASIC and memory
where the top die to bottom die is critical
Misplaced Die
Rotated Die
Speed vs. Accuracy
• Speed vs Accuracy have opposing
trends and normally cannot merge on a
single system
• High-Accuracy placement machines
cannot go faster, High-Speed machines
cannot be more accurate by simply
going slower
• Merging of Semiconductor and SMT
assembly technologies enables new
paradigm in placement equipment
• This is the foundation of a platform
technology / architecture, from the
leveling pads, to the
spindle/manipulator to handle the
device to be placed
Placement accuracy getting better
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ettin
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Techniques – Enabling High-Accuracy Placement
Importance of Mapping
• Each positioning system is unique, thus any absolute vector from encoder position to a particular location can differ from the predicted location
• Absolute moves over a large area are therefore impossible and the final destination will vary from system to system
• Solution: A machine map that correlates positioning system imperfections to encoder locations
Enhanced Mapping
• Models behavior of the positioning system and relates encoder coordinate locations to machine coordinates
– Machine locations are typically defined by the mapping plate(s)
– Encoder locations are defined by the (X,Y) linear encoders located on the X and Y beams (axis)
• Plate and grid sizes define the area and mapping resolution
• Enhanced mapping process certifies measurements modeling
Enhanced Mapping Illustration
• In an encoder coordinate system,
moving from P1 to P2 is purely an
X movement
• When the same movement is done
in a machine coordinate system,
both X and Y movements are
required
• Due to these spatial differences,
both an X and a Y map are
generated to translate between the
two coordinate systems
Techniques for Accuracy Stability
AOI feedback
• Accuracy is either self-verified or validated through capable automated optical inspection (AOI) systems
• The challenge: both processes may agree on repeatability but not means, thus a method to align to a common reference is key
• Appling AOI feedback is essential to refine each placement or spindle bias to a nominal placement coordinate, enabling multi-spindle systems to achieve higher throughputs without affecting accuracy
Mold operations or thermal effects on materials
• High material counts and HVM can only be realized by leveraging the abilities of process feedback from the AOI systems
• Feedback method supports post process steps requiring up stream corrections to accommodate / enhance final process performance conditions
• Software utilities enable seamless import of offset data into the placement system
Carrier Handling Challenges
• Conventional die attach machines are designed to handle leadframe, strip laminate
and singulated substrates; maximum width is usually 300mm or 12 inches. They
cannot handle larger substrates.
• The transport conveyor and board support are of fixed design, thus needing to change
the whole transport rail if there is a new package size
LaminateLeadframe
Increasing Throughput with Large Board Handling
• Wafer level packaging typically uses 300mm metal wafer format carrier
• Die size growing to meet the demand for more I/Os, thus 300mm carrier will frequently
have to be loaded/unloaded, hampering productivity
• This can be addressed by transforming the wafer format into a larger panel
Transitioning from 300 to 600mm
300mm metal carrier
600mm glass carrier
300mm metal carrier
600mm glass carrier
Precision Lifter and Board Support
Precision Lifter and custom top plate provides flexibility on board support for
different board size, different materials and different type
Large Panel
Support Tooling
Thin Laminate, Porous
Tooling
Spring Support Tooling
with Top Frame
Multiple Part Challenges
The wafer level packaging will not be limited to die only. Passives such as 01005
chips, interposers and spacers will eventually be part of the process. Also, a
carrier may consist of multiple part numbers for more complex circuits.
• Wafer
– Innova & Innova Plus - Handles various
sizes up to 300mm, capable of feeding
multiple wafers
• Tape & Reel
– Standard Tape feeders
– Dual Lane for 0201 and 01005
• Matrix Tray
– Stationary 2”x 2”, 4”x 4” & JEDEC
– Automated Stackable Feeders
– 2”x 2”, 4”x 4” & JEDEC
Die Stacking Process
Embedded
Die
Mold
Epoxy
Wafer Tape (Blue Tape)
Thickness – 100-150 μm
Through Mold Via (TMV)
30 – 50 μm depth
150 – 250 wide
Bump Topography
(100 – 150 μm)
The cross section shows layer of embedded die,epoxy and wafer tape. Due to presence of
bumps underneath, the bottom side is notflat. There is a potential surface
topography of 100-150 μm.
Cross Section for illustration purposes only
Die Stacking Process
Wafer Tape (Blue Tape)
Thickness – 100-150 μm
WLCSP Die
Size – 15 x 15mm
Thickness – 0.4 – 1mm
Bump Topography
(100 – 150 μm)
The WLCSP die will be placed on topof the die via TMV
Cross Section for illustration purposes only
Die Stacking Challenges and Solution
• Die stacking requires high accuracy between top & bottom components
• Misalignment may cause loss of interconnection between components
• High-accuracy placement and local alignment reduces this potential problem
• Different height of bottom component can cause warping or planarity issues
• Impact sensing eliminates this issue
TAP - High Accuracy by Top Alignment Process
• Traditional assembly aligns a device / die for
placement based on its bottom features
• Placement based on top features is limited
as the die active surface cannot be imaged
while held by a pick tip or
spindle/manipulator
• These barriers can be eliminated through
Top Alignment Process (TAP)
– Die outline and the top active pattern are
inspected, setting reference between
features
– Following top inspection, the die is picked
and bottom side is inspected, setting the
relationship between die outline and spindle
position
– Top to bottom correction is then applied with
the outline serving as reference, setting the
final offset based on top features and
eliminating inaccuracy caused by
component shift between inspect and pick
Alternative Solution
Wafer
Feeder
Pick & Place
Machine
Placement Capability
AMS high Cpk values during 6-hour run
Conclusions
Conclusions
• Demand for smaller but powerful gadgets or larger but more complex and
much more powerful will continue
• Product and component designs will continue to evolve to meet the market
demands
• The number of thinner, more powerful and ICs will increase
• The trend of combining system capabilities like ASIC and memory storage
will drive higher wafer level packaging complexity
• The supply chain will have to adapt to these requirements
• Materials, equipment and processes will also evolve and this emerging
packaging technology will drive the semiconductor/packaging industry and
wafer fabrication houses