Post on 17-May-2018
transcript
ECE 5745 Complex Digital ASIC DesignTopic 8: Testing and Verification
Christopher Batten
School of Electrical and Computer EngineeringCornell University
http://www.csl.cornell.edu/courses/ece5745
Coverge Design For Test: Scan and BIST
Part 1: ASIC Design Overview
P P
MM
Topic 1Hardware
DescriptionLanguages
Topic 2CMOS Devices
Topic 3CMOS Circuits
Topic 4Full-Custom
DesignMethodology
Topic 5Automated
DesignMethodologies
Topic 7Clocking, Power Distribution,
Packaging, and I/O
Topic 8Testing and Verification
Topic 6Closing
theGap
Topic 8Testing and Verification
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Coverge Design For Test: Scan and BIST
Testing and Verification
Specification
RTL
Gate Level
Layout
Chip
Formal VerificationTest Vector Equivalence (RTL Sim)
Formal Verification
Timing, Power, Noise Analysis
Test Vector Equivalence (GL Sim)
Layout vs Schematic
Timing, Power, Noise AnalysisDRC, ERC, Manufacturing Tests
Test Vector Equivalence (Circuit Sim)
Scan Testing
BIST DF
TC
ov
era
ge
Test Vector Equivalence (GL Sim)
Test Vector Equivalence (Circuit Sim)
Scan Testing
BIST
Test Vector Equivalence (RTL Sim)
Due to time constraints, we will just focus on coverage and DFT.
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• Coverge • Design For Test: Scan and BIST
Coverage Types
Coverage = measuring progress to complete design verification
I Bug rate. Indirect way to measure coverage. When bug rate sags, find different
ways to test
I Code coverage. Line, path, toggle, FSM
I Functional coverage. Which features have been tested?. cover property to identify
interesting signal values orsequences of signal values
. cover group samples datavalues and transactions
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• Coverge • Design For Test: Scan and BIST
Functional Coverage
I You can can use a directed test for features in designI You can use random testing to make writing tests easierI How do you know you are testing every feature?I Functional Coverage: measure of which design features are tested
Adapted from [Spear’12]
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• Coverge • Design For Test: Scan and BIST
Functional Coverage Strategies
I Gather information, not data. Do we really need to test all 4B
values of a 32-bit address?. Force constrained random testing
into “interesting” areas
I Only measure what you are goingto use in converage analysis. Gathering functional coverage
data can be expensive. Think critically about what to
monitor/record
I Measuring completeness. “Are we there yet?”. Use code coverage then bug rate to help determine
when verification is starting to convergeAdapted from [Spear’12]
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• Coverge • Design For Test: Scan and BIST
Functional Coverage Example
Adapted from [Spear’12]
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Coverge • Design For Test: Scan and BIST •
Testing and Verification
Specification
RTL
Gate Level
Layout
Chip
Formal VerificationTest Vector Equivalence (RTL Sim)
Formal Verification
Timing, Power, Noise Analysis
Test Vector Equivalence (GL Sim)
Layout vs Schematic
Timing, Power, Noise AnalysisDRC, ERC, Manufacturing Tests
Test Vector Equivalence (Circuit Sim)
Scan Testing
BIST DF
TC
ov
era
ge
Test Vector Equivalence (GL Sim)
Test Vector Equivalence (Circuit Sim)
Scan Testing
BIST
Test Vector Equivalence (RTL Sim)
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Coverge • Design For Test: Scan and BIST •
Scan Testing
Adapted from [Weste’11]
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Coverge • Design For Test: Scan and BIST •
Scan Testing
Adapted from [Kapur’17]
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Coverge • Design For Test: Scan and BIST •
Automatic Test Pattern Generation
RTL
Gate-Level
Scan InsertionATPG
Scan Test Vectors Gate-Level w/ Scan
ATPG Place and Route
Synthesis
Scan Test Sequence Layout
Chip Test
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Coverge • Design For Test: Scan and BIST •
BIST: Built-In Self Test
Controller
Comparator
Pattern Generator
BIST Module
DUT
Test
Con
tro
ller
Mux
Normal Interface
TestResults
TestMode
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Coverge • Design For Test: Scan and BIST •
Linear-Feedback Shift Registers
Cycle Q0 Q1 Q2, Y
0 1 1 11 0 1 12 0 0 13 1 0 04 0 1 05 1 0 16 1 1 0
7 1 1 1repeats forever
Adapted from [Weste’11]
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Coverge • Design For Test: Scan and BIST •
Boundry Scan Testing
Adapted from [Weste’11]
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Coverge • Design For Test: Scan and BIST •
Acknowledgments
I [Spear’12] C. Spear and G. Tumbush, “SystemVerilog for Verification,” 3rd ed,Springer, 2012.
I [Weste’11] N. Weste and D. Harris, “CMOS VLSI Design: A Circuits andSystems Perspective,” 4th ed, Addison Wesley, 2011.
I [Kapur’05] R. Kapur and K. Brisacher, “Next Generation Scan Synthesis,”COMPILER, 2005. https://www.synopsys.com/news/pubs/compiler/art2_scansynthe-may05.html
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