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Cc mch logic t hp c bn(Modular Combinational Logic Circuits)
Dr. Le DungSchool of Electronics and TelecommunicationsHanoi University of Science and Technology
Hanoi 5/2011
NI DUNGI. B gii m (Decoder)
1. Binary Decoder
2. BCD to Decimal Decoder
3. BCD to 7-segment Decoder
II. B lp m (Encoder)1. Binary Encoder
2. Binary Priority Encoder
3. Decimal to BCD Priority Encoder
III. B dn knh B phn knh (Multiplexer & Demultiplexer)1. MUX v DEMUX
2. 1 of 8 MUX v 1 to 16 MUX
3. Dual four-input MUX v Quad two-input MUX
4. ng dng ca MUX5. DEMUX c thc hin t Decoder
IV. B cng B tr - B so snh n v s hc v logic1. Binary Adder
2. BCD Adder
3. Subtractor
4. Comparator
5. Arithmetic Logic Unit (ALU)
Dr. Le Dung - School of Electronics and Telecommunications Page 2 / 60
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B GII M NH PHN - BINARY DECODER
n to 2n
DECODER
active-high
outputsMSB xn-1
LSB x0z0
z2n - 1
x1
.
.
.
.
.
.
z1
Ch c 1 u ra mc HIGH khit 1 m nh phn ti u vo
M hnh ton hcz0 = xn-1 . . . x1. x0 = Minterm0
z1 = xn-1 . . . x1. x0 = Minterm1
z2n-1 = xn-1 . . . x1. x0 = Minterm2n-1
Ch c 1 u ra mc LOW khit 1 m nh phn ti u vo
n to 2nDECODER
active-low
outputsMSB xn-1
LSB x0z0
z2n - 1
x1
.
.
.
.
.
.
z1
M hnh ton hcz0 = xn-1 . . . x1. x0 = Minterm0
z1 = xn-1 . . . x1. x0 = Minterm1
z2n-1 = xn-1 . . . x1. x0 = Minterm2n-1
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TNG HP B GII M NH PHN 2 TO 4
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2 to 4DECODERactive-low
outputs
LSBx0z0
MSBx1
z1
z2
z3
V sao li hay thc hin b gii mvi u ra tch cc mc thp ?
-Fanout-Power dissipation-NAND gates
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TNG HP B GII M NH PHN 3 TO 8
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TNG HP B GII M NH PHN 4 TO 16
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B GII M VIU VO ENABLE
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Enable = High such as normal 2 to 4 DecoderEnable = Low all outputs = High (inactive)
ngha ca u vo Enable ?
X2 = 0 Decoder0 acticve, Decoder1 inactiveX2 = 1 Decoder0 inacticve, Decoder1 active
IC 3 TO 8 Decoder 74LS138
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TNG HP B GII M NH PHN 5 TO 32T IC 74LS138
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IC 74LS139
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IC 74LS154
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NG DNG CA B GII M
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1. Tng hp mch logic t hp (Hnh 1)2. Gii m a ch nh trong cc b nh RAM, ROM (Hnh 2)3. Gii m lnh trong cc b vi x l4. Thc hin cc mch DEMUX (Phn sau)
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BCD to DECIMAL DECODER IC 74LS42
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MTNG DNG VI IC 74LS42
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(http://www.matni.com/Arabic/Elec-Info/LED SEQ/bfflash2.htm)
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BCD to 7-segment DECODER IC 74LS47
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BNG CHC NNG CA IC 74LS47
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IC 74LS48 dng cho 7-segment LED CC
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IC 74HC4511 dng cho 7-segment LCD
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B LP M - ENCODER
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V d : B lp m 8 to 3 Encoder
8 to 3 Encoder
B lp mnh phntng qut
BINARY PRIORITY ENCODER IC 74LS148
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MC U TIN CHO CCU VO 7 > 6 > 5 > 4 > 3 > 2 > 1 > 0
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DECIMAL to BCD PRIORITY ENCODER
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IC 74LS147
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LP M BN PHM VI IC 74LS147
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(Chy m phng c trn Circuit Maker 2000)
B DN KNH (MUX) B PHN KNH (DEMUX)
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B MUX 8 to 1 IC 74LS151A
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TO B MUX 16 to 1 T IC 74LS151A
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ng dng ca chn u vo Strobe
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B MUX 16 to 1 - IC 74LS150
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DUAL(2 bits) FOUR-INPUT MUX - IC 74LS153
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QUAD TWO-INPUT MUX - IC 74LS157
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MCH CHN 1 TRONG 2 S BCD HIN THDNG IC 74LS157
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(Chy m phng c trn Circuit Maker 2000)
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THC HIN 8-bit two-input MUX dng 74LS157
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THC HIN 4-bit four-input MUX dng 74LS157
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NG DNG CA B DN KNH
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1. TNG HP MCH LOGIC T HP (Hnh 1)2. NH TUYN D LIU3. CHUYNI D LIU T SONG SONG SANG NI TIP4. TO CHUI TN HIU TUN HON
TNG HP MCH LOGIC T HP BNG MUX
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VD: Thc hin hm F = (0, 2, 5, 6, 9, 10, 14, 15) dng 74LS151
Bi tp: 1. Thc hin f = ab + bc bng MUX 4 to 1.
2. Thc hin f = (3,6,7,8,10,12,13,14) bng MUX 4 to 1.
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THC HIN B PHN KNH DEMUX
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Dng DECODER thc hin DEMUX
VD: Decoder74LS138 thc hin DEMUX 1-line to 8-line
Datasheet: 1-OF-8 DECODER/ DEMULTIPLEXER54/74LS138
CHUYNI SONG SONG-NI TIPDNG MUX v DEMUX
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B CNG NH PHN 1 BIT-ADDER
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B cng Half-Adder B cng Full-Adder
B CNG NH PHN n BIT NI TIP
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Thanh ghi dch
Thanh ghi dch
Thanh ghi dch
Flip-Flip
Cc thanh ghi dch v Flip-Flop lm vic theo xung nhpTc cng chm
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B CNG NH PHN KIU NI TNGPseudo-parallel binary Adder or Cascaded Full-Adder
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VD: Thc hin b cng nh phn gi song song (kiu ni tng) 3 bits
Kiu ni tng ny cn c tn l Ripple-Carry Adder
IC 7482 TWO-BIT PSEUDO-PARALLEL ADDER
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7482
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IC 74LS83A FOUR-BIT ADDER
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c thit k tnh nh nhanh tng tc b cng
THIT K B CNG 8-BIT DNG 74LS83A
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BCD ADDER
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BI TP: THIT K B CNG BCD DNG 74LS83A
CASCADING BCD ADDER
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HIGH-SPEED ADDER DESIGN
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5. Fully Parallel Adder (Look-up Table Adder)
1. Carry Look-ahead Adder
2. Carry-Save Adder (c thm)
4. Kogge-Stone Adder (c thm)
3. Carry-Bypass Adder (c thm)
CARRY LOOK-AHEAD ADDER DESIGN
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Xut pht t cng thc COUT = Ci = Ai.Bi + (Ai Bi).Ci-1
t Gi = Ai.Bi gi l Generate termPi= (Ai Bi) gi l Propagate term
Ci = Gi + Pi.Ci-1
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IC 74182 LOOK-AHEAD CARRY GENERATOR
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74182
B TR - SUBTRACTOR
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A B = A + (-B) = A + Bb2 = A + Inv(B) + 1
Dng IC 74LS83 v 74LS86 (hoc vi MUX)
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MCH PHT HIN TRN OVERFLOW DETECTION
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B SO SNH COMPARATOR
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Thc hin b so snh 1-bit
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4-BIT MAGNITUDE COMPARATOR 74LS85
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GHP NI CC IC 74LS85
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ARITHMETIC LOGIC UNIT
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VD: Bng chc nng ca ALU
IC 74LS382 ALU CHIP
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GHP NI IC 74LS382
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VD: To b cng 8-bit t 2 IC 74LS382
BI TP THIT K ALU (1)
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Thit k b ALU 1-bit t ghp nichng li thnh ALU n-bit
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BI TP THIT K ALU (2)
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- Chia ALU thnh 2 khi LUv AU thit k.- Dng MUX kt hp lithnh ALU
MUX 2 to 1
BI TP THIT K ALU (3)
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Thit k khi LU (Logic Unit) vi 4 hm c bn
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BI TP THIT K ALU (4)
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Thit k khi AU (Arithmetic Unit) vi 4 php ton
KT QU: THIT K 1-BIT ALU
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