Post on 11-Apr-2018
transcript
CMOS Harmonic Rejection Receiver
Architecture Design of
Multiband Radar Systems
Electronics Systems Research Division
National Chung-Shan Institute of Science and Technology (NCSIST)
Taiwan
October 04, 2016 at Ankara, Turkey
Hua-Chin Lee (speaker) and Ya-Lan Tsao
2
Outline
Introduction
Harmonic Rejection Architecture
Direct-Conversion Harmonic-Rejection Receiver
a. gm-Boosted Noise-Cancelling LNA
b. Mixer Array
c. Harmonic-Rejection Filter
d. PLL-Based Frequency Synthesizer
e. Measurement results
Conclusions
3
Multiband Radars
• System property
• Operating in a variety of
frequency bands.
• Being a joint system.
• Purpose
• Detect and track hostile targets.
Antenna
Transmitter /
Receiver circuit
Signal processing
Decision making
Antenna
Transmitter /
Receiver circuit
Antenna
Transmitter /
Receiver circuit
4
About this research
Antenna
Transmitter /
Receiver circuit
Signal processing
Decision making
Hardware
Software
Software
+ Human
National Chung-Shan Institute
of Science and Technology
National Taiwan Univertity
EECS
MediaTek Inc.
Taiwan Semiconductor
Manufacturing Company
5
System Block Diagram
T/R
Switch
Tunable
Filter
Wideband
PA
Wideband
TXLPF
LPFWideband RX
(LNA, Mixer)
Wideband
Frequency
Synthesizer
ADC
DAC
Digital
Baseband /
MAC
Spectrum
SensingADC
Research area
6
RFBB
LO
t
fLO 3LO 5LO 7LO
fLO 3LO 5LO 7LO
Harmonic Rejection
ISSCC 2001[4]
f
Circuitry linearity
Signal quality
7
RFBB
LO
t
fLO 3LO 5LO 7LO
fLO 3LO 5LO 7LO
Harmonic Rejection
t
t
t
t
LO1
LO2
LO3
LO
1 2 3( ) ( ) 2 ( ) ( )LO LO LO LOf t f t f t f t ISSCC 2001[4]
f
Harmonic rejection eliminates multiple high-Q band-select filters.
8
Proposed Direct-Conversion Harmonic-
Rejection (DCHR) Receiver
29:41:29
29:41:29
9
Proposed Harmonic Rejection
Two-stage weighting in filters (29:41:29)
45
90
135
45
90
135
90
135
180
90
135
180
x29
x41
x29
x29
x29
x41
x29
x41
x29
x29
x29
x41
x29
x41
x29
x29
x29
x41
0
45
90
0
45
90
58
58
82
58
58
82
58
58
82
x29
x41
x29
4756
4756
6726
8
4756 : 6726 : 4756
(error to 2) 4.42 10
10
Proposed DCHR Receiver Architecture
Pros
a. One single-ended input LNA
• Power reduction
• Low complexity
b. Switching mixers used in the mixer array
• Power reduction
• Low complexity
c. Two-stage weighting in HR filters
• In the baseband
Cons
a. R nets
11
RF
BB11BB12 BB21
BB22
BB31BB32 BB41
BB42
IF81
0∘
45∘
90∘
135∘
180∘
225∘
270∘
315∘
8-Phase Frequency Synthesizer
This Chip
Noise Cancelling
LNA
2-Stage Polyphase HR Filters8-Phase Switching Mixer
VDD
vout
vRF
vLOVDD
vout
vRF
vLOVDD
vout
vRF
vLOVDD
vout
vRF
vLOVDD
vout
vRF
vLOVDD
vout
vRF
vLOVDD
vout
vRF
vLOVDD
vout
vRF
vLO
VDD
vout
vRF
vLOVDD
vout
vRF
vLOVDD
vout
vRF
vLOVDD
vout
vRF
vLOVDD
vout
vRF
vLOVDD
vout
vRF
vLOVDD
vout
vRF
vLOVDD
vout
vRF
vLO
IF71IF61
IF51IF41
IF31IF21
IF11
IF82IF72
IF62IF52
IF42IF32
IF22IF12
_
+_+
_
++_
_
+_+
_
+_+
CLKrefPLL
IF11IF21IF31IF52IF62IF72
IF12IF22IF32IF51IF61IF71
41R 29R
20R
20R
IF21IF31IF41IF62IF72IF82
IF22IF32IF42IF61IF71IF81
41R 29R
20R
20R
IF31IF41IF51IF72IF82IF12
IF32IF42IF52IF71IF81IF11
41R 29R
20R
20R
IF41IF51IF61IF82IF12IF22
IF42IF52IF62IF81IF11IF21
41R 29R
20R
20R
BB11BB21BB31
BB12BB22BB32
I+I-
20R
20R
BB11BB31BB41
BB12BB32BB42
Q+Q-
20R
20R
C
C
C1
C1
41R 29R
41R 29R C2
C2
out+
out-in
Off-chip BIAS
network
Freqsel8
Unity-gain
Buffer
Unity-gain
Buffer
Proposed Direct-Conversion Harmonic-
Rejection (DCHR) Receiver
29:41:29 29:41:29
12
gm-Boosted Noise-Cancelling LNA
4u/0.1u
500Ω 350Ω
6.6kΩ
6.6kΩ
60u/0.1u
125u/0.1u
6u/0.1u
6.6kΩ
300Ω
25u/0.1u
• Wideband input matching
• Single differential
• Avoiding a external balun
13
Mixer Array
Create 8-phase IF signals
• Providing 45º
phase shift
14
Harmonic-Rejection Filter
Overall response IF41
IF51
IF61
IF82
IF12
IF22
IF42
IF52
IF62
IF81
IF11
IF21
BB41BB42
41R
41R
29R
41R
41R
29R
41R
41R
29R
41R
41R
29R
20R
20R
C
C
BB11
BB21
BB31
BB12
BB22
BB32
I+I-
41R
41R
29R
41R
41R
29R
20R
20R
C
C
BB31
BB41
BB11
BB32
BB42
BB12
Q+Q-
41R
41R
29R
41R
41R
29R
20R
20R
C
C
IF31
IF41
IF51
IF72
IF82
IF12
IF32
IF42
IF52
IF71
IF81
IF11
BB31BB32
41R
41R
29R
41R
41R
29R
41R
41R
29R
41R
41R
29R
20R
20R
C
C
IF21
IF31
IF41
IF62
IF72
IF82
IF22
IF32
IF42
IF61
IF71
IF81
BB21BB22
41R
41R
29R
41R
41R
29R
41R
41R
29R
41R
41R
29R
20R
20R
C
C
IF11
IF21
IF31
IF52
IF62
IF72
IF12
IF22
IF32
IF51
IF61
IF71
BB11BB12
41R
41R
29R
41R
41R
29R
41R
41R
29R
41R
41R
29R
20R
20R
C
C
3111 21
2 2
11
( )( ) ( )1( )
20 41 29 41
( ) 2 1
( ) 1 41
20
BBBB BBI
I
IF
v sv s v sv s sC
R R R R
v s
v s RsC
R
2 3 4
8 8 8 82 2 2
2 2 1 2 1
41 29 41 2941 29 41
T T T Ts s s s
e e e eR R R RR R R
2 3
8 8 82 2 2
2 2 2 1 2
41 29 41 291 41 29
20
T T Ts s s
e e eR R R RR R
sCR
15
Harmonic-Rejection Filter
HR filter frequency response for square-wave
LO input
16
107
108
109
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
Magnitude (
dB
)
Bode Diagram
Frequency (Hz)
Harmonic-Rejection Filter
Phase error in 1 degree
108.4
108.5
-40
-35
-30
-25
-20
-15
-10
Magnitude (dB
)
Bode Diagram
Frequency (Hz)
17
PLL-Based Frequency Synthesizer
Architecture
18
Measurement Setup
19
Measurement Results
Performance comparisons ISSCC08[7] ISSCC06[5] ISSCC09[8] ISSCC07[6] This work
Technology 65-nm
CMOS
90-nm
CMOS
65-nm
CMOS
0.13-μm
CMOS
90-nm
digital CMOS
Supply
voltage 1.2 V 2.5 V* / 1 V 1.2 V 1.2 V 1 V
Freq.(GHz) 0.2~0.9 0.8~5 0.4~0.9 0.048~0.86 0.1~1.2
Area (mm2) 1.2x0.82 2.9x2.4 1x1 3x3.8 1x1
Rx block Mixer, LO
generator
LNA*,
Mixer*, Divider
LNA, Mixer,
Divider
LNA, Mixer,
BB filter, VGA,
ADC, PLL
LNA, Mixer,
HR Filter, PLL
Gain(dB) 5 36 34 83 34
NF (dB) 12 5 4 4~7 4
IIP3 (dBm) 11 -15 3 -14 -10
HR3 (dB) 41 38 60 42 50
HR5 (dB) 44 40 64 X 53
Total power
consumption 19 mW 51 mW 60 mW 468 mW 28.6 mW
20
Conclusions
A wideband DCHR receiver for multiband radar
systems is proposed and demonstrated.
A wideband gm-boosted LNA with noise-cancelling is
proposed.
The 2-stage weighting in HR filter provides more
precise 1:√2:1 ratio than pri arts.
The highly integrated DCHR receiver is demonstrated.
21
Thank you for your attention!