Computer Architecture & Operating Systems

Workshop 2 - Lecture 1

Plagiarism & Citing Sources /

Program Execution, Buses & I/O Devices

Avoiding Plagiarism

Referencing Sources correctly

Academic Report Writing

i) Definition of PLAGIARISM

Plagiarism is the act of copying, including or directly quoting from, the work of another without adequate acknowledgement. The submission of plagiarised materials for assessment purposes or for publication or for public presentation is fraudulent and all suspected cases will be investigated and dealt with appropriately by the University following the procedures outlined here and with reference to the Disciplinary Code.

All work submitted by students for assessment purposes is accepted on the understanding that it is their own work and written in their own words except where explicitly referenced using the accepted norms and formats of the appropriate academic discipline.

Source: National University of Ireland, Galway. (2007). Code of practice for dealing with plagiarism. Retrieved July 4, 2007, from NUIG, University Code of Conduct, Appendix VI web site: http://www.nuigalway.ie/student_life/university_code_conduct/code.html#1.10

ii) Why acknowledge sources?

Acknowledge your dependence on another person’s ideas or words

Receive credit for your research Establish the credibility & authority of your knowledge

and ideas To place your own ideas in context To permit your reader to pursue your topic further To permit your reader to access your sources

Source: Princeton University. (2007). Acknowledging your sources. Retrieved July 4, 2007, from Academic Integrity at Princeton web site: www.princeton.edu/pr/pub/integrity/pages/acknowledge.html

iii) How to cite sources?

There are 2 parts to citing your sources

In-text citations Reference List “direct quotation” (Smith, 2001, p. 45) always on its own page idea according to Smith (2001),… at the end of the thesis

iv) Always cite your sources!

SOURCES

CITATIONS

2. Identify type of source (e.g. book, web page)

1. Select appropriate sources

3. Determine fields required for that source

A good citation allows the reader to locate

the source(s)

Connecting Components

All the units must be connected, whereby different types of connection are required for different types of unit: Memory Input/Output (I/O) CPU

Buses

What is a bus? Communication pathway connecting two or

more devices Usually broadcast (a number of channels in

one bus) Power lines may not be shown

Types of bus Data Bus

Carries data/instructionsWidth is a key determinant of performance

Buses

Types of bus Address Bus

Identifies the source or destination of data Bus width determines maximum system memory capacity

Control Bus Control and timing information, e.g. memory read/write signal,

Interrupt request or clock signals

What does a Bus look like?

Single Bus Problem

Lots of devices on one bus leads to propagation delay: Long data paths mean that co-ordination of bus use

can adversely affect performance If aggregate data transfer approaches bus capacity

Most systems use multiple buses to overcome these problems

Traditional (ISA) Bus (with cache)

High Performance Bus

Bus Types

Dedicated with separate data and address lines Multiplexed with shared lines

A control line distinguishes between address valid and data valid Advantage: Fewer lines Disadvantages: More complex control & reduced

performance Bus Arbitration

More than one module (e.g. CPU and DMA controller) controlling the bus

Only one module may control bus at one time Arbitration may be centralised or distributed

Bus Arbitration

Centralised Arbitration Single hardware device (the bus controller or

arbiter) controlling bus access May be part of CPU or separate

Distributed Arbitration Each module may claim the bus Control logic on all modules

PCI Bus

32 or 64 bit Peripheral Component Interconnection Usually runs in 32 bit mode at 33Mhz = 133MBps 64 bit mode at 66MHz = 528MBps

Intel released to public domain 49 mandatory lines & 51 optional lines PCI Commands

Transaction between initiator (master) and target Master claims bus Determine type of transaction (read or write) Address phase One or more data phases

PCI Bus

PCI Bus

Input/Output (I/O)

I/O Devices External Memory - Hard & Floppy Disks, CD-ROM Human Readable - Screen, printer, keyboard Machine Readable- Monitoring and control Communications - Modem, Network Interface Card

Input/Output Problems Wide variety of peripherals, which deliver different

amounts of data at different speeds and in different formats (word or block), e.g. Keyboard or mouse < 1 Kilobits per second (kbps) Fast Ethernet 100 Megabits per second (Mbps)

All slower than CPU and RAM

I/O Devices

Typical I/O Device Data Rates

I/O Modules

Abstract and simplify the interaction between the CPU the peripheral

Provide internal interfaces (CPU/Mem I/O module) and external interfaces (I/O module actual device)

I/O Module Functions Control and timing as well as error detection CPU communication Data buffering

- CPU/Main Memory - high data rate - I/O devices - vary from very low to high - I/O module uses buffers to match data rates between CPU and I/O device

Generic I/O Scenario:Peripheral to CPU Transfer

CPU checks I/O module device status I/O module returns status If ready, CPU requests data transfer I/O module gets data from device I/O module transfers data to CPU

Remark: internal (CPU) & external (device) communication is required

I/O Module Diagram

Input/Output Techniques

Programmed Interrupt driven Direct Memory Access (DMA)

Programmed I/O CPU has direct control over I/O

Sensing status Read/write commands Transferring data

CPU waits for I/O module to complete operation Programmed I/O wastes CPU time

Programmed I/O: Detail

CPU requests I/O operation I/O module performs operation I/O module sets status bits CPU checks status bits periodically I/O module does not inform CPU

directly I/O module does not interrupt CPU

Interrupt Driven I/O

Overcomes CPU waiting

No repeated CPU checking of device I/O command issued CPU undertakes other work CPU checks for interrupt at end of each instruction cycle

I/O module interrupts when ready CPU saves context etc. Processes interrupt Reloads context and continues

Interrupt Processing

Interrupt Driven I/O: Basic Operation

CPU issues read command I/O module gets data from

peripheral whilst CPU does other work

I/O module interrupts CPU CPU requests data I/O module transfers data

Identifying the Interrupting Module

Different line for each module Limits number of devices

Software poll CPU asks each module in turn – slow!

Daisy chain or hardware poll Interrupt Acknowledge sent down a chain Module responsible places vector on bus CPU uses vector to identify handler routine

Bus master Module must claim the bus before it can raise

interrupt e.g. PCI & SCSI

Multiple Interrupts

An interrupt handler can be interrupted because of a new interrupt request with higher priority

Different line for each module Each interrupt line has a priority

Software poll Poll higher priority devices first

Daisy chain or hardware poll Higher priority devices first in daisy chain

Bus master If bus mastering only current master can interrupt

Direct Memory Access (DMA)

Interrupt driven and programmed I/O require active CPU intervention Transfer data is limited, the CPU is tied up

DMA is the answer: a DMA controller is another module (hardware) on the bus Takes over from CPU for I/O

DMA Operation CPU tells DMA controller details about operation CPU carries on with other work DMA controller deals with transfer DMA controller sends interrupt when finished

DMA Transfer Cycle Stealing

DMA controller takes over bus for a cycle Transfer of one word of data CPU suspended just

before it accesses bus (reads/writesfrom/to memory)

Slows down CPU but not as much as CPU doing transfer

DMA Configurations

Single bus, detached DMA controller Each transfer uses bus twice, CPU is suspended twice

Single bus, integrated DMA controller Each transfer uses bus once, CPU is suspended once

DMA Configurations

Separate I/O bus Bus supports all DMA enabled devices Each transfer uses bus once, CPU is suspended once

Techniques for Data Input

I/O Channels

I/O devices getting more sophisticated Have their own processor/memory (e.g.

3D graphics cards) CPU instructs I/O controller to do transfer I/O controller does entire transfer Improves speed: takes load off CPU

In This Lecture, You Have Learned …

Computer buses Data bus versus address bus versus control bus Traditional buses versus high-performance buses Bus types and bus arbitration Synchronous versus asynchronous timing The PCI and the AGP bus

I/O devices Typical I/O scenarios and expected data rates I/O modules and I/O module functions I/O scenarios I/O techniques: programmed I/O, interrupt driven I/O, DMA Handling multiple I/O tasks using interrupt driven I/O