COPING WITH INTERCONNECT

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Digital Integrated Circuits © Prentice Hall 1995Interconnect

Impact of Interconnect Parasitics

• Reduce Reliability

• Affect Performance

Classes of Parasitics

• Capacitive

• Resistive

• Inductive

Nature of Interconnect

Local Interconnect

Global Interconnect

SLocal = STechnology

SGlobal = SDie

INTERCONNECT

Dealing with Capacitance

Capacitance: The Parallel Plate Model

Substrate

Typical Wiring Capacitance Values

Fringing Capacitance

W - H/2H

Fringing Capacitance: Values

How to counter Clock Skew?

(from [Bakoglu89])

Interwire Capacitance

Substrate

Insulator

Level1

Level2

Creates Cross-talk

Interwire Capacitance

Impact of Interwire Capacitance

(from [Bakoglu89])

Capacitance Crosstalk

5x5 m Overlap: 0.35 V Interference

How to Battle Capacitive Crosstalk

Substrate (GND)

ShieldinglayerVDD

Shieldingwire

• Avoid parallel wires

• Shielding

Driving Large Capacitances

Vin Vout

tpHL = CL Vswing/2

Transistor

Sizing

Using Cascaded Buffers

1 u u2 uN-1

In Out

uopt = e

tp in function of u and x

1.0 3.0 5.0 7.0u

x=1000

x=10,000

Impact of Cascading Buffers

Output Driver Design

How to Design Large Transistors

G(ate)

S(ource)

D(rain)

Multiple

Contacts

(a) small transistors in parallel(b) circular transistors

Bonding Pad Design

Bonding Pad

InVDD GND

Reducing the swing

tpHL = CL Vswing/2

• Reducing the swing potentially yields linear reduction in delay• Also results in reduction in power dissipation• Requires use of “sense amplifier” to restore signal level

INTERCONNECT

Dealing with Resistance

Wire Resistance

R = H W

Sheet ResistanceRo

Interconnect Resistance

Dealing with Resistance

• Selective Technology Scaling

• Use Better Interconnect Materials

• More Interconnect Layersreduce average wire-length

e.g. silicides, bypasses

Polycide Gate Mosfet

PolySilicon

Silicide

Silicides: WSi2, TiSi2, PtSi2 and TaSi

Conductivity: 8-10 times better than Poly

Modern Interconnect

RI Introduced Noise

VDD - V’

Power and Ground Distribution

(a) Finger-shaped network (b) Network with multiple supply pins

Electromigration (1)

Limits dc-current to 1 mA/m

Electromigration (2)

RC-Delay

RC-Models

Reducing RC-delay

Repeater

The Ellmore Delay

Penfield-Rubinstein-Horowitz

INTERCONNECT

Dealing with Inductance

Inductive Effects in Integrated Circuits

CoaxialCable

TriplateStrip Line

MicroStrip Wire aboveGround Plane

L di/dt

VoutVin

L di/dt: Simulation

2 4 6 8 10t (nsec)

tfall = 0.5 nsec

tfall = 4 nsec

Signals Waveforms for Output Driver connected To Bonding Pads(a) vout; (b) iL and (c) vL.

The Results of an Actual Simulation are Shown on the Right Side.

Choosing the Right Pin

MountingCavity

Lead Frame

Bonding Wire

Make Rise- and Fall Times as slow as possible

Decoupling Capacitors

CHIPSUPPLY

Bonding

WireBoard

Wiring

Decoupling

Capacitor

Packaging

Requirements

• Electrical: Low parasitics

• Mechanical: Reliable and Robust

• Thermal: Efficient Heat Removal

• Economical: Cheap

Bonding Techniques

Lead Frame

Substrate

Wire Bonding

Tape-Automated Bonding (TAB)

(a) Polymer Tape with imprinted

(b) Die attachment using solder bumps.

wiring pattern.

Substrate

Solder BumpFilm + Pattern

Sprockethole

Polymer film

Leadframe

Testpads

Flip-Chip Bonding

Solder bumps

Substrate

Interconnect

layers

Package-to-Board Interconnect

(a) Through-Hole Mounting (b) Surface Mount

Package Types

Package Parameters

Multi-Chip Modules

COPING WITH INTERCONNECT

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