Post on 22-Jan-2021
transcript
CS250, UC Berkeley Spring 2017Lecture 01, Introduction 1
CS250VLSI Systems Design
Fall 2020
John Wawrzynek with
Arya Reais-Parsi (virtual GSI)
CS250, UC Berkeley FA20Lecture 01, Introduction 1
First Thing …‣ This class has always been and will continue to be highly interactive :
not recorded. ‣ It is like a “studio-based art class”. Students show and discuss their art
and get feedback and ideas from other students and the instructor. Minimal emphasis on lectures.
‣ We found this to be a very effective for students to advance their design skills. But it’s success depends on commitment by everyone. Everyone is expected to stay engaged and offer comments and questions.
‣ Challenging now in the days of the pandemic. ‣ It can work over zoom, but it takes more effort by all of to stay
engaged. In my experience with teleconferencing and (many) zoom meetings over these months, teleconferencing works best with video enabled.
‣ If your situation prohibits you from comfortably keeping your video on, please let me know. Otherwise I’ll expect that you keep it on.
‣ Stay muted, but un-mute and interrupt at any time! 2
CS250, UC Berkeley FA20Lecture 01, Introduction 1
John Wawrzynek (pronounced “Warsnik”)Professor in EECS ‣ Berkeley faculty since 1989
Teaching: ‣ CS61c, EECS151/251A, other hardware and architecture
courses Research: ‣ Computer Architecture, Reconfigurable Computing, Digital
Design Methodologies, ‣ Advanced Wireless Systems
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Administrative: ‣ CS Vice-chair for Graduate
Matters ‣ Chair Berkeley Campus Conflict
of Interest Committee Degrees: ‣ MSEE UIUC, PhD Caltech
Start-ups: Former-life: professional musician (bass), Buffalo NY
CS250, UC Berkeley FA20Lecture 01, Introduction 1
The context for CS250‣ Number 1 reason for students to enroll in CS250: ‣ “Gain more experience in digital design - specifically
targeting custom ICs”
‣ Components of Digital Design: 1. Logic and Transistor Circuits and low-level blocks: ‣ how to achieve desired function of low-level chip building
blocks ‣ state transitions and clocking ‣ performance/cost/power tradeoffs ‣ physical realization concerns (floorplanning, clock
distribution, pwr distribution) ‣ Provides “Bottom-up” knowledge
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CS250, UC Berkeley FA20Lecture 01, Introduction 1
The context for CS250‣ Components of Digital Design:
2. Chip Architectures and high-level blocks: ‣ How building blocks are assembled to achieve high-level
functionality ‣ Processor Cores (CPUs), chip-multiprocessors (CMP), Field
Programmable Gate Arrays (FPGAs), Coarse-grain Reconfigurable Arrays (CGRAs), Domain processors (GPU, DNN engines, DSPs), algorithm specific accelerators (graph processor, video codec, encryption engine)
‣ The programmable architectures start from a standard “execution model” - ISA. Accelerators start from an algorithm or set of algorithms.
‣ We learn their structure and degrees of freedom in functionality and implementation tradeoffs
‣ Provides “Top-down” knowledge
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CS250, UC Berkeley FA20Lecture 01, Introduction 1
‣ Components of Digital Design: 3. Design Representations/Methodologies/Tools ‣ Representations give us a way to abstract, enter, manipulate,
analyze, our design leading to an implementation. ‣ Ex: data-flow graphs, Bool Equations, Verilog , logic gate netlists, GDS
‣ Methodology - roadmap that we follow to implement our designs ‣ The tools analyze and automate aspects of implementaion and
optimization (convert from one from to another)
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The context for CS250
CS250, UC Berkeley FA20Lecture 01, Introduction 1
You’ve learned the basics already‣ What we assume you know at this point:
1. Circuits: Basic logic design and optimization, CMOS implementations of logic functions and state elements. Structure of basic building blocks: arithmetic, FSMs, memory blocks, edge-triggered synchronous clocking.
2. Architecture: Basic RISC CPU structure, FPGA fabric structure, and in principle - how to design an accelerator
3. Tools: some design flow for ASIC or FPGA - from Verilog/VHDL to mapping to chip or fabric. Most likely with industry standard tools from Cadence, Synopsys, and Mentor Graphics.
‣ We assume that you understand how to map function to circuits, but not much experience with optimization.
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CS250, UC Berkeley FA20Lecture 01, Introduction 1
Berkeley Digital Design Classes‣ CS152/252: ‣ CPU structure, CMPs, memory systems, on-chip interconnect (NoCs)
‣ EECS151/251A: ‣ Focus on RISC-V microarchitecture, Xilinx FPGA fabric architecture.
Synchronous logic design. Arithmetic blocks. ASIC + FPGA design flows.
‣ EE241B: ‣ Extensive CMOS transistor level circuit analysis and optimization for
performance/cost/power. ‣ EE250: ‣ More practice with design tools. Synopsys with “academic” process
design kit (PDK) ‣ Alternative design methodology - Chisel based (not Verilog/VHDL) ‣ Emphasis on design optimization - Design Space Exploration (DSE)
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CS250, UC Berkeley FA20Lecture 01, Introduction 1
Design Optimization‣ Industrial View: ‣ Meeting some set of prescribed (or desired) constraints on
power, cost, and performance. ‣ How do we define these?
‣ Academic View: ‣ Mapping the Pareto Optimal Frontier
‣ How do we find these points? 9
Performance
Costlow-performance at low-cost
high-performance at high-cost
“Pareto Optimal” Frontier
(# of components)
(tasks/sec)
CS250, UC Berkeley FA20Lecture 01, Introduction 1
Design Space Exploration‣ CS250 has traditionally focussed on: ‣ methodology for DSE ‣ practice on some particular function (accelerator, processor,
…) ‣ Processor cores, Memory controllers, image processors, cordic
blocks, audio processor, radio/communications blocks ‣ Mapping the Pareto frontier has been the goal
‣ What are the tradeoffs to be made? ‣ Pipelining, Serialization versus parallelization gives us a way
to trade area for performance, and area for power. ‣ Designs are specified as “parameterized generators” allowing
parameter sweeps to build and analyze a variety of designs. ‣ Chisel helps in building generators.
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EE141
Chisel: Constructing Hardware In a Scala Embedded Language❑ Embeds hardware-description language in Scala,
using Scala’s extension facilities: Hardware module is just data structure in Scala
❑ Different output routines generate different types of output (C, FPGA-Verilog, ASIC-Verilog) from same hardware representation
❑ Full power of Scala for writing hardware generators ▪ Object-Oriented: Factory objects, traits, overloading, etc. ▪ Functional: Higher-order functions, anonymous
functions, currying ▪ Compiles to JVM: Good performance, Java
interoperability
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Chisel Program
C++ code FPGA
VerilogASIC
Verilog
Software Simulator
C++ Compiler
Scala/JVM
FPGA Emulation
FPGA Tools
GDS Layout
ASIC Tools
CS250, UC Berkeley FA20Lecture 01, Introduction 1
ASIC tools, PDKs, Fabrication‣ Chip design relies heavily on CAD tools: ‣ Logic synthesis/mapping, layout, functional/timing/power
analysis, verification ‣ And on “process design kits” (PDK) ‣ geometric design rules, process electrical paramaters, cell
layouts, cell models for simulation and analysis, … ‣ A problem for us: ‣ commercial tools are very complex to use (some efforts recently
here with “Hammer” make it somewhat easier, though). ‣ Not well documented (companies that design chips have teams
of full-time staff to maintain tools). ‣ Support has been poor - companies focus on paying customers. ‣ PDKs for real IC processes are available only under NDA.
“Instructional” PDKs have been used instead, designs can't be fabricated
‣ Open source design tools and PDK?
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From Tim Ansell, Google
CS250, UC Berkeley FA20Lecture 01, Introduction 1
New: Open Source ASIC tools, PDKs, Shuttle runs
‣ Tim Ansell - Google
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From Tim Ansell, Google
OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII - completed SoC design examples have fabricated.
CS250, UC Berkeley FA20Lecture 01, Introduction 1
Open PDK‣ Skywater Technology - 130nm Fabrication
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From Tim Ansell, Google
CS250, UC Berkeley FA20Lecture 01, Introduction 1
Google Sponsored Shuttle Runs
‣ Wouldn’t it be good to actually fabricate what you designed?
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From Tim Ansell, Google
CS250, UC Berkeley FA20Lecture 01, Introduction 1
Connecting CS250 Project to Research
‣ Traditionally this course (and perhaps others) tries to make a connection to ongoing research projects.
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Berkeley Open Reconfigurable Architecture (BORCA)
■ Design a "better" architecture and make it publicly available as a starting point for new research and development (academia and industry).
■ RISC architectures a good example (RISC-V). ■ A rethinking of reconfigurable architectures
through a detailed evaluation of: ■ current architectures, ■ scholarly work, ■ application targets, and ■ design methodology trends.
Problems with Existing Reconfigurable Architectures
■ Primarily designed as standalone chips need a IP "block" for SOCs.
■ Current tool chains are too slow need new interconnect architectures, better tools
■ State of the art arrays probably not be power/area efficient re-architect the arrays and use novel circuits
■ Existing arrays have proprietary architectures and tools, stifling innovation open architectures and tools
■ Commercial arrays don’t support dynamic reconfiguration well.
Approach
1) Build on and improve open source mapping tools. 2) Develop agility in ASIC block design from the start. 3) Understand current state-of-art array designs. 4) Review past studies on architecture variations and on tools. 5) Assemble set of benchmarks. 6) Focus on interconnect. 7) Build "generator" for area/power efficient reconfigurable array.
Architecture innovation must go hand in hand with tool development.Architecture innovation must go hand in hand with chip realizations.
Propose architecture Develop Physical model
Evaluate efficiency on benchmarks
Should lead to an understanding of cost benefit tradeoffs (map out the Pareto optimal frontier).
CS250, UC Berkeley FA20Lecture 01, Introduction 1
Proposals for this semester:‣ Use the open-source design tools: openLane
risky - tools might break (but we have the source!) ‣ Use with open-source PDK: Sky130-PDK ‣ Focus design project on open reconfigurable architecture ‣ Target shuttle run for fabrication
Can we make a November tapeout deadline?
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CS250, UC Berkeley SP16Lecture 01, Introduction 1
Mandatory Survey1.Describe your experience(s) with previous courses in digital design.
For instance, did you take EECS151/251A at UCB and which lab did you take? If not at UCB, where and which digital design courses did you take. Give project details. 2.Outside of your course experience described above, have you had any
additional experience doing digital design and using ASIC and/or FPGA tools? 3.Have you ever studied design tools from the point of view of the
algorithms that they use? If so, describe your experience. 4.What do you expect to get out of this course? What is your main
objective in taking it? 5.We are proposing to focus this semester on the design of
reconfigurable arrays (FPGAs and perhaps coarse grain arrays). What do you think about that proposal? 6.Do you anticipate a timezone mismatch or any other issue that would
prevent you from participating live in the class meetings over zoom?
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CS250, UC Berkeley SP16Lecture 01, Introduction 1
End of Introduction part 1
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