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CSEE 3827: Fundamentals of Computer Systems
Lecture 6
February 9, 2009
Martha Kimmartha@cs.columbia.edu
CSEE 3827, Spring 2009 Martha Kim
Combinational circuits
• Combinational circuits are stateless
• The outputs are functions only of the intputs
2
Combinational circuit OutputsInputs
CSEE 3827, Spring 2009 Martha Kim
Sequential circuits
• Sequential circuits have state
• The outputs are functions of both the current inputs and the current state of the circuit
3
Sequential circuit
OutputsInputs Combinational circuit
Storage elements
next state
current state
CSEE 3827, Spring 2009 Martha Kim
Design procedure
1.Specification
(define desired behavior)
2.Formulation
(derive a truth table or boolean equations that relate outputs to inputs)
3.Optimization
4.Technology Mapping
(transform circuit to use available gates (e.g., NANDs))
5.Verification
(verify that final design behaves correctly)
4
CSEE 3827, Spring 2009 Martha Kim
Hierarchical design
5
© 2008 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e
3-4
(a)
A0 N0MX
MX
MX
MX
ME
N1
N2
N3
E
B0
A1
B1
A2
B2
A3
B3
Ai
Ni
MXBi
N0N1 E
MEN2N3
(b) (c)
(4-bit equality comparator)
Enabling
CSEE 3827, Spring 2009 Martha Kim
Enabled circuits
7
© 2008 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e
3-15
XF
EN
(a)
ENX
F
(b)
Output is enabled only when input ‘ENABLE’ signal is asserted
CSEE 3827, Spring 2009 Martha Kim
Enabling example: Car control
• Inputs:
• IG (ignition switch)
• LS (light switch)
• RS (radio switch)
• WS (power window switch)
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• Outputs
• L (lights)
• R (radio)
• W (power windows)
What are the enabling relationships?
What is the truth table for this system?
Decoding
CSEE 3827, Spring 2009 Martha Kim
Decoder (1:2)
10
Converts n-bit input to m-bit output, where n <= m <= 2n
© 2008 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e
3-17
A D0 D1
0 1 01 0 1
(a) (b)
D1 AA
D0 A
CSEE 3827, Spring 2009 Martha Kim
Decoder (2:4)
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n
© 2008 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e
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A1
0011
A0
0101
D0
1000
D1
0100
D2
0010
D3
0001
(a)
D0 A1 A0
D1 A1 A0
D2 A1 A0
D3 A1 A0
(b)
A1
A0
CSEE 3827, Spring 2009 Martha Kim
Decoder (3:8)
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© 2008 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e
3-19
3-to-8 Line decoder
1-to-2-Line decoders
4 2-input ANDs 8 2-input ANDs
2-to-4-Linedecoder
D0A0
A1
A2
D1
D2
D3
D4
D5
D6
D7
Hierarchical design: use small decoders to build bigger decoder
CSEE 3827, Spring 2009 Martha Kim
Decoder-based circuits
• If decoders produce minterms...
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3:8decoder
AB
C
‘A’B’C‘A’BC‘AB’C‘ABCA’B’CA’BCAB’CABC
Encoding
CSEE 3827, Spring 2009 Martha Kim
Encoders
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Inverse of a decoder: converts m-bit input to n-bit output, where n <= m <= 2n
© 2008 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e
T 3-7
TABLE 3-7Truth Table for Octal-to-Binary Encoder
Inputs Outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000
00001111
00110011
01010101
CSEE 3827, Spring 2009 Martha Kim
Encoders
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Inverse of a decoder: converts m-bit input to n-bit output, where n <= m <= 2n
© 2008 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e
T 3-7
TABLE 3-7Truth Table for Octal-to-Binary Encoder
Inputs Outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000
00001111
00110011
01010101
CSEE 3827, Spring 2009 Martha Kim
Priority Encoder
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© 2008 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e
T 3-8
Inputs Outputs
D3 D2 D1 D0 A1 A0 V
00001
0001X
001XX
01XXX
X0011
X0101
01111
TABLE 3-8Truth Table of Priority Encoder
Code conversion
CSEE 3827, Spring 2009 Martha Kim
General code conversion
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© 2008 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e
3-3
(a) Segment designation
a
bf
e cg
d(b) Numeric designation for display
Multiplexers
CSEE 3827, Spring 2009 Martha Kim
Multiplexers
• Combinational circuit that selects binary information from one of many input lines and directs it to one output line
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(2 inputs)n
(n selection bits)
(1 output)
CSEE 3827, Spring 2009 Martha Kim
Truth table for a 4:1 mux
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i0i1i2i3
s1 s0
o
CSEE 3827, Spring 2009 Martha Kim
Internal mux organization
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© 2008 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 4e
3-26
S1Decoder
S0
Y
S1Decoder
S0
Y
S1Decoder
4 2 AND-ORS0
Y
I2
I3
I1
I0
CSEE 3827, Spring 2009 Martha Kim
Multibit multiplexing
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