Dark silicon and end of multi-core scaling

ByChinthaka Henadeera

Seminar of Dependable systems -SS 2012

Presentation outline1. Introduction

2. Motivation

3. Scaling models3.1 Device scaling model3.2 Single core scaling model3.3 Multi-core scaling model

4. Model combinations

5. Evaluation of model combinations

6. Conclusions

7. References

Introduction

● Transistors of chips are doubled every 18 months according to the Moore's law.

● Moore's law is based on Dennard's scaling.● Failure of Dennard's scaling has motivated

chip designers towards multi-core chips in order to exploit the Moore's law continuously.

Motivation

● Hot question

“Can we gain 32 times performance from multi-core processors in 2024 with respect to 2008 ?”

Scaling models

● To model the behaviour of future multicore processors , 3 scaling models are created and are combined.

1) Device scaling model (DevM)

2) Single core scaling model (CorM)

3) Multi-core scaling model (CmpM)

Overview

Figure. 1 Overview of models and methodology [1]

Device scaling model (DevM)

● To determine area, frequency and power of future tech nodes.

● Uses ITRS projections and conservative device scaling projections.

Device scaling model cont.Table 1 Scaling factors for ITRS and Conservative projections

Single core scaling model (CorM)

● Pareto-optimal frontiers for area/performance and power/performance are created using over 150 processors.

Single core scaling model (CorM)

contd.

Figure 2(a) Power/performance frontier at 45 nm[1]

Figure 2(b) Area/performance frontier At 45 nm [1]

Multi-core scaling model (CmpM)

● There are 2 Multi-core scaling models

1) Amdahl’s Law Upper-bound model (CmpMU)

2) Realistic model (CmpMR)

Amdahl’s Law Upper-bound model (CmpM

U)

● Amdahl's law is extended in such a way that can describe symmetric, asymmetric, dynamic and composed multi-core topologies.

● CmpMU model provides a strict upper bound

of parallel performance.

Amdahl’s Law Upper-bound modelcontd.

Symmetric Asymmetric Dynamic Composed

CPU multicore

Serial 1 ST Core 1 Large ST Core 1 Large ST Core

1 Large ST Core

Parallel N ST Core 1 Large ST Core + N small ST Cores

N small ST Cores

N small ST Cores

GPU multicore

Serial 1 MT Core(1 Thread)

1 Large ST Core (1 Thread)

1 Large ST Core (1 Thread)

1 Large ST Core(1 Thread)

Parallel N MT Core(Multiple threads)

1 Large ST Core (1 thread) + N small MT cores(Multiple threads)

N Small MT Cores (Multiple threads)

N Small MT Cores (Multiple threads)

Table 2 . CPU and GPU Topologies

ST Core: Single-tread core MT Core: Many-thread core

Realistic model (CmpMR)

● Micro-architectural features, application behaviours, physical constraints, multi-core topologies are considered for this model.

Realistic model (CmpMR) contd.

Figure 3 Equations used for CmpMR

Realistic model (CmpMR) contd.

● Speed up of realistic model is calculated using,

Figure 4

Realistic model (CmpMR) contd.

● Speed up of realistic model is calculated using,

Figure 4

Model combinations

● DevM x CorM● DevM x CorM x CmpM

Evaluation of model combinationsDevM x CorM

Figure 5. DevM x CorM

Evaluation of model combinationsDevM x CorM x CorM

u

Figure 6 DevM x CorM x CorMu

Results of combining modelsDevM x CorM x CmpM

R

Figure 7 DevM x CorM x CmpMR

under Symmetric topology and ITRS scaling

Results of combining models contd.

Table 3.

Conclusions

● Dark Silicon percentage increases with scaling down of the tech node.

● ITRS projection is quite optimistic and it shows

● 7.9x of speed up in 2024 with respect to 2008

● 32x of speed up is impossible.

References

[1] Hadi Esmaeilzadeh, Emily Blem, Renée St. Amant, Karthikeyan Sankaralingam, Doug Burger. Dark Silicon and the End of Multicore Scaling 2010

Questions

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Thank you