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transcript
Package Diagrams
Data Sheet
FPGA-DS-02053-6.3
April 2021
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-DS-02053-6.3
Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice.
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 3
Contents 1. 16-Ball WLCSP Package Option 1: iCE40 LP .................................................................................................................. 6 2. 16-Ball WLCSP Package Option 2: iCE40 UltraLite™ ..................................................................................................... 7 3. 20-Pin (300-Mil) CERDIP Package ................................................................................................................................. 8 4. 20-Pin LCC Package ....................................................................................................................................................... 9 5. 20-Pin PLCC Package ................................................................................................................................................... 10 6. 20-Pin Plastic DIP Package .......................................................................................................................................... 11 7. 24-Pin (300-Mil) CERDIP ............................................................................................................................................. 12 8. 24-Pin Plastic DIP ........................................................................................................................................................ 13 9. 24-Pin QFNS Package .................................................................................................................................................. 14 10. 25-Ball WLCSP Package (0.40 mm Pitch) .................................................................................................................... 15 11. 25-Ball WLCSP Package (0.35 mm Pitch) .................................................................................................................... 16 12. 28-Pin LCC Package ..................................................................................................................................................... 17 13. 28-Pin PLCC Package ................................................................................................................................................... 18 14. 28-Pin Plastic DIP Package .......................................................................................................................................... 19 15. 28-Pin SSOP Package .................................................................................................................................................. 20 16. 30-Ball WLCSP Package ............................................................................................................................................... 21 17. 32-Pin QFN Package Option 1: Power Manager II, iCE40™ ........................................................................................ 22 18. 32-Pin QFN Package Option 2: MachXO2™ ................................................................................................................ 23 19. 32-Pin QFN Package Option 3: MachXO2 SG32C ........................................................................................................ 24 20. 36-Ball ucBGA Package ............................................................................................................................................... 25 21. 36-Ball ucfBGA Package: iCE40 Ultra™ ....................................................................................................................... 26 22. 36-Ball WLCSP Package Option 1: iCE40 Ultra ............................................................................................................ 27 23. 36-Ball WLCSP Package Option 2: MachXO2, MachXO3™ .......................................................................................... 28 24. 36-Ball WLCSP Package Option 3: CrossLink™ ............................................................................................................ 29 25. 44-Pin JLCC Package .................................................................................................................................................... 30 26. 44-Pin PLCC Package ................................................................................................................................................... 31 27. 44-Pin TQFP Package .................................................................................................................................................. 32 28. 44-Pin LQFP Package .................................................................................................................................................. 33 29. 48-Pin TQFP Package .................................................................................................................................................. 34 30. 48-Pin LQFP Package .................................................................................................................................................. 35 31. 48-Pin QFN Package: L-ASC10, iCE40 Ultra, iCE40 UltraPlus, MachXO2 ..................................................................... 36 32. 49-Ball caBGA Package ............................................................................................................................................... 37 33. 49-Ball ucBGA Package ............................................................................................................................................... 38 34. 49-Ball WLCSP Package ............................................................................................................................................... 39 35. 56-Ball csBGA Package ................................................................................................................................................ 40 36. 64-Ball csBGA Package ................................................................................................................................................ 41 37. 64-Pin QFNS Package .................................................................................................................................................. 42 38. 64-Ball ucBGA Package ............................................................................................................................................... 43 39. 64-Ball ucfBGA Package .............................................................................................................................................. 44 40. 64-Pin LQFP Package .................................................................................................................................................. 45 41. 68-Pin JLCC Package .................................................................................................................................................... 46 42. 68-Pin PLCC Package ................................................................................................................................................... 47 43. 72-Pin QFN Package Option 1: CrossLink™-NX ........................................................................................................... 48 44. 72-Pin QFN Package Option 2: MachXO3D ................................................................................................................. 49 45. 72-Pin WLCSP Package: CrossLink-NX ......................................................................................................................... 50 46. 80-Ball ctfBGA Package ............................................................................................................................................... 51 47. 80-Ball ckfBGA Package .............................................................................................................................................. 52 48. 81-Ball csBGA Package ................................................................................................................................................ 53 49. 81-Ball csfBGA Package .............................................................................................................................................. 54 50. 81-Ball ucBGA Package ............................................................................................................................................... 55 51. 81-Ball WLCSP Package ............................................................................................................................................... 56 52. 84-Pin CPGA Package .................................................................................................................................................. 57
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-DS-02053-6.3
53. 84-Pin PLCC Package ................................................................................................................................................... 58 54. 84-Pin QFN Package .................................................................................................................................................... 59 55. 100-Ball caBGA Package ............................................................................................................................................. 60 56. 100-Ball csBGA Package .............................................................................................................................................. 61 57. 100-Ball fpBGA Package .............................................................................................................................................. 62 58. 100-Pin PQFP Package ................................................................................................................................................ 63 59. 100-Pin LQFP Package Option 1: MachXO2, MachXO™, ispMACH® 4000 .................................................................. 64 60. 100-Pin VQFP Package Option 2: iCE40 ...................................................................................................................... 65 61. 120-Pin PQFP Package ................................................................................................................................................ 66 62. 121-Ball caBGA Package (9 mm x 9 mm Body) ........................................................................................................... 67 63. 121-Ball csBGA Package .............................................................................................................................................. 68 64. 121-Ball csfBGA Package ............................................................................................................................................. 69 65. 121-Ball ucBGA Package ............................................................................................................................................. 70 66. 128-Pin PQFP Package ................................................................................................................................................ 71 67. 128-Pin LQFP Package ................................................................................................................................................. 72 68. 132-Ball csBGA Package Option 1: MachXO2, MachXO, LatticeXP2™ ........................................................................ 73 69. 132-Ball csBGA Package Option 2: iCE40 .................................................................................................................... 74 70. 132-Ball ucBGA Package ............................................................................................................................................. 75 71. 133-Pin CPGA Package ................................................................................................................................................ 76 72. 144-Ball csBGA Package .............................................................................................................................................. 77 73. 144-Ball fpBGA Package .............................................................................................................................................. 78 74. 144-Pin LQFP Package ................................................................................................................................................. 79 75. 160-Pin PQFP Package ................................................................................................................................................ 80 76. 176-Pin LQFP Package ................................................................................................................................................. 81 77. 184-Ball csBGA Package .............................................................................................................................................. 82 78. 196-Ball caBGA Package ............................................................................................................................................. 83 79. 196-Ball csBGA Package .............................................................................................................................................. 84 80. 208-Ball ftBGA Package .............................................................................................................................................. 85 81. 208-Ball fpBGA Package .............................................................................................................................................. 86 82. 208-Pin PQFP Package ................................................................................................................................................ 87 83. 225-Ball ucBGA Package ............................................................................................................................................. 88 84. 237-Ball ftBGA Package .............................................................................................................................................. 89 85. 256-Ball caBGA Package ............................................................................................................................................. 90 86. 256-Ball csfBGA Package ............................................................................................................................................. 91 87. 256-Ball ftBGA Package Option 1: ispMACH 4000, MachXO, LatticeXP2 ................................................................... 92 88. 256-Ball ftBGA Package Option 2: LatticeECP3™ ........................................................................................................ 93 89. 256-Ball ftBGA Package Option 3: MachXO2 .............................................................................................................. 94 90. 256-Ball fpBGA Package .............................................................................................................................................. 95 91. 256-Ball SBGA Package ............................................................................................................................................... 96 92. 272-Ball BGA Package ................................................................................................................................................. 97 93. 284-Ball csBGA Package .............................................................................................................................................. 98 94. 285-Ball csfBGA Package ............................................................................................................................................. 99 95. 289-Ball csBGA Package (9.5 mm x 9.5 mm Body) ................................................................................................... 100 96. 320-Ball SBGA Package ............................................................................................................................................. 101 97. 324-Ball caBGA Package ........................................................................................................................................... 102 98. 324-Ball csfBGA Package ........................................................................................................................................... 103 99. 324-Ball ftBGA Package ............................................................................................................................................ 104 100. 328-Ball csBGA Package ............................................................................................................................................ 105 101. 332-Ball caBGA Package ........................................................................................................................................... 106 102. 352-Ball SBGA Package ............................................................................................................................................. 107 103. 381-Ball caBGA Package ........................................................................................................................................... 108 104. 388-Ball BGA Package ............................................................................................................................................... 109 105. 388-Ball fpBGA Package ............................................................................................................................................ 110 106. 400-Ball caBGA Package ........................................................................................................................................... 111
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 5
107. 416-Ball fpBGA Package ............................................................................................................................................ 112 108. 432-Ball SBGA Package ............................................................................................................................................. 113 109. 484-Ball caBGA Package (19 mm x 19 mm Body) ..................................................................................................... 114 110. 484-Ball fpBGA Package ............................................................................................................................................ 115 111. 484-Ball fcBGA Package: Mach™-NX ........................................................................................................................ 116 112. 516-Ball fpBGA Package ............................................................................................................................................ 117 113. 554-Ball caBGA Package ........................................................................................................................................... 118 114. 672-Ball fpBGA Package ............................................................................................................................................ 119 115. 676-Ball fpBGA Package ............................................................................................................................................ 120 116. 676-Ball fcBGA Package ............................................................................................................................................ 121 117. 680-Ball fpBGA Package ............................................................................................................................................ 122 118. 680-Ball fpSBGA Package .......................................................................................................................................... 123 119. 756-Ball caBGA Package ........................................................................................................................................... 124 120. 900-Ball fpBGA Package ............................................................................................................................................ 125 121. 1020-Ball Organic fcBGA Package ............................................................................................................................. 126 122. 1020-Ball Organic fcBGA Package Rev. 2 .................................................................................................................. 127 123. 1036-Ball ftSBGA Package......................................................................................................................................... 128 124. 1152-Ball Organic fcBGA Package Option 1: LatticeSC/SCM40 ................................................................................ 129 125. 1152-Ball Organic fcBGA Package Option 2: LatticeSC/SCM80 & SC/SCM115 ......................................................... 130 126. 1152-Ball Ceramic fcBGA Package ............................................................................................................................ 131 127. 1152-Ball fpBGA Package .......................................................................................................................................... 132 128. 1156-Ball fpBGA Package .......................................................................................................................................... 133 129. 1704-Ball Organic fcBGA Package ............................................................................................................................. 134 130. 1704-Ball Ceramic fcBGA Package ............................................................................................................................ 135 Appendix A. Package Archive ........................................................................................................................................... 136
32-Pin QFN (Punch Singulated) Package ....................................................................................................................... 136 Technical Support Assistance ........................................................................................................................................... 137 Revision History ................................................................................................................................................................ 138
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 6
1. 16-Ball WLCSP Package Option 1: iCE40 LP Dimensions in Millimeters
Cccc
C1A
A
aaa(4X)
.015
.05 BMM
CC A
PIN #1 ID FIDUCIALLOCATED IN THIS AR EA
REF. Min. Nom. Max.
0.4130.122
0.188
0.452
0.152
0.218
0.491
0.182
0.248
1.40 BSC
1.48 BSC
1.05 BSC
1.05 BSC
0.35 BSC
0.03
0.03
0.175
0.215
4
AB
CD
3 .16 X bE
BA
D
ALL DIMENSIONS AND TOLERANCE PER ASME Y 14.5M - 1994.
ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSION b IS MEASURES AT THE MAXIMUM BUMP DIAMETERPARALLEL TO PRIMARY DATUM C.
PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BUMPS.
BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THEPACKAGE BODY.
NOTES:
3
4
5
1.
2.
4 3 2 1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 7
2. 16-Ball WLCSP Package Option 2: iCE40 UltraLite™ Dimensions in Millimeters
Cccc
C1A
A
aaa(4X)
eeeddd B
MM
CC A
ALL DIMENSIONS AND TOLERANCE PER ASME Y 14.5M - 1994.
ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSION b IS MEASURES AT THE MAXIMUM BUMP DIAMETER
PARALLEL TO PRIMARY DATUM C.
PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BUMPS.
BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE
PACKAGE BODY.
NOTES:
3
4
5
1.
2.
TOP VIEW
BOTTOM VIEW
SIDE VIEW
sbe s
e
sbd D1
s
e
E1
163 b
A
B
C
D
4 3 2 1
5
D
BE
A
PIN #1 FIDUCIALLOCATED IN THIS AREA
REF. Min. Nom Max.A
A1bD
ED1E1es
sbDsbEaaacccdddeee
0.4130.1220.188
0.0670.067
0.4520.1520.218
1.409 BSC1.409 BSC
BSCBSCBSC
1.051.050.35
0.180
0.0710.071
0.0720.072
0.030.03
0.0500.015
4
0.491
0.1820.248
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-DS-02053-6.3
3. 20-Pin (300-Mil) CERDIP Package Dimensions in Inches
.100 BSC
.300 REF
BASE METAL
INCHES
DIMENSIONS A, A1 AND L ARE MEASURED WITH THE5. 1E
ALLOWED LEAD TIP POSITION RANGE.
E3 IS TO BE MEASURED AT THE LEAD TIPS.
PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS-003.
6.
7.NL
e
.125
E3
E2
.325
OVERRUN AND MENISCUS, AND LID TO BASE MISMATCH.DIMENSIONS D AND E1 INCLUDE ALLOWANCE FOR GLASS
.060 INCHES FROM THE LEAD TIP.MEASUREMENTS TO BE TAKEN AT A MINIMUM OF
ALL DIMENSIONS ARE IN INCHES.
DIMENSIONING AND TOLERANCING PERANSI Y14.5M.
4.
3.
2.
1.1A
E
D
.308
.942
c1
c
.008
.008
b2
b1
.045
A2
b
X4 3b
B
A
LO
-MIN.
S
MY
(b)
3
.296.288
20
.200-
.410-
.045
.325
.970
-
.950
.012
.014-
-
.010
.065
.021
-
.018
.023
.175
-
-
- -
MAX..200
NOM.-
E2
LEAD FINISHWITH
E3
b2
M.010
b
C
BASE PLANE
SEATING PLANE
A1
Z Z
B
(c) c1
b1
A
e
4
D
L 7
A2
A
e/2
DETAIL A
E
N/2
N
1
4
E1
B
(DATUM A)
c
(DATUM B)
E
NOTES:
DETAIL ASECTION Z-Z
TOP VIEW
SIDE VIEW
.015
.140
.015
.015
.023
.280
b3
C A
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 9
4. 20-Pin LCC Package Dimensions in Inches
OF .010 INCHES MAXIMUM ABOVE THE DIMENSION SHOWN
D2
D4
D
L (19 PLACES)
FLATNESS TOLERANCE IS .004 INCHES PER INCH.
NOT TO EXCEED .005 INCHES MAXIMUM PER SIDE.
DIMENSIONS D AND E MAY HA VE MATERIAL PROTRUSION
ALL DIMENSIONS ARE IN INCHES.
DIMENSIONING AND TOLERANCING PERANSI Y14.5.
3
4.
3.
2.
1.
3
E
B
(3 PLACES)
X 45
X 45
.030
.050
.020
.010
A
.075
.042
.270
.342
.270
.342
.022
.007
.054
.064
MIN.
E4
L1
L
e
A2
e
L1
A
E2
E
D4
D2
D
B
A2
A1
S
B
MY
L
O
.315
.095
.058
.050 BSC
(TYPICAL)
.200
.050
.030RADIUS
MAX.
.358
.315
.358
.028
.015
.200
.089
.074
INCHES
E2 E4
4
A1
NOTES:
TOP VIEW
BOTTOM VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-DS-02053-6.3
5. 20-Pin PLCC Package Dimensions in Inches
A-B //
.007 S H
.002 S
A-B S S D
.007 S A-B H S D S
A-B S .002
3 2 1
20
A-B .007 S H
.007 S H
S S D
D S A-B S
DIMENSION APPLIES TO BASE METAL ONLY
TOP POINT OF MEASUREMENT IS DATUM
MEASUREMENT IS AT MAJOR FLAT AREA OF LOWER PLASTIC SURFACE
DEFINED BY D3/E3
ALLOWABLE PROTRUSION IS .010 PER SIDE.
8
7 ; BOTTOM POINT OF -H-
LOCATED AT TOP OF MOLD PARTING LINE AND
TO BE MEASURED AT SEATING PLANE
EXIT PLASTIC BODY AT DATUM PLANE
DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
COINCIDENT WITH TOP OF LEAD WHERE LEAD EXITS PLASTIC BODY
ALL DIMENSIONS AND TOLERANCES CONFORM TO ANSI Y14.5M-1982
DATUMS
DATUM PLANE
6
5
4 AND A-B -D-
-H-
NOTES:
CONTACT POINT
TO BE DETERMINED WHERE CENTER LEADS
-C-
-H-
7
7
7
E E1 -D-
E3 E3
6
4
D
D1 6
-B- 4
4 -D-
0.05 0
D3
D3
-A-
D/E
(N-4PLACES)
D2/E2 D2/E2
-H- 3
A1
A
-C-
SEATING PLANE
-A-B-
-A-B-
-D-
5 5
.00 4 C
A A
A2
.02 0 (MIN)
PI N 1 ID ZONE
DETAIL "J"
SECTION A-A
.02 1
.01 3
8
.01 05
.00 75
.01 8
.01 3
.01 25
.00 75
8
ALL DIMENSIONS IN INCHES
H S .007 D S S A-B .03 2
.02 6
.007 M A-B C D S S
.02 1
.01 3
DETAIL "J" (TYP ALL SID ES)
SEATING PLANE .02 5 MIN.
.04 5 MIN.
3
1.
2.
-C-
L
E
N
E2 E3
E1
D
D2 D3
D1
A1 A2
A
S
Y
B M
O MAX. NOM. MIN.
20
.395 .390 .385
.353
.155
.075
.141
.350
.169
.356
.172
.105
-
.090
.062
.165
.120
.083
.180
.075
.169
.356
.395
.141
.350
.385
.155
.353
.390
BOTTOM VIEWTOP VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 11
6. 20-Pin Plastic DIP Package Dimensions in Inches
.000
.115
-
eCeB
L-
-
.130 47.0607.430
.150
OF LEAD , WHERE LEAD EXITS BODY11. DATUM PLANE -H- COINCIDENT WITH THE BOTTOM
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010
8. N IS THE MAXIMUM NUMBER OF LEAD
2. DIMENSIONING AND TOLERANCING PER
3. DISTANCE BETWEEN LEADS INCLUDING DAMBAR
THE PACKAGE SEATED IN JEDEC SEATING4. DIMENSIONS A, A1 & L ARE MEASURED WITH
DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
6. E AND eA MEASURED WITH THE LEADS CONSTRAINEDTO BE PERPENDICULAR TO DATUM -C-
7. eB AND eC ARE MEASURED AT THE LEAD TIPS
9. POINTED OR ROUNDED LEAD TIPS ARE PREFERRED
PROTRUSIONS SHALL NOT EXCEED .010INCLUDE DAMBAR PROTRUSIONS. DAMBAR
10. b2 MAXIMUM DIMENSION DOES NOTTO EASE INSERTION
WITH THE LEADS UNCONSTRAINED.
POSITIONS.
5. DIMENSIONS D, D1 AND E1
1. CONTROLLING DIMENSION: INCH.
PLANE GAUGE GS-3.
PROTRUSIONS TO BE .005 MINIMUM.
ANSI Y14.5M
c .008 .014.010
E .300
.240E1
eAe
.310
.100 BSC
.300 BSC
.250
.005
.008
.980
D1
c1D
-
.0101.030
.325
6
6.280 5
- 5
.0111.060 5
.115A 2
.014
.014
.045b1b
b2.018
.018
.060
MIN.
.015
-
1
LO
AA -
-NOM.
.195
10
.020
.022
.070
- 44
MAX..210
TE
N = 20
INCHESS
BM
Y
NO
eC
PLANEGAGE
PLANESEATING
.010
b
A1
10
b2
BASE PLANE
D Z
-A- 5
-C-
4x
CMD1
5
Le -H-
.015
A
Z
A2
4
c
N
N/2 1
E1 (c)
(b)
c1
5
-B-b1
BASE METAL
WITHLEA D FINISH
eB
7
6
eA
DE TAIL SEE
A
6
E
DETAIL ANOTES:
SECTION Z-Z
CL
CLTOP VIEW
SIDE VIEW
.130
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-DS-02053-6.3
7. 24-Pin (300-Mil) CERDIP Dimensions in Inches
BASE METAL
.100 BSC
.300 REF
INCHES
DIMENSIONS A, A1 AND L ARE MEASURED WITH THE5. E2
ALLOWED LEAD TIP POSITION RANGE.
E3 IS TO BE MEASURED AT THE LEAD TIPS.
PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS-003.
6.
7.NL
E3e
.325
OVERRUN AND MENISCUS, AND LID TO BASE MISMATCH.
DIMENSIONS D AND E1 INCLUDE ALLOWANCE FOR GLASS
.060 INCHES FROM THE LEAD TIP.
MEASUREMENTS TO BE TAKEN AT A MINIMUM OF
ALL DIMENSIONS ARE IN INCHES.
DIMENSIONING AND TOLERANCING PERANSI Y14.5M.
4.
3.
2.
1.1A
c
E1E
.280
.308Dc1
1.242.008
b2b1
.045
.015
A2b
.140
(b)
A
L
O
-MIN.
S
B
MY
3
.200-24
.410-
.014
.296
.325-.288
1.270.012
1.250.010
.065
.021
--
.018.023.175
--
MAX..200
NOM.
--
-
b
.010
BASE PLANE
SEATING PLANE
C
b2
A1
7L
(c)
CM Bb1
Z Z
LEAD FINISH
c1
WITH
4
D
e
A2
A
A
E
N/2
e/2N
B
E1
1
4
(DATUM A)
E2
c
(DATUM B)
E
E3
NOTES:
SECTION Z-Z
TOP VIEW
SIDE VIEW
A
.015
.015
.008
.125
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 13
8. 24-Pin Plastic DIP Dimensions in Inches
.130eCL
eB---
.000
.115.060.150
.43077
OF LEAD , WHERE LEAD EXITS BODY11. DATUM PLANE -H- COINCIDENT WITH THE BOTTOM
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010
8. N IS THE MAXIMUM NUMBER OF LEAD
2. DIMENSIONING AND TOLERANCING PER
3. DISTANCE BETWEEN LEADS INCLUDING DAMBAR
THE PACKAGE SEATED IN JEDEC SEATING4. DIMENSIONS A, A1 & L ARE MEASURED WITH
DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
6. E AND eA MEASURED WITH THE LEADS CONSTRAINEDTO BE PERPENDICULAR TO DATUM -C-
7. eB AND eC ARE MEASURED AT THE LEAD TIPS
9. POINTED OR ROUNDED LEAD TIPS ARE PREFERRED
PROTRUSIONS SHALL NOT EXCEED .010INCLUDE DAMBAR PROTRUSIONS. DAMBAR
10. b2 MAXIMUM DIMENSIONS DOES NOTTO EASE INSERTION
WITH THE LEADS UNCONSTRAINED.
POSITIONS.
5. DIMENSIONS D, D1 AND E1
1. CONTROLLING DIMENSION: INCH.
PLANE GAUGE GS-3.
PROTRUSIONS TO BE .005 MINIMUM.
ANSI Y14.5M
.010c .008 .014
1.250
.300 BSC
.100 BSC
.310
.250E
E1e
eA
.300
.240
D1
c1D
-
.010.0081.230
.005.325
.280
6
65
-
.011
1.280 55
NOM.
.018
.060
.018
.130A2 .115
b1b2
b.014
.014
.045
LO
A1A
--
.015
MIN.
.195
.022
.020
.070 10
-.210MAX.
4
4
TE
INCHES
N = 24
B
Y
S
M
ON
eC
6
PLANEGAGE
eA
eB
c
E
PLANESEATING
.010
b
A110
b2
BASE PLANE
D Z
-A- 5
-C-
4xCM
D1
5
Le -H-
.015
A
Z
A24
N
N/2 1
E1 (c)
(b)
c1
5
-B-b1
BASE METAL
WITHLEAD FINISH
7
DETAILSEE
A
6
DETAIL ANOTES:
CSECTION Z-Z
CL
L
TOP VIEW
SIDE VIEW
-
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14 FPGA-DS-02053-6.3
9. 24-Pin QFNS Package Dimensions in Millimeters
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 15
10. 25-Ball WLCSP Package (0.40 mm Pitch) Dimensions in Millimeters
Notes:1 ALL DIMENSIONS AND TOLERANCE PER ASME Y 14.5M - 1994.2 ALL DIMENSIONS ARE IN MILLIMETERS.3 DIMENSION b IS MEASURED AT THE MAXIMUM BUMP DIAMETER
PARALLEL TO PRIMARY DATUM C.4 PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BUMPS.
AA1bDE
D1E1eaaabbbcccdddeee
REF.
2.492 BSC2.546 BSC1.60 BSC1.60 BSC0.40 BSC0.0250.0600.0150.1500.050
0.6150.2300.280
0.5750.2000.250
0.5350.1700.220
PIN #1 ID FIDUCIAL
LOCATED IN THIS AREA
A
B
C
D
E
5 4 3 2 1
dd d
e e e
e
E 1
C
C
e
D 1
E B
D
C
A
aaa
2x
2x
aaa C
b25 X
TOP VIEW
BOTTOM VIEW
SIDE VIEW
A B
3
A
bbb C
ccc C
C 4A
1
Min. Nom. Max.
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16 FPGA-DS-02053-6.3
11. 25-Ball WLCSP Package (0.35 mm Pitch) Dimensions in Millimeters
Cccc
C1A
A
aaa(4X)
.015
.05 BMM
CC A
BA
Notes:1 ALL DIMENSIONS AND TOLERANCE PER ASME Y 14.5M - 1994.2 ALL DIMENSIONS ARE IN MILLIMETERS.3 DIMENSION b IS MEASURED AT THE MAXIMUM BUMP DIAMETER
PARALLEL TO PRIMARY DATUM C.4 PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BUMPS.5 BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE
PACKAGE BODY.
PIN #1 ID FIDUCIAL
LOCATED IN THIS AREA
25 X bE
D
D1e
s
e
s
E1
A
B
C
D
E
5 4 3 2 1
A
A1
b
D
E
D1
E1
e
aaa
ccc
s
REF.
1.71 BSC
1.71 BSC
1.40 BSC
1.40 BSC
0.35 BSC
0.03
0.03
0.015
0.491
0.182
0.248
0.452
0.152
0.218
0.413
0.122
0.188
BOTTOM VIEW
TOP VIEW
SIDE VIEW
5
4
3
Min. Nom. Max.
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 17
12. 28-Pin LCC Package Dimensions in Inches
OF .010 INCHES MAXIMUM ABOVE THE DIMENSION SHOWN
L (27 PLACES)
FLATNESS TOLERANCE IS .004 INCHES PER INCH.
NOT TO EXCEED .005 INCHES MAXIMUM PER SIDE.
DIMENSIONS D AND E MAY HAVE MATERIAL PROTRUSION
ALL DIMENSIONS ARE IN INCHES.
DIMENSIONING AND TOLERANCING PER
4.
3
ANSI Y14.5.
3.
2.
1.
E
B
(3 PLACES)
X 45
X 45
.030
.050
.020
.010
A
.075
.042
.370
.440
.370
.440
.022
.007
.054.064
MIN.
E4
L1L
e
3
e
D
L1
A
A2
E2ED4D2DBA2A1
S
B
MY
L
O
.403
.095
.058.050 BSC
(TYPICAL)
.300
.050
.030RADIUS
MAX.
.460
.403
.460
.028
.015
.300
.089
.074
INCHES
4
E2
D2
D4
E4
A1
NOTES:
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18 FPGA-DS-02053-6.3
13. 28-Pin PLCC Package Dimensions in Inches
A-B//
.00 7 S H
.00 2 S
A-B S SD
.007 S A-BH SS
A-B S.00 2
1 28
A-B.00 7 S H
.00 7 S H
SS D
DSA-B S
DIM ENSION APPLIES TO BASE META L ONLY
TOP POINT OF M EASUREMENT IS DA TUM
MEASUREMENT IS AT MA JOR FLAT AREA OF LOWER PLASTIC SURFACE
DEFINED BY D3/E3
ALLOW ABLE PROTRUS ION IS .010 PER SIDE.
8
7 ; BOTTOM POINT OF-H-
LOCATED AT TOP OF MOLD PARTING LINE AND
TO BE M EA SURED A T SEATING PL ANE
EXIT PLA STIC BODY AT DATUM PLANE
DIM ENSIONS D1 AND E1 DO NOT INCL UDE MOLD PROTRUSION.
COINCIDENT W ITH TOP OF LEAD W HERE L EAD EXITS PLA STIC BODY
ALL DIM ENSIONS AND TOLERA NCES CONFORM TO ANSI Y14.5M-1982
DATUMS
DATUM PLANE
6
5
4 ANDA-B -D-
-H-
NOTES:
CONTACT POINT
TO BE DETERMINED W HERE CENTER L EADS
-C-
-H-
7
7
7
E E1-D-
E3E3
6
4
D
D16
-B- 4
4-D-
D3
D3
-A-
D/E
D2/E2 D2/E2
-H- 3
A1A
-C-
SEATING PLANE
-A-B-
-A-B-
-D-
5 5
.004 C
A A
A2
.020(MIN)
PIN 1 ID ZONE
DETAIL "J"
SECTION A-A
.021
.013
8
.0105
.0075
.018
.013
.0125
.0075
8
ALL DIM ENSIONS IN INCHES
HS.00 7 D SSA-B.032
.026
.007 M A-BC DS S
.021
.013
DETAIL "J" (TYP ALL SIDES)
SEATING PLANE.025 MIN.
.045 MIN.
3
1.
2.
-C-
Y
E2
NE3
28
E1
D3E
.125
.191
.485
.450
.062
D2D1
A2D
.453
.205
.490
-
.090
MIN..165
A1A
O
B
M
L
.172
.105
NOM.
.219
.456
.083
.495
.180
.120
MAX.
S
.125
.219
.456
.495
.191
.450
.485
.205
.453
.490
0.050 (N-4PLACES)
BOTTOM VIEW TOP VIEW
SIDE VIEW
D
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 19
14. 28-Pin Plastic DIP Package Dimensions in Inches
+0.010 M A
0.015 M A B C
1.300 BSC
INCHES
.100 BSC
.300 BSC
NOM.
1.365
NL
28
.110 .130
C
B
A
ee
e
.000--
-
1Ee
E.275 .285
.300 .310
B .014
C .008
D1D 1.345
2
1BB .030
.045
A1
2AA
.120 .135.015
-
-
OB
MY
MIN.-
L
.150
.430
.060
.295
.325
.022
.015
1.385
.045
.060
.180
.150-
MAX.
S
e
B1
B
4x
B2
A
A1
A2
-A-
SEATING PLANE
D1L
C
-B-
Be
D
eA
e
CLC
PER ANSI Y14.5M-1982
DAMBAR PROTRUSIONS. DAMBAR PROTRUSIONS
9 B1 AND B2 MAXIMUM DIMENSIONS DO NOT INCLUDE
6 E AND eA MEASURED WITH THE LEADS
CONSTRAINED TO BE PERPENDICULAR TO PLANE A
8 N IS THE NUMBER OF TERMINAL POSITIONS
WITH THE LEADS UNCONSTRAINED. eC MUST BE
7 eB AND eC ARE MEASURED AT THE LEAD TIPS
FLASH OR PROTRUSION. MOLD FLASH AND
5 D AND E1 DIMENSIONS DO NOT INCLUDE MOLD
PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS-3
4 DIMENSION A, A1, AND L ARE MEASURED WITH THE
3 ALL END LEADS IN THIS FAMILY ARE 1/2 LEADS
N
E SHALL NOT EXCEED 0.010
E
-C-N/2 1
PROTRUSION SHALL NOT EXCEED 0.010
ZERO OR GREATER
1
2 DIMENSIONING AND TOLERANCING
1 CONTROLLING DIMENSION: INCHES
NOTE:
TOP VIEW
SIDE VIEW
.018
.050
.040
.010
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20 FPGA-DS-02053-6.3
15. 28-Pin SSOP Package Dimensions in Millimeters
0.55L 0.75
DIMENSIONING & TOLERANCES PER ANSI.Y14.5M-1982.
"D" & "E1" DO NOT INCLUDE MOLD FLASH ORPROTRUSIONS, BUT DO INCLUDE MOLD MISMATCHAND ARE MEASURED AT THE PARTING LINE.MOLD FLASH OR PROTRUSIONS SHALL NOT
TO BE DETERMINED AT THE SEATING PLANE
CONTROLLING DIMENSION: MILLIMETERS.
4.
EXCEED 0.20mm PER SIDE.
2.
3.
1.
0.090
R1
L1N
OC 4--
1.25 REF.28
DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION b BY MOREEXCESS OF b DIMENSION AT MAXIMUM MATERIAL CONDITION.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13mm TOTAL IN
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
THAN 0.07mm AT LEAST MATERIAL CONDITION.
BETWEEN 0.10 & 0.25mm FROM THE LEAD TIP
"N" IS THE NUMBER OF TERMINAL POSITIONS7.
6.
5.
8--
6
c
(b)
5
b1
c1
BASE METAL
10.50
DIMENSIONS
-B-
S COMMON
0.22b 0.30
7.40
5.009.90
0.090.09
E1e
E
D
c1
c1
10.20
0.65 BSC7.80
5.30
--
0.15
0.221.650.05
--MIN.
2Ab
A1
Y
O
L
A
B
M
1.75--
-
NOM.--
N
3
E1
3
D
3
-A-
SEATING PLANE
GAUGE PLANE
PARTING LINE
WITH LEAD FINISH
2 NX R R1
C
0.33
8.20
5.60
0.210.25
1.850.38
--
MAX.2.0 O
L
L1
4
A
A
0.25 BSC
DETAIL "A"
BM+ 0.20 C A S S
SEE
2A
0.10
S
PLANESEATING
Pin 1 Identifier
E
- C -
1A
A
e 5
0.15
b
+ M AC
C
B S
NOTES:
SECTION A-A
TOP VIEW
DETAIL 'A'
END VIEW
SIDE VIEW
2 1
0.95
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 21
16. 30-Ball WLCSP Package Dimensions in Millimeters
E15 4 3 2 1
sD
D1
A
B
C
D
E
Fe
sE
eDEADBUG VIEW
3 30 b
dddeee
MM
C
C
A B
PIN #1 ID FIDUCIALLOCATED IN THIS AREA
5
aaa
(4x)
B
D
AE
LIVEBUG VIEW
A
4
ccc C
C SIDE VIEWA1
Notes:1. ALL DIMENSIONS AND TOLERANCE PER ASME Y 14.5M – 1994.2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSION b IS MEASURED AT THE MAXIMUM BUMP DIAMETER PARALLEL TO PRIMARY DATUM C.
4. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BUMPS.
5. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY.
REF. Min. Nom. Max.AA1bDED1E1e
sDsE
aaaccc
dddeee
0.6000.1400.230 0.260 0.290
2.537 BSCBSCBSCBSC
2.114
2.001.60
0.400.270.260.0300.0500.0150.050
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
22 FPGA-DS-02053-6.3
17. 32-Pin QFN Package Option 1: Power Manager II, iCE40™ Dimensions in Millimeters
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 23
18. 32-Pin QFN Package Option 2: MachXO2™ Dimensions in Millimeters
5
4
3
SEATINGPLANE
0.15
C
PIN 1 ID AREA
3
1
N
DA
2X
(CORNER CHAMFER)
PIN #1 ID FIDUCIAL
B e
0.15
2X
C B 32
AC
D2
b 0.10 4 C M B
E
3
0.08 5C
A3A1
A
32X
L
0.45 TYP4X
E2
1
APPLIES TO EXPOSED PORTION OF TERMINALS.
DIMENSIONS AND TOLERANCES
EXACT SHAPE AND SIZE OF THIS
DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP.
NOTES: UNLESS OTHERWISE SPECIFIED
ALL DIMENSIONS ARE IN MILLIMETERS.2.
1.
FEATURE IS OPTIONAL.
PER ANSI Y14.5M.
SYMBOL
A
A1
A3
D
D2
E
E2
b
e
L
NOM. MAX.MIN.
0.00
3.10
0.20
0.55
0.02
3.20
0.25
0.60
0.05
3.30
0.30
0.35 0.40 0.45
0.50
0.2 REF
5.0 BSC
5.0 BSC
3.10 3.20 3.30
0.50 BSC
SIDE VIEW
TOP VIEW
BOTTOM VIEW
VIEW AVIEW A
A
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
24 FPGA-DS-02053-6.3
19. 32-Pin QFN Package Option 3: MachXO2 SG32C Dimensions in Millimeters
2x0.15 C A
A
N
D
2x0.15 C A
13
PIN 1 ID AREA
D2
L
32X32
PIN #1 ID FIDUCIAL(CORNER CHAMFER)
3
1
E2
eb 4
0.45 TYP4X
BOTTOM VIEW
0.10 M C A B0.05 M C
VIEW A
A
A1A3
0.08 C 5
E
B
TOP VIEW
VIEW A
SIDE VIEW
C
SEATINGPLANE
NOTES: UNLESS OTHERWISE SPECIFIED
1. DIMENSIONS AND TOLERANCES PER ANSI Y14.5M.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.
4. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP.
5. APPLIES TO EXPOSED PORTION OF TERMINALS.
6. JEDEC REFERENCE MO-248 AND DR-4.2.
SYMBOL MIN. NOM. MAX.
A
A1
A3
D
D2
E
E2
b
e
L
0.50
0.00
0.02 REF
5.0 BSC
3.40
3.40
0.18
0.35
0.55
0.02
3.50
5.0 BSC
3.50
0.25
0.50 BSC
0.40
0.65
0.05
3.60
3.60
0.30
0.45
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 25
20. 36-Ball ucBGA Package Dimensions in Millimeters
C4 ddd
bbb C
C
1A
A 2A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.20 0.25 03.0b
0.40 BSC
aaa
ddd
bbb
e
-
-
-
-
-
- 0.10
0.10
0.10
NOM.
0.20 BSC
2.00 BSC
2.50 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.10
MAX.
1.00
0.90
----
6
--
b
.05
.153
BMM
CC A
e
S
N
S
e
M
aaa
4X 6
D
E
B
A
5(4X)
PIN #1 ID FIDUCIAL LOCATED IN THIS AREA
BOTTOM VIEW TOP VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
26 FPGA-DS-02053-6.3
21. 36-Ball ucfBGA Package: iCE40 Ultra™ Dimensions in Millimeters
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
BOTTOM VIEW
TOP VIEW
SIDE VIEW
C
b
.05
.153
BMM
CC A
4 ddd
e
S
N
S
e
M
0.20 0.25 03.0b
0.40 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.10
0.10
NOM.
0.20 BSC
2.00 BSC
2.50 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.12
bbb C
C
MAX.
0.91
0.70
1A
aaa
4X 6
D
E
A2 A
B
A
5(4X)
- -
--
6
0.81-
6 5 4 3 2 1
A
B
C
D
E
F
0.10
PIN #1 ID FIDUCIALLOCATED IN THIS AREA
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 27
22. 36-Ball WLCSP Package Option 1: iCE40 Ultra Dimensions in Millimeters
Cccc
C1A
A
eeeddd B
MM
CC A
REF. Min. Nom. Max.
0.4130.122
0.188
0.452
0.152
0.218
0.491
0.182
0.248
2.078 BSC
2.078 BSC
1.75 BSC
1.75 BSC
0.35 BSC
0.164
0.055
0.030
ALL DIMENSIONS AND TOLERANCE PER ASME Y 14.5M - 1994.
ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSION b IS MEASURES AT THE MAXIMUM BUMP DIAMETERPARALLEL TO PRIMARY DATUM C.
PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BUMPS.
BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THEPACKAGE BODY.
NOTES:
3
4
5
1.
2.
0.157 0.172
0.0550.051 0.056
0.051 0.056
0.030
0.050
0.015
SIDE VIEW
TOP VIEWBOTTOM VIEW
sbE
sbD
s
e
D1
6 5 4 3 2 1A
B
C
D
E
F
s
e
E1
3 36 b
PIN #1 ID FIDUCIALLOCATED IN THIS AREA
5 (4X)
aaa
D
BE
A
4
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28 FPGA-DS-02053-6.3
23. 36-Ball WLCSP Package Option 2: MachXO2, MachXO3™ Dimensions in Millimeters
Cccc
bbb C
C 1A
A
REF. Min. Nom. Max.
0.5100.167
0.239
0.543
0.196
0.266
0.576
0.225
0.319
2.487 BSC
2.541 BSC
2.00 BSC
2.00 BSC
0.40 BSC
0.244
0.060
ALL DIMENSIONS AND TOLERANCE PER ASME Y 14.5M - 1994.
ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSION b IS MEASURES AT THE MAXIMUM BUMP DIAMETERPARALLEL TO PRIMARY DATUM
PRIMARY DATUM AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BUMPS.
NOTES:
3
4
1.
2.
- -
0.271- -
0.030
0.025
0.0150
0.050
SIDE VIEW
TOP VIEWBOTTOM VIEW
sD
e
D1
e
sEE1
6 5 4 3 2 1
A
B
C
D
E
F
3 36 b
ddd M C A B
eee C
PIN #1 ID FIDUCIALLOCATED IN THIS AREA A
D
aaa C2x
BE
aaa C
2x
4
C.
C.
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 29
24. 36-Ball WLCSP Package Option 3: CrossLink™ Dimensions in Millimeters
REF. Min. Nom. Max.
0.113
0.188 0.218
0.600
0.248
2.535 BSC
2.583 BSC
2.00 BSC
2.00 BSC
0.40 BSC
0.030
0.015
ALL DIMENSIONS AND TOLERANCE PER ASME Y 14.5M - 1994.
ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSION b IS MEASURES AT THE MAXIMUM BUMP DIAMETER
PARALLEL TO PRIMARY DATUM C.
PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BUMPS.
BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THEPACKAGE BODY.
NOTES:
3
4
1.
2.
0.050
0.0505
-
-
-
-
SIDE VIEW
TOP VIEWBOTTOM VIEW
e
D1
e
E1
3 36 b
dddeee
M
MC
C
A B
PIN #1 ID FIDUCIALLOCATED IN THIS AREA
5 (4X)
aaa
D
BE
A
A
A1C
Cccc
4
6 5 4 3 2 1
A
B
C
D
E
F
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
30 FPGA-DS-02053-6.3
25. 44-Pin JLCC Package Dimensions in Inches
CORNER CHAMFERS AND/OR NOTCHES ARE OPTIONAL.
DIMENSIONING AND TOLERANCING PER ANSI Y14.5M.
3.
.050
ALL DIMENSIONS ARE IN INCHES.
-A-
.004
PLANE
SEATING
2.
1.
E4
D4
DETAIL A
D
D1
D2
E2
SECTION B-B
N
R
Q
L2
L1
L
.020 MIN.
A1
LO
BM
Y
D4/E4
A
B1
C
B
A
D2/E2
D1/E1
D/E
C1
C
B2
B1
B
A1
S
-
-
-
-
-
-
-
-
-
44
.040.020
.003
.025
.020
.005
-
-
-
-
-
-
-
.500 BSC
.660.620
.690
.013.007
.065 REF
C1
WITHLEAD FINISH
BASE METAL
MAX.
.700
.010
.035
.020
.023
.630 BSC
.675
.007
.022
.013
.013
.115 .190
MIN.
INCHES
(N PLACES)
DETAIL AE1 E
M.011
B2
B
R
L2
L1
Q
A
L
C
B
B
NOTES:
BOTTOM VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 31
26. 44-Pin PLCC Package Dimensions in Inches
A-B //
.00 7 S H
.00 2 S
A-B S S D
.00 7 S A-B H S D S
A-B S .00 2
1 44
A-B .00 7 S H
.00 7 S H
S S D
D S A-B S
DIM ENSION APPLIES TO BASE META L ONLY
TOP POINT OF M EASUREMENT IS DA TUM
MEASUREMENT IS AT MA JOR FLAT AREA OF LOWER PLASTIC SURFACE
DEFINED BY D3/E3
ALLOWABLE PROTRUSION IS .010 PER SIDE.
8
7 ; BOTTOM POINT OF -H-
LOCATED AT TOP OF MOLD PARTING LINE AND
TO BE M EA SURED A T SEATING PL ANE
EXIT PLA STIC BODY AT DATUM PLANE
DIM ENSIONS D1 AND E1 DO NOT INCL UDE MOLD PROTRUSION.
COINCIDENT WITH TOP OF LEAD WHERE L EAD EXITS PLA STIC BODY
ALL DIM ENSIONS AND TOLERA NCES CONFORM TO ANSI Y14.5M-1982
DATUMS
DATUM PLANE
6
5
4 AND A-B -D-
-H-
NOTES:
CONTACT POINT
TO BE DETERMINED WHERE CENTER LEADS
-C-
-H-
7
7
7
E E1 -D-
E3 E3
6
4
D
D1 6
-B- 4
4 -D-
D3
D3
-A-
D/E
D2/E2 D2/E2
-H- 3
A1 A
-C-
SEATING PLANE
-A-B-
-A-B-
-D-
5 5
.004 C
A A
A2
.020 (MIN)
PIN 1 ID ZONE
DETAIL "J"
SECTION A-A
.021
.013
8
.0105
.0075
.018
.013
.0125
.0075
8
ALL DIM ENSIONS IN INCHES
H S .00 7 D S S A-B .032
.026
.00 7 M A-B C D S S
.021
.013
DETAIL "J" (TYP ALL SIDES)
SEATING PLANE .025 MIN.
.045 MIN.
3
1.
2.
-C-
NOM.
S
L
A
Y M
B
O MIN. .165 .172
MAX. .180
A1 .090 .120 .105
A2 .062 .083 -
D .685 .695 .690
D1 .650 .656 .653
D2 .291 .319 .305
D3 .225
E E1 E2 E3 .225
N 44
.291
.685
.650
.319 .305
.656
.695 .690
.653
0.050 (N-4PLACES)
BOTTOM VIEW TOP VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
32 FPGA-DS-02053-6.3
27. 44-Pin TQFP Package Dimensions in Millimeters
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 33
28. 44-Pin LQFP Package Dimensions in Millimeters
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34 FPGA-DS-02053-6.3
29. 48-Pin TQFP Package Dimensions in Millimeters
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 35
30. 48-Pin LQFP Package Dimensions in Millimeters
EXACT SHAPE O F EACH CORNER IS O PTIO NAL.
TO THE LOWEST POINT ON THE PACKAGE BODY.
7. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
BASE METAL
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
THESE DIMENSIONS APPLY TO THE FLAT SECTION O F THE
ALLOWABLE MOLD PR OTRUSION IS 0.254 MM ON D1 AND E1
DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MO LD PROTRUSION.
5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
8.
OF THE PACKAGE BY 0.15 MM.
DIMENSIONS.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
6. SECTION B-B:
3.
1b
0.220.17 72.0b
0.16
0.23
0.200.09c
c1 0.09
b1 0.17
0.15
0.13
0.20
MAX.
1.60
0.15
0.75
1.45
e
N
L 0.45
0.50 BSC
0.60
48
E1
E
D1
D
9.00 BSC
7.00 BSC
9.00 BSC
7.00 BSC
A2
A1
1.35
0.05
SYMBOL
A -
MIN.
1.40
-
NOM.
-
C A-B
SEE DETAIL "A"
LEAD FINISH
C SEATING PLANE
A3.
0.08
c
b
1c
M C
b
A -B D
3.D
4X8.
e
B 3.
E
D0.20
GAUGE PLANE
A10.08 C
A A2
1.00 REF.
L
0.20 MIN. 0-7
H
E1
0.25
0.20 DD A-BH D1
SECTION B - B
DETAIL "A"
NOTES:
PIN 1 INDICATO R
1
N
MA RKING
ORIENTATION
TOP VIEW
BOTTOM VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36 FPGA-DS-02053-6.3
31. 48-Pin QFN Package: L-ASC10, iCE40 Ultra, iCE40 UltraPlus, MachXO2
Dimensions in Millimeters
APPLIES TO EXPOSED PORTION OF TERMINALS.
DIMENSIONS AND TOLERANCES
EXACT SHAPE AND SIZE OF THIS
DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP.
NOTES: UNLESS OTHERWISE SPECIFIED
ALL DIMENSIONS ARE IN MILLIMETERS.2.
1.
FEATURE IS OPTIONAL.
PER ANSI Y14.5M.
SYMBOL
A
A1
A3
D
D2
E
E2
b
e
L
NOM. MAX.MIN.
0.00
5.20
0.15
0.90
0.02
5.35
0.225
1.00
0.05
5.50
0.30
0.35
0.80
0.2 REF
7.0 BSC
7.0 BSC
0.50 BSC
5.20 5.35
SIDE VIEW
WEIV MOTTOBWEIV POT
A D
N
2X0.15 C A
2X0.15 C B
1
3PIN 1 ID AREA
E
B
VIEW A
C
SEATINGPLANE
D2
L3
CHAMFER 0.30x4548X
N
1
0.2500
PIN #1 ID FIDUCIALLOCATED IN THIS AREA
E2
e
0.50 TYP4X
48Xb 0.10 M C A B
0.05 M C
4
VIEW AA
0.10 C
0.08 C 5
A1A3
3.
4.
5.
5.50
0.40 0.45
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 37
32. 49-Ball caBGA Package Dimensions in Millimeters
IDENTIFIERA1 BALL I.D.
TO EACH SIDE OF THE PACKAGE BODY.
DIMENSION "b" IS MEASURED AT THE
EXACT SHAPE AND SIZE OF THIS FEATURE
PLANE ARE DEFINED BY THE SPHERICAL
BILATERAL TOLERANCE ZONE IS APPLIED
ALL DIMENSIONS ARE IN MILLIMETERS.
C
b
PRIMARY DATUM C AND SEATING
CROWNS OF THE SOLDER BALLS.
IS OPTIONAL.6
5
4
.15
.08
MAXIMUM SOLDER BALL DIAMETER,PARALLEL TO PRIMARY DATUM C
DIMENSIONS AND TOLERANCES
NOTES: UNLESS OTHERWISE SPECIFIED
PER ANSI Y14.5M.
3
1.
2.
3AC
C
M
M
B
ddd4
e
S
N
S
e
M
0.52b 0.460.40
0.80 BSC
bbb
ddd
aaa
e
-
-
0.10
0.12
0.10-
-
-
7.00 BSC
4.80 BSC
0 BSC
NOM.
0.36
1.04
1.40
SYMBOL MIN.
M/N
D/E
A1
A2
S
A
0.31
0.99
1.30
C
Cbbb
MAX.
0.41
1.09
1.50
A 1
aaa
4X6
D
E
A 2A
A
B
(4X) 5
TOP VIEWBOTTOM VIEW
SIDE VIEW
-
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
38 FPGA-DS-02053-6.3
33. 49-Ball ucBGA Package Dimensions in Millimeters
C4 ddd
bbb C
C1A
A2A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
30.20 0.25 03.0b
0.40 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.10
0.10
NOM.
2.40 BSC
3.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
0.10
MAX.
1.00
0.90
- -
--
6
--
b
.05
.153
BMM
CC A
e
N
e
M
aaa
4X 6
D
E
B
A
5(4X)
PIN #1 ID FIDUCIAL
LOCATED IN THIS AREA
BOTTOM VIEWTOP VIEW
SIDE VIEW
0.10
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 39
34. 49-Ball WLCSP Package Dimensions in Millimeters
Cccc
bbb C
C 1A
A
Notes:1 ALL DIMENSIONS AND TOLERANCE PER ASME Y 14.5M - 1994.2 ALL DIMENSIONS ARE IN MILLIMETERS.
3 DIMENSION b IS MEASURED AT THE MAXIMUM BUMP DIAMETER PARALLEL TO PRIMARY DATUM C.
4 PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BUMPS.
AA1bDED1E1esDsEaaabbbcccdddeee
REF. Min. Nom. Max.
2.40 BSC2.40 BSC0.40 BSC
0.6000.2320.3193.1553.225
-0.1990.2663.1063.185
-0.1670.2393.0553.125
0.0300.0600.0500.0150.050
0.3530.388
0.3830.418
- -
TOP VIEW
BOTTOM VIEW
SIDE VIEW
7 6 5 4 3 2 1sD
e
A
B
C
D
E
F
G
D1
e
sEE1
3 49 X b
ddd M C A BCeee M
PIN #1 ID FIDUCIALLOCATED IN THIS AREA A
aaa C
2x
D
B
aaa C2x
E
4
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
40 FPGA-DS-02053-6.3
35. 56-Ball csBGA Package Dimensions in Millimeters
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS ME ASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM C
MAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.25 0.30 53.0b
0.50 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.08
0.10
1.23
NOM.
0.25 BSC
4.50 BSC
6.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
1.10
0.15
MAX.
1.35
1.10
--
--
C
4
ddd
bbb C
C
1A
A 2Ab
.05
.153
B
M
M
C
C A
e
S
N
S
e
M
A1 BALL I.D.
IDENTIFIER
aaa
4X6
D
E
B
A
5
(4X)BOTTOM VIEW
TOP VIEW
SIDE VIEW
0.10
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 41
36. 64-Ball csBGA Package Dimensions in Millimeters
C
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
b
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
.05
.15
2.
1.
3
3B
MM
CC A
4 ddd
e
S
N
S
e
M
0.25 0.30b
0.50 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.08
0.10
NOM.
0.25 BSC
3.50 BSC
5.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.90
0.15
bbb C
C
MAX.
1.10
0.85
1A
aaa
4X 6
D
E
A2A
B
A
5(4X)
- -
--
PIN #1 ID FIDUCIAL
LOCAT ED IN TH IS AREA
6
1.00
TOP VIEWBOTTOM VIEW
SIDE VIEW
0.10
0.35
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
42 FPGA-DS-02053-6.3
37. 64-Pin QFNS Package Dimensions in Millimeters
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 43
38. 64-Ball ucBGA Package Dimensions in Millimeters
C4 ddd
bbb C
C
1A
A 2A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.20 0.25 03.0b
0.40 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.08
0.10
NOM.
0.20 BSC
2.80 BSC
4.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.10
MAX.
1.00
0.90
- -
--
6
--
b
.05
.153
BMM
CC A
e
S
N
S
e
M
aaa
4X 6
D
E
B
A
5(4X)
PIN #1 ID FIDUCIAL LOCATED IN THIS AREA
BOTTOM VIEW TOP VIEW
SIDE VIEW
0.10
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
44 FPGA-DS-02053-6.3
39. 64-Ball ucfBGA Package Dimensions in Millimeters
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM C.MAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.25b
0.40 BSC
aaa
ccc
bbb
e
0.10
0.08
NOM.
0.20 BSC
2.80 BSC
3.50 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.11
MAX.
1.00
M A1 CORNERINDEX AREA
aaa
4X6
D
E
B
A
5(4X)
N
e
b
eeeddd
3B
MM
CC A
S
e
C
4
ccc
bbb C
CA
A2
A
1
-
0.20 0.30
0.62 -
eee
ddd
0.08
0.10
--
-
-
BOTTOM VIEW TOP VIEW
SIDE VIEW
0.15
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 45
40. 64-Pin LQFP Package Dimensions in Millimeters
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
46 FPGA-DS-02053-6.3
41. 68-Pin JLCC Package Dimensions in Inches
CORNER CHAMFERS AND/OR NOTCHES ARE OPTIONAL.
DIMENSIONING AND TOLERANCING PER ANSI Y14.5M.
3.
2.
1.
-A-
.00 4
PLANE
SEATING
ALL DIMENSIONS ARE IN INCHES.
.05 0
E4
D4
DETAIL A
D
D1
D2
E2
O
SECTION B-B
D4/E4D2/E2D1/E1
NRQL2L1L
.02 0 MIN.
A1
SY
MBA
B1
C
B
A
D/EC1CB2B1BA1
---
-----
68.040.020
.003
.025
.020
.005.930 BSC
-
-----
-
L
.800 BSC.960.920
.990
.013.007
.080 REF
C1
WI THLEAD FINISH
BASE METAL
MAX.
1.000.010
.035
.020
.023
.975
.007
.022
.013
.013
.115MIN.
INCHES
(N PLACES)
DETAIL A
E1 E
M.01 1
B2
B
R
L2
L1
A
Q
L
C
B
B
NOTES:
BOTTOM VIEW
SIDE VIEW
-
.190
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 47
42. 68-Pin PLCC Package Dimensions in Inches
A-B //
.007 S H
.002 S
A-B S S D
.007 S A-B H S D S
A-B S .002
1 68
A-B .007 S H
.007 S H
S S D
D S A-B S
DIMENSION A PPLIES TO BASE METAL ONLY
TOP POINT OF MEASUREMENT IS DATUM
MEASUREMENT IS AT MAJOR FLAT AREA OF LOWER PLASTIC SURFACE
DEFINED BY D3/E3
ALLOWABLE PROTRUSION IS .010 PER SIDE.
8
7 ; BOTTOM POINT OF -H-
LOCATED AT TOP OF MOLD PA RTING LINE AND
TO BE MEA SURED AT SEATING PLANE
EXIT PLASTIC BODY AT DATUM PLANE
DIMENSIONS D1 AND E1 DO NOT INCLUDE M OLD PROTRUSION.
COINCIDENT WITH TOP OF LEA D WHERE LEAD EXITS PLA STIC BODY
ALL DIMENSIONS A ND TOLERANCES CONFORM TO ANSI Y14.5M-1982
DA TUMS
DA TUM PLANE
6
5
4 AND A-B -D-
-H-
NOTES:
CONTACT POINT
TO BE DETERMINED WHERE CENTER LEADS
-C-
-H-
7
7
7
E E1 -D-
E3 E3
6
4
D
D1 6
-B- 4
4 -D-
D3
D3
-A-
D/E
D2/E2 D2/E2
-H- 3
A1 A
-C-
SEATING PLANE
-A-B-
-A-B-
-D-
5 5
.004 C
A A
A2
.020 (MIN)
PIN 1 ID ZONE
DETAIL "J"
SECTION A-A
.021
.013
8
.0105
.0075
.018
.013
.0125
.0075
8
ALL DIMENSIONS IN INCHES
H S .007 D S S A-B .032
.026
.007 M A-B C D S S
.021
.013
DETAIL "J" (TYP ALL SIDES)
SEATING PLANE .025 MIN.
.045 MIN.
3
1.
2.
-C-
E3 N 68
E1 E2
E D3 .375
MAX.
.120
.180
.995
.083
.958
.469 D1 D2
.950
.441
D A2 .062
.985
.455
.954
.990
-
MIN. A A1
.165
.090
L
M
B
O
.105
.172
NOM.
S
Y
.455 .441
.375
.950
.985 .990
.954
.469
.995
.958
0.050 (N-4PLACES)
BOTTOM VIEW TOP VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
48 FPGA-DS-02053-6.3
43. 72-Pin QFN Package Option 1: CrossLink™-NX Dimensions in Millimeters
SIDE VIEW
TOP VIEW
BOTTOM VIEW
A D0.10 C A
0.10 C B
0.10 C B
0.10 C A B
0.10 C 0.05 CA
A2A3A1
E
C
1
SEATINGPLANE
0.10 M C A BD2
0.4500
PIN1 ID0.20 R 1
72
18
19
0.4200+0.18
0.4200+0.18
E2
0.10 M C A B
36
37
Leb
0.10 M C A B
0.05 M C
54
55
NOTES: UNLESS OTHERWISE SPECIFIED
1. DIMESNIONS AND TOLERANCES PER ANSI Y14.5M. 2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.
4. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP.
5. APPLIES TO EXPOSED PORTION OF TERMINALS.
SYMBOL MIN. NOM. MAX.
A
A1
A3
D
D2
E
E2
b
e
L
0.00
6.05
6.05
0.20
0.50 BSC
0.30
0.01
0.2 REF
10.0
6.20
10.0
6.20
0.25
0.40
0.90
0.05
6.35
6.35
0.30
0.50
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 49
44. 72-Pin QFN Package Option 2: MachXO3D Dimensions in Millimeters
A D
D1
aaa C A
aaa C B
E1 E
bbb C B
bbb C AB
ccc CA
eee C
A3
A1
1
SEATINGPLANEC
SIDE VIEW
TOP VIEW
0.4500
PIN1 ID0.20 R
D2fff M C A B
1
72
18
19
0.4200+0.18
0.4200+0.18
R
E2
1.0110
1.011055
L54
36
37b e L
fffM
CA
Bbbb M C A B
ddd M C
BOTTOM VIEW
NOTES: UNLESS OTHERWISE SPECIFIED
1. DIMENSIONS AND TOLERANCES PER ANSI Y14.5M.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.4. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP.
5. APPLIES TO EXPOSED PORTION OF TERMINALS.
SYMBOL MIN. NOM. MAX.
A
A1
A3
D
D2
E
E2
b
e
L
TOLERANCES OF FORM & POSITION
aaa
bbb
ccc
ddd
eee
fff
ggg
0.100
0.100
0.100
0.050
0.050
0.100
0.200
0.00
7.078
7.07
0.20
0.30
0.01
0.2 REF
10.0
7.178
10.0
7.178
0.25
0.50 BSC
0.40
0.90
0.05
7.278
7.278
0.30
0.50
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
50 FPGA-DS-02053-6.3
45. 72-Pin WLCSP Package: CrossLink-NX Dimensions in Millimeters
BOTTOM VIEWBOTTOM VIEW TOP VIEWTOP VIEW
SIDE VIEWSIDE VIEW
CCcccccc
bbbbbb CC
CC11AA
AA
9 8 7 6 5 4 3 2 1sD
e
A
B
C
D
E
F
G
H
D1
3 72 X b
ddd M C A Beee M C
e
sEE1
PIN #1 ID FIDUCIALLOCATED IN THIS AREA A
aaa C
2x
D
BE
aaa C2x
NOTES:
1. ALL DIMENSIONS AND TOLERANCE PER ASME Y 14.5M – 1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM BUMP DIAMETER PARALLEL TO PRIMARY DATUM C.
4. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BUMPS.
REF. Min. Nom. Max.A
A1b
D
ED1E1e
sD
sE
aaa
bbb
ccc
dddeee
0.164
0.239
3.8074 BSC4.1251 BSC
2.800 BSC3.200 BSC
0.40 BSC
0.485
0.445
0.030.060
0.03
0.015
0.050
0.1940.269
0.608
0.224
0.299
0.515
0.475
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 51
46. 80-Ball ctfBGA Package Dimensions in Millimeters
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM C.MAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.25b
0.65 BSC
aaa
ccc
bbb
e
0.10
0.08
NOM.
0.325 BSC
5.85 BSC
6.50 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.11
MAX.
1.00
M A1 CORNERINDEX AREA
aaa
4X 6
D
E
B
A
5
(4X)
N
e
b
eeeddd
3B
MM
CC A
S
e
C
4
ccc
bbb C
CA
A2 A
1
-
0.20 0.30
0.61 -
eee
ddd 0.15
0.05
0.10
--
-
-
BOTTOM VIEW TOP VIEW
SIDE VIEW
109
87
65
43
21
A
B
C
D
E
F
G
H
J
K
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
52 FPGA-DS-02053-6.3
47. 80-Ball ckfBGA Package Dimensions in Millimeters
B
BOTTOM VIEW TOP VIEW
SIDE VIEW
1 2 3 4 5 6 7 8 9 10
K
J
H
G
F
E
D
C
B
A
e
D D1
A
aaa (4X) C
e
E1
E
b n X
eee M C A B
fff M C
PIN A1 CORNER
M
cccC D
dd
dC
SC A1 A
SymbolCommon Dimensions
MIN. NOM. MAX.
Package: MFC TFBGA
Body Size:XY
ED
7.0007.000
Ball Pitch: e 0.650
Total Thickness: A 0.962 1.082 1.200
Mold Thickness: M 0.490 0.530 0.570
Substrate Thickness: S 0.252 0.282 0.312
Ball Diameter: 0.350
Stand Off: A1 0.220 0.270 0.320
Ball Width: b 0.320 0.370 0.420
Package Edge Tolerance: aaa 0.100
Mold Parallelism: ccc 0.100
Coplanarity: ddd 0.080
Ball Offset (Package): eee 0.150
Ball Offset (Ball): fff 0.050
Ball Count: n 80
Edge Ball Center to Center: XY
E1D1
5.8505.850
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 53
48. 81-Ball csBGA Package Dimensions in Millimeters
C4 ddd
bbb C
C
1A
A2
A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
30.20 0.25 03.0b
0.50 BSC
aaa
ddd
bbb
e
-
-
-
-
-
- 0.10
0.10
0.10
NOM.
4.00 BSC
5.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
0.10
MAX.
1.00
0.90
----
6
--
b
.05
.153
BMM
CC A
e
N
e
M
aaa
4X 6
D
E
B
A
5(4X)
PIN #1 ID FIDUCIAL
LOCATED IN THIS AREA
BOTTOM VIEW TOP VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
54 FPGA-DS-02053-6.3
49. 81-Ball csfBGA Package Dimensions in Millimeters
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM C.MAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.25b
0.50 BSC
aaa
ccc
bbb
e
0.10
0.08
NOM.
0.00 BSC
4.00 BSC
4.50 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.11
MAX.
1.00
M A1 CORNERINDEX AREA aaa
4X6
D
E
B
A
5
(4X)
N
e
b
eeeddd
3B
MM
CC A
S
e
C
4
ccc
bbb C
CA
A2A
1
-
0.20 0.30
0.64 -
eee
ddd 0.15
0.08
0.10
--
-
-
98
76
54
3
21
A
B
C
D
E
F
G
H
J
BOTTOM VIEW TOP VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 55
50. 81-Ball ucBGA Package Dimensions in Millimeters
C4 ddd
bbb C
C
1A
A 2A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
30.20 0.25 03.0b
0.40 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.10
0.10
NOM.
3.20 BSC
4.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
0.10
MAX.
1.00
0.90
- -
--
6
--
b
.05
.153
BMM
CC A
e
N
e
M
aaa
4X 6
D
E
B
A
5(4X)
PIN #1 ID FIDUCIAL LOCATED IN THIS AREA
BOTTOM VIEW TOP VIEW
SIDE VIEW
0.10
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
56 FPGA-DS-02053-6.3
51. 81-Ball WLCSP Package Dimensions in Millimeters
Cccc
bbb C
C 1A
A
Notes:1 ALL DIMENSIONS AND TOLERANCE PER ASME Y 14.5M - 1994.2 ALL DIMENSIONS ARE IN MILLIMETERS.3 DIMENSION b IS MEASURED AT THE MAXIMUM BUMP DIAMETER PARALLEL TO PRIMARY DATUM C.4 PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BUMPS.
AA1bDED1E1esDsEaaabbbcccdddeee
REF. Min. Nom. Max.
3.20 BSC3.20 BSC0.40 BSC
0.5670.2250.319
0.5430.1960.266
3.797 BSC3.693 BSC
0.5100.1670.239
0.0250.0600.0300.0150.050
--
--
0.2990.247
BOTTOM VIEWTOP VIEW
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
b
sDe
D1
e
sEE1
3 81 X
ddd M C A B
eee M C
PIN #1 ID FIDUCIALLOCATED IN THIS AREA
A
aaa C2x
D
B
Eaaa C
2x
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 57
52. 84-Pin CPGA Package Dimensions in Inches
NOT TO EXCEED .003 INCHES MAXIMUM PER SIDE.
.006 INCHES MAXIMUM ABOVE THE DIMENSION SHOWN
DIMENSIONS D AND E MAY HAVE MATERIAL PROTRUSION OF 3.
DIMENSIONING AND TOLERANCING PER ANSI Y14.5M.
.080 MAX.
SECTION X-X
ALL DIMENSIONS ARE IN INCHES.
NOTES:
2.
1.
BASE METAL
.020
.016.0215
.0165
3
.100
.100
1.180
1.140
D
E1.180
1.140
-B-
3
-A-
.145
.045
SEATING PLANE-C-
.200
.100
.075
X
X
.10
.30
.008
.070
M
M
M A
C
C MB
BOTTOM VIEWSIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
58 FPGA-DS-02053-6.3
53. 84-Pin PLCC Package Dimensions in Inches
A-B //
.00 7 S H
.00 2 S
A-B S S D
.00 7 S A-B H S D S
A-B S .00 2
1 84
A-B .00 7 S H
.00 7 S H
S S D
D S A-B S
DIM ENSION APPLIES TO BASE META L ONLY
TOP POINT OF M EASUREMENT IS DA TUM
MEASUREMENT IS AT MA JOR FLAT AREA OF LOWER PLASTIC SURFACE
DEFINED BY D3/E3
ALLOWABLE PROTRUSION IS .010 PER SIDE.
8
7 ; BOTTOM POINT OF -H-
LOCATED AT TOP OF MOLD PARTING LINE AND
TO BE M EA SURED A T SEATING PL ANE
EXIT PLA STIC BODY AT DATUM PLANE
DIM ENSIONS D1 AND E1 DO NOT INCL UDE MOLD PROTRUSION.
COINCIDENT WITH TOP OF LEAD WHERE L EAD EXITS PLA STIC BODY
ALL DIM ENSIONS AND TOLERA NCES CONFORM TO ANSI Y14.5M-1982
DATUMS
DATUM PLANE
6
5
4 AND A-B -D-
-H-
NOTES:
CONTACT POINT
TO BE DETERMINED WHERE CENTER LEADS
-C-
-H-
7
7
7
E E1 -D-
E3 E3
6
4
D
D1 6
-B- 4
4 -D-
D3
D3
-A-
D/E
D2/E2 D2/E2
-H- 3
A1 A
-C-
SEATING PLANE
-A-B-
-A-B-
-D-
5 5
.004 C
A A
A2
.020 (MIN)
PIN 1 ID ZONE
DETAIL "J"
SECTION A-A
.021
.013
8
.0105
.0075
.018
.013
.0125
.0075
8
ALL DIM ENSIONS IN INCHES
H S .00 7 D S S A-B .032
.026
.00 7 M A-B C D S S
.021
.013
DETAIL "J" (TYP ALL SIDES)
SEATING PLANE .025 MIN.
.045 MIN.
3
1.
2.
-C-
E3 N 84
E1 E2
D3 E
.475
.180
MAX.
.080
1.158
1.195
.120
.569 D1 D2
1.150
.541
A2 D
.059
1.185
1.154
.555
1.190
-
MIN. A A1
.165
.090
M
B
O
L
.172
.105
NOM.
Y
S
.541
1.150
.475
.555
1.154
1.185 1.190
.569
1.158
1.195
0.050 (N-4PLACES)
BOTTOM VIEWTOP VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 59
54. 84-Pin QFN Package Dimensions in Millimeters
APPLIES TO EXPOSED PORTION OF TERMINALS.
DIMENSIONS AND TOLERANCES
EXACT SHAPE AND SIZE OF THIS
DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP.
NOTES: UNLESS OTHERWISE SPECIFIED
ALL DIMENSIONS ARE IN MILLIMETERS.2.
1.
FEATURE IS OPTIONAL.
PER ANSI Y14.5M.
SYMBOL
A
A1
A3
D
D2
E
E2
b
e
f
NOM. MAX.MIN.
0.00
4.30
0.17
0.85
0.02
-
0.22
0.95
0.05
4.50
0.27
0.75
0.15 REF
7.0 BSC
7.0 BSC
0.50 BSC
-
g
S
L
M 0.30 0.40 0.50
0.50 BSC
0.65 BSC
0.25 BSC
0.30 0.40 0.50
0.15
PIN 1 ID
3
DA
2X
B
L
0.15
2X
C
E2
A1
AC
eb0.10 4M B
PIN #1 ID FIDUCIAL LOCATED IN THIS AREA
N
1
E
5
4
3
3
SEATINGPLANE
C
0.08 5C
A3A1
A
B1
A12
B9
B10
A13
B18
A24
B19
A25
B27
A36
A37
B28
A48
B36
f
D2
M
S
g
0.10 CM B
0.10 M B
0.05 C
0.10 M B
84X
84X
TOP VIEW
BOTTOM VIEW
VIEW B
VIEW A
SIDE VIEW
VIEW B
VIEW A
B
A
C A
C A
C A
4.30 4.50
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
60 FPGA-DS-02053-6.3
55. 100-Ball caBGA Package Dimensions in Millimeters
MIN.SYMBOL MAX.NOM.
CROWNS OF THE SOLDER BALLS.
BILATERAL TOLERANCE ZONE IS APPLIED
EXACT SHAPE AND SIZE OF THIS FEATURE
TO EACH SIDE OF THE PACKAGE BODY.
IS OPTIONAL.
ALL DIMENSIONS ARE IN MILLIMETERS.
PARALLEL TO PRIMARY DATUM C
MAXIMUM SOLDER BALL DIAMETER,
DIMENSION "b" IS MEASURED AT THE
DIMENSIONS AND TOLERANCES
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
PLANE ARE DEFINED BY THE SPHERICAL
PRIMARY DATUM C AND SEATING
6
5
4
3
1.
2.
bbb
ddd
-
-
0.10
0.12
-
-
7.20 BSC
10.00 BSC
0.46
0.80 BSC
0.40 BSC
0.36
1.04
1.40
M/N
b
aaa
e
S
0.40
-
D/E
A1
A2
A
0.31
0.99
1.30
0.52
0.10-
0.41
1.09
1.50
b
3
e
S
10
A1 BALL I.D.
4X
.08
.15C
C
M
M
S
A B
Cddd
4 C
e
Cbbb
59 8 7 16 2
NE
K
J
H
G
F
IDENTIFIER
B
D
C
A
6
A
1A
A 2
E
B
M
aaa(4X)
D
5
A
TOP VIEWBOTTOM VIEW
SIDE VIEW
4 3
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 61
56. 100-Ball csBGA Package Dimensions in Millimeters
C
4
ddd
bbb C
C1A
A 2A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.25 0.30b
0.50 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.08
0.10
1.23
NOM.
0.25 BSC
6.50 BSC
8.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.90
0.15
MAX.
1.35
1.10
- -
--
A1 BALL I.D.IDENTIFIER
aaa
4X6
D
E
B
A
5(4X)
b
.05
.153
BMM
CC A
e
S
N
S
e
M
BOTTOM VIEW TOP VIEW
SIDE VIEW
0.35
0.10
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
62 FPGA-DS-02053-6.3
57. 100-Ball fpBGA Package Dimensions in Millimeters
bbb
PLANE ARE DEFINED BY THE SPHERICAL
DIMENSION "b" IS MEASURED AT THE
ALL DIMENSIONS ARE IN MILLIMETERS.
TO EACH SIDE OF THE PACKAGE BODY.
EXACT SHAPE AND SIZE OF THIS FEATURE
BILATERAL TOLERANCE ZONE IS APPLIED
IDENTIFIER
A1 BALL I.D.
2.
1.
3
4
NOTES: UNLESS OTHERWISE SPECIFIED
5
6 IS OPTIONAL.
PRIMARY DATUM C AND SEATING
PER ANSI Y14.5M.
DIMENSIONS AND TOLERANCES
MAXIMUM SOLDER BALL DIAMETER,
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
4
ddd C
S
e
A
b
3.25
.10 M
M
C
C
10 9 8 7 6 5
M
B
S
e
J
K
H
G
4 3 2 1
D
E
F
C
B
N
A
0.70
1.70
MAX.
0.20
0.20
0.25
0.70
D/E
e
aaa
ddd
bbb
S
M/N
b
C
A
A2
A1
SYMBOL
11.00 BSC
0.50 BSC
1.00 BSC
9.00 BSC
-
-
-
0.40
-
-
-
0.55
1.10 REF
1.501.30
0.30
MIN. NOM.
0.50
2
5(4X)
4X
C
6
aaa
A A
1A
D A
E
B
BOTTOM VIEWTOP VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 63
58. 100-Pin PQFP Package Dimensions in Millimeters
0.13/0.30 R.
23.20 BSC
17.20 BSC
20.00 BSC
ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1
TO THE LOWEST POINT ON TH E PACKAGE BODY.
5. 0 THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TI P.
7. 0 A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
EXACT SHAPE OF EXPOSED HEATSINK IS OPTIONAL.
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
OF THE PACKAG E BY 0.15 MM.
8.
9.
6. 0 SECTION B-B:
DIMENSIONS.
c
c1
b
b1
0.11
0.11
0.22
0.22
-
-
0.30
N
e
E
E1
L
0.65 BSC
100
14.00 BSC
0.73 0.88
BASE METAL
LEAD FINIS H
DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
4. 0 DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
1. 0 DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
c1c
2. 0 ALL D IMENSIONS ARE IN MILLIMETERS.
3.
1b
b
A
D1
D
A1
A2
-
0.25
2.50
-
-
2.70
SYMBOL MIN. NOM.
1.60 REF.
L
R. MIN.0.13
0.40 MIN.
0° MIN.
0.23
0.19
0.40
0.36
1.03
3.40
0.50
2.90
MAX.
GAGE PLANE
0-7°
0.25
NOTES:
PLANE
-C-
SEATING
bM0.12 C A-B D
SEE DETAIL "A"
(N-4)X e
C0.10
A
A1
-H-
A2
-D-
83 -B-
PIN 1 INDICATOR
3N
1
E
-A-
D D1
3
C X4B-A D52.0
E1
H X4B-A D02.0
SECTION B - B
DETAIL "A"
TOP VIEW
BOTTOM VIEW
0.15
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
64 FPGA-DS-02053-6.3
59. 100-Pin LQFP Package Option 1: MachXO2, MachXO™, ispMACH® 4000
Dimensions in Millimeters
LEAD FINISH
BASE METAL
5. THE TOP OF PACKAG E MAY BE SMALLER THAN THE BOTTOM
4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1
2. ALL DIMENSIONS ARE IN MILLIMETERS.
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
THESE DIMENSIONS APPLY TO TH E FLAT SECTION OF THE
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
7. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
TO THE LOWEST POINT ON THE PACKAGE BODY.
EXACT SHAPE OF EACH CORNER IS OPTI ONAL.8.
DIMENSIONS.
OF THE PACKAGE BY 0.15 MM.
6. SECTION B-B:
3.
SECTION B-B
b1
c
b
c 1
0.160.130.09c1
0.50 BSC
0.17
0.09c
b1
0.17b
e
0.15
0.20
0.20
0.23
0.22 0.27
14.00 BSC
16.00 BSC
0.45
N
L
E1
E
100
0.60 0.75
14.00 BSC
16.00 BSC
D1
D
0.05
1.35A2
A1
1.40
-
1.45
0.15
SYMBOL
DETAIL 'A'
A1
0.10 C
MIN.
A -
NOM.
1.60
MAX.
0.20 MIN.
1.00 REF.
0-7
L
SIDE VIEW
SEATING PLANE0.20 CM B-A D
b
TOP VIEW
8
e
D
A
3
D
GAUGE PLANE
SEE DETAIL 'A'
C
A A2
0.204X A-BH D
H
0.25
BOTTOM VIEW
3
3
B
E1E
D1
0.20 C B-A D 100X
N
1
NOTES:
PIN 1 INDICATOR
MARKINGORIENTATION
-
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 65
60. 100-Pin VQFP Package Option 2: iCE40 Dimensions in Millimeters
NOTES:
PIN 1 INDICATOR
MARKINGORIENTATION
LEAD FINISH
BASE METAL
5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1
2. ALL DIMENSIONS ARE IN MILLIMETERS.
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
7. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
TO THE LOWEST POINT ON THE PACKAGE BODY.
EXACT SHAPE OF EACH CORNER IS OPTIONAL.8.
DIMENSIONS.
OF THE PACKAGE BY 0.15 MM.
6. SECTIO N B-B:
3.
SECTION B-B
b1
c
b
c 1
0.160.130.09c1
0.50 BSC
0.17
0.09c
b1
0.17b
e
0.15
0.20
0.20
0.23
0.22 0.27
14.00 BSC
16.00 BSC
0.45
N
L
E1
E
100
0.60 0.75
14.00 BSC
16.00 BSC
D1
D
0.05
0.95A2
A1
1.00
-
1.05
0.15
SYMBOL
DETAIL 'A'
A10.08 C
MIN.
A - -
NOM.
1.20
MAX.
0.20 MIN.
1.00 REF.
0-7°
L
SIDE VIEW
SEATING PLANE0.20 CM DA-B
b
TOP VIEW
8
e
D
A
3
D
GAUGE PLANE
SEE DETAIL 'A'
C
A A2
0.204X A-BH D
H0.25
BOTTOM VIEW
3
3
B
E1E
D1
0.20 A-BC D 100X
N
1
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
66 FPGA-DS-02053-6.3
61. 120-Pin PQFP Package Dimensions in Millimeters
0° MIN.
0.20 MIN.
-
NOM.
-
3.40
31.20 BSC
0.88
31.20 BSC
28.00 BSC
28.00 BSC
120
0.80 BSC
-
0.35
0.15
-
3. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
TO THE LOWEST POINT ON THE PACKAGE BODY.
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
4. 0 DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1
5. 0 THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
THESE DIMENSI ONS APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
7. 0 A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
EXACT SHAPE OF EXPOSED HEATSINK IS OPTIONAL.9.
6. 0 SECTION B-B:
8.
DIMENSIONS.
OF THE PACKAGE BY 0.15 MM.
c1
N
e
b
b1
c
0.29
0.29
E
E1
L
D1
0.73
2. 0 ALL DIMENSIONS ARE IN MILLI METERS.
1. 0 DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
c
BASE METAL1b
c1
A
SYMBOL
A1
A2
D
0.25
3.20
-
MIN.
L
1.60 REF.
LEAD FINISHb
R. MIN.0.13
0.19
0.41
0.23
0.45
1.03
0-7°
0.50
3.60
4.10
MAX.
GAGE PLANE
0.25
0.13/0.30 R.
SECTION B - B
DETAIL "A"
TOP VIEW
BOTTOM VIEW
SEE DETAIL "A"
(N-4)X
NOTES:
0.20 M C DA-B
PLANE
C
SEATING
b
0.10
e
CA1
A A2
H
D
8
A3
1
N
PIN 1 INDICATOR
3
D 3
B
E E1
0.25 C 4X
D1
A-BH0.20 D 4X
DA-B
0.11
0.11
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 67
62. 121-Ball caBGA Package (9 mm x 9 mm Body) Dimensions in Millimeters
BOTTOM VIEW TOP VIEW
SIDE VIEW
D
M
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
N E
S
e
S
eb
3 .15 M C A B
.08 M C
5
aaa
D
(4X)
A
BA1 CORNER INDEX AREA
E
64X
A A2
bbb C
ddd C
C
4
SYMBOL MIN. NOM. MAX.
A
A1
A2
D/E
M/N
S
b
e
aaa
bbb
ddd
0.15
0.55
1.10
9.00 BSC
8.00 BSC
0.00 BSC
0.30 0.40 0.50
0.80 BSC
0.15
0.20
0.10
NOTES: UNLESS OTHERWISE SPECIFIED
1. DIMENSIONS AND TOLERANCES PER ANSI Y14. 5M.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C.
4. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
5. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY.
6. EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
68 FPGA-DS-02053-6.3
63. 121-Ball csBGA Package Dimensions in Millimeters
C4 ddd
bbb C
C
1A
A2
A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
30.20 0.25b
0.50 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.10
0.10
NOM.
5.00 BSC
6.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
0.10
MAX.
1.00
0.90
-
--
6
--
b
.05
.153
BMM
CC A
e
N
e
M
aaa
4X 6
D
E
B
A
5(4X)
PIN #1 ID FIDUCIAL LOCATED IN THIS AREA
BOTTOM VIEW TOP VIEW
SIDE VIEW
0.10
0.30
-
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 69
64. 121-Ball csfBGA Package Dimensions in Millimeters
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
70 FPGA-DS-02053-6.3
65. 121-Ball ucBGA Package Dimensions in Millimeters
C4 ddd
bbb C
C
1A
A2
A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
30.20 0.25b
0.40 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.10
0.10
NOM.
4.00 BSC
5.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
0.10
MAX.
1.00
0.90
- -
--
6
--
b
.05
.153
BMM
CC A
e
N
e
M
aaa
4X 6
D
E
B
A
5(4X)
PIN #1 ID FIDUCIAL
LOCATED IN THIS AREA
BOTTOM VIEW TOP VIEW
SIDE VIEW
0.10
0.30
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 71
66. 128-Pin PQFP Package Dimensions in Millimeters
0° MIN.
0.20 MIN.
-
NOM.
-
3.40
31.20 BSC
0.88
31.20 BSC
28.00 BSC
28.00 BSC
128
0.80 BSC
-
0.35
0.15
-
3. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
TO THE LOWEST POINT ON THE PACKAGE BODY.
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
4. 0 DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1
5. 0 THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
THESE DIMENSI ONS APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
7. 0 A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
EXACT SHAPE OF EXPOSED HEATSINK IS OPTIONAL.9.
6. 0 SECTION B-B:
8.
DIMENSIONS.
OF THE PACKAGE BY 0.15 MM.
c1
N
e
b
b1
c
0.29
0.29
E
E1
L
D1
0.73
2. 0 ALL DIMENSIONS ARE IN MILLI METERS.
1. 0 DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
c
BASE METAL1b
c1
A
SYMBOL
A1
A2
D
0.25
3.20
-
MIN.
L
1.60 REF.
LEAD FINISHb
R. MIN.0.13
0.19
0.41
0.23
0.45
1.03
0-7°
0.50
3.60
4.10
MAX.
GAGE PLANE
0.25
0.13/0.30 R.
SECTION B - B
DETAIL "A"
TOP VIEW
BOTTOM VIEW
SEE DETAIL "A"
(N-4)X
NOTES:
0.20 M C DA-B
PLANE
C
SEATING
b
0.10
e
CA1
A A2
H
D
8
A3
1
N
PIN 1 INDICATOR
3
D 3
B
E E1
0.25 C A-B D 4X
D1
A-BH0.20 D 4x
0.11
0.11
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
72 FPGA-DS-02053-6.3
67. 128-Pin LQFP Package Dimensions in Millimeters
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
TO THE LOWEST POINT ON THE PACKAGE BODY.
7. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
BASE METAL
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE
ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1
DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
8.
OF THE PACKAGE BY 0.15 MM.
DIMENSIONS.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
6. SECTION B-B:
3.
1b
c c 1
c1
c
0.09
0.09
b1
b
0.13
0.13
0.13
0.15
0.16
0.20
0.16
0.18
0.19
0.23
16.00 BSCE
0.45L
N
e
E1
0.60 0.75
0.40 BSC
128
14.00 BSC
D1
D
A2
A1
1.35
0.05
16.00 BSC
14.00 BSC
1.40
-
1.45
0.15
SYMBOL
A -
MIN.
-
NOM.
1.60
MAX.
SEE DETAIL "A"
LEAD FINISH
C SEATING PLANE
8.
b
0.07
b
-BCM A D
4X
D 3.
e
3. A
B
D
GAUGE PLANE
0.08 C
A1
A A2
1.00 REF.
0.20 MIN.
L
0-7
H
0.25
E
3.
E1
A-BC A-B0.20
H0.20 DD
D1
SECTION B - B
DETAIL "A"
NOTES:
PIN 1 INDICATOR
1
N
MARKING ORIENTATION
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 73
68. 132-Ball csBGA Package Option 1: MachXO2, MachXO, LatticeXP2™
Dimensions in Millimeters
PRIMARY DATUM C AND SEATING
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM C
MAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.25 0.30b
0.50 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.08
0.10
1.23
NOM.
0.25 BSC
6.50 BSC
8.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.90
0.15
MAX.
1.35
1.10
- -
--
C
4
ddd
bbb C
C
1A
A 2Ab
.05
.153
B
M
M
C
C A
e
S
N
S
e
M
A1 BALL I.D.IDENTIFIER
aaa
4X6
D
E
B
A
5(4X)
BOTTOM VIEWTOP VIEW
SIDE VIEW
0.10
0.35
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
74 FPGA-DS-02053-6.3
69. 132-Ball csBGA Package Option 2: iCE40 Dimensions in Millimeters
C
4
ddd
bbb C
C1A
A 2A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.25 0.30b
0.50 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.08
0.10
-
NOM.
0.25 BSC
6.50 BSC
8.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
-
0.15
MAX.
1.00
0.85
- -
--
A1 BALL I.D.IDENTIFIER
aaa
4X6
D
E
B
A
5(4X)
b
.08.15
3B
MM
CC A
e
S
N
S
e
M
BOTTOM VIEW TOP VIEW
SIDE VIEW
0.10
0.35
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 75
70. 132-Ball ucBGA Package Dimensions in Millimeters
C
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
b
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
.05
.15
2.
1.
3
3B
MM
CC A
4 ddd
e
S
N
S
e
M
0.20 0.25b
0.40 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.08
0.10
NOM.
0.20 BSC
4.40 BSC
6.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.10
bbb C
C
MAX.
1.00
0.90
1A
aaa
4X 6
D
E
A 2A
B
A
5(4X)
- -
--
PIN #1 ID FIDUCIAL
LOCATED IN THIS AREA
6
--
BOTTOM VIEWTOP VIEW
SIDE VIEW
0.30
0.10
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
76 FPGA-DS-02053-6.3
71. 133-Pin CPGA Package Dimensions in Inches
ALL DIMENSIONS ARE IN INCHES.2.
NOT TO EXCEED .003 INCHES MAXIMUM PER SIDE.
.006 INCHES MAXIMUM ABOVE THE DIMENSION SHOWNDIMENSIONS D AND E MAY HAVE MATERIAL PROTRUSION OF
3.
DIMENSIONING AND TOLERANCING PER ANSI Y14.5M.
D -A-
-B-.050
BASE METAL
SECTION X-X
NOTES:
1.
.100
.016
.020
.0165
.0215
.080 MAX.
.100
.050
1.440
1.480
1.480
1.440E 3
3
.070
.100
SEATING PLANE
-C-
.045
.075
.200
X
X
.008
A
.10
.30M
M
C
C MB
.145BOTTOM VIEWSIDE VIEW
M
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 77
72. 144-Ball csBGA Package Dimensions in Millimeters
C
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
b
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
.05
.15
2.
1.
3
3B
MM
CC A
4 ddd
e
S N
S
e
M
0.25 0.30b
0.50 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.08
0.10
1.00
NOM.
0.25 BSC
5.50 BSC
7.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.90
0.15
bbb C
C
MAX.
1.10
0.85
1A
aaa
4X 6
D
E
A 2A
B
A
5(4X)
- -
--
PIN #1 ID FIDUCIAL
LOCATED IN T HIS AREA
6TOP VIEWBOTTOM VIEW
SIDE VIEW
0.10
0.35
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
78 FPGA-DS-02053-6.3
73. 144-Ball fpBGA Package Dimensions in Millimeters
A
E
0.50
1.70
0.60
0.50 BSC
1.00 BSC
11.00 BSC
11.60
13.00 BSC
0.50
NOM.
11.00B/C
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICALPRIMARY DATUM C AND SEATING
EXACT SHAPE AND SIZE OF THIS FEATURE
MAXIMUM SOLDER BALL DIAMETER,DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
IS OPTIONAL.6
5
4
3
ddd
ccc
bbb
aaa
e
b
S
M/N
D/E
-
-
-
-
-
-
-
-
0.50
C
DIMENSIONS AND TOLERANCES
ALL DIMENSIONS ARE IN MILLIMETERS.
NOTES: UNLESS OTHERWISE SPECIFIED
PER ANSI Y14.5M.1.
2.
ddd
4 C
C
bbb
.10
.253
b
e
S
A
M
M
C
C B
S
e
GN
K
J
H
M
L
E
D
C
B
F
Cccc
A2
A1
A
SYMBOL
0.30
1.30
0.30
MIN.
4X6
A2
1
AA
C
12.20
0.25
0.35
0.20
0.20
0.70
0.70
0.70
2.10
MAX.
B
A1 CORNER
INDEX AREA
101112 1
M
9 678 345 2
aaa
(4X)
B
D A
5
BOTTOM VIEW
TOP VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 79
74. 144-Pin LQFP Package Dimensions in Millimeters
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
TO THE LOWEST POINT ON THE PACKAGE BODY.
7. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
BASE METAL
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE
ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1
DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
8.
OF THE PACKAGE BY 0.15 MM.
DIMENSIONS.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
6. SECTION B-B:
3.
1b
c c 1
c1
c
0.09
0.09
b1
b
0.17
0.17
0.13
0.15
0.16
0.20
0.20
0.22
0.23
0.27
22.00 BSCE
0.45L
N
e
E1
0.60 0.75
0.50 BSC
144
20.00 BSC
D1
D
A2
A1
1.35
0.05
22.00 BSC
20.00 BSC
1.40
-
1.45
0.15
SYMBOL
A -
MIN.
-
NOM.
1.60
MAX.
SEE DETAIL "A"
LEAD FINISH
C SEATING PLANE
8.
b
0.08
b
-BCM A D
4X
D 3.
e
3. A
B
D
GAUGE PLANE
0.08 C
A1
A2A
1.00 REF.
0.20 MIN.
L
0-7
H
0.25
E
3.
E1
A-BC A-B0.20
H0.20 DD
D1
SECTION B - B
DETAIL "A"
NOTES:
PIN 1 INDICATOR
1
N
MARKINGORIENTATION
TOP VIEW BOTTOM VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
80 FPGA-DS-02053-6.3
75. 160-Pin PQFP Package Dimensions in Millimeters
0° MIN.
0.20 MIN.
-
NOM.
-
3.40
31.20 BSC
0.88
31.20 BSC
28.00 BSC
28.00 BSC
160
0.65 BSC
-
0.30
0.15
-
3. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
TO THE LOWEST POINT ON THE PACKAGE BODY .
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
4. 0 DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1
5. 0 THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
THESE DIMENSI ONS APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
7. 0 A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
EXACT SHAPE OF EXPOSED HEATSINK IS OPTIONAL.9.
6. 0 SECTION B-B:
8.
DIMENSIONS.
OF THE PACKAGE BY 0.15 MM.
c1
N
e
b
b1
c
0.22
0.22
E
E1
L
D1
0.73
2. 0 ALL DIMENSIONS ARE IN MILLI METERS.
1. 0 DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
c
BASE METAL1b
c1
A
SYMBOL
A1
A2
D
0.25
3.20
-
MIN.
L
1.60 REF.
LEAD FINISHb
R. MIN.0.13
0.19
0.36
0.23
0.40
1.03
0-7°
0.50
3.60
4.10
MAX.
GAGE PLANE
0.25
0.13/0.30 R.
SECTION B - B
DETAIL "A"
TOP VIEW
BOTTOM VIEW
SEE DETAIL "A"
(N-4)X
NOTES:
0.13 M C DA-B
PLANE
C
SEATING
b
0.10
e
CA1
A A2
H
D
8
A3
1
N
PIN 1 INDICATOR
3
D 3
B
E E1
0.25 C A-B 4X
D1
A-BH0.20 D 4X
D
0.11
0.11
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 81
76. 176-Pin LQFP Package Dimensions in Millimeters
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
TO THE LOWEST POINT ON THE PACKAGE BODY.
7. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
BASE METAL
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE
ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1
DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
8.
OF THE PACKAGE BY 0.15 MM.
DIMENSIONS.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
6. SECTION B-B:
3.
1b
c c 1
c1
c
0.09
0.09
b1
b
0.17
0.17
0.13
0.15
0.16
0.20
0.20
0.22
0.23
0.27
26.00 BSCE
0.45L
N
e
E1
0.60 0.75
0.50 BSC
176
24.00 BSC
D1
D
A2
A1
1.35
0.05
26.00 BSC
24.00 BSC
1.40
-
1.45
0.15
SYMBOL
A -
MIN.
-
NOM.
1.60
MAX.
SEE DETAIL "A"
LEAD FINISH
C SEATING PLANE
8.
b
0.08
b
-BCM A D
4X
D 3.
e
3. A
B
D
GAUGE PLANE
0.08 C
A1
A A2
1.00 REF.
0.20 MIN.
L
0-7
H
0.25
E
3.
E1
A-BC A-B0.20
H0.20 DD
D1
SECTION B - B
DETAIL "A"
NOTES:
PIN 1 INDICATOR
1
N
MARKINGORIENTATION
TOP VIEW BOTTOM VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
82 FPGA-DS-02053-6.3
77. 184-Ball csBGA Package Dimensions in Millimeters
C
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
A1 BALL I.D.IDENTIFIER
b
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
.05
.15
2.
1.
3
3B
MM
CC A
4
ddd
e
S
N
S
e
M
0.25 0.30b
0.50 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.08
0.10
1.35
NOM.
0.25 BSC
6.50 BSC
8.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
1.20
0.16
bbb C
C
MAX.
1.50
1.34
1A
aaa
4X6
D
E
A2A
B
A
5(4X)
- -
--
TOP VIEWBOTTOM VIEW
SIDE VIEW
14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
0.10
0.35
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 83
78. 196-Ball caBGA Package Dimensions in Millimeters
C
A1 BALL I.D.IDENTIFIER
b
.08
.153
BMM
CC A
4
ddd
e
S
N
Se
M
bbb C
C1A
aaa
4X 6
D
E
A2A
B
A
5(4X)
7.
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
JEDEC REFERENCE: JEP95DR4.5
0.45 0.50b
0.80 BSC
aaa
ddd
bbb
e
-
-
-
-
- 0.20
0.15
-
NOM.
0.40 BSC
10.40 BSC
12.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
-
0.27
MAX.
1.60
1.10--
0.20
0.55
BOTTOM VIEW TOP VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
84 FPGA-DS-02053-6.3
79. 196-Ball csBGA Package Dimensions in Millimeters
C
4
ddd
bbb C
C
1A
A 2A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.25 0.30b
0.50 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.08
0.10
-
NOM.
0.25 BSC
6.50 BSC
8.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
-
0.15
MAX.
1.00
0.85
- -
--
A1 BALL I.D.IDENTIFIER
aaa
4X6
D
E
B
A
5(4X)
b
.08.15
3B
MM
CC A
e
S
N
S
e
M
BOTTOM VIEW TOP VIEW
SIDE VIEW
0.10
0.35
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 85
80. 208-Ball ftBGA Package Dimensions in Millimeters
C
4
ddd
bbb C
C
1A
A 2A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.40 0.50b
1.0 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.12
0.20
1.40
NOM.
0.50 BSC
15.0 BSC
17.0 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
1.25
0.30
MAX.
1.55
1.25
- -
--
A1 BALL I.D.IDENTIFIER
aaa
4X6
D
E
B
A
5(4X)
b
.10
.253
BMM
CC A
e
S
N
S
e
M
BOTTOM VIEW TOP VIEW
SIDE VIEW
0.60
0.25
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
86 FPGA-DS-02053-6.3
81. 208-Ball fpBGA Package Dimensions in Millimeters
S
1.
2.
NOTES: UNLESS OTHERWISE SPECIFIED
6
4
5
3
0.50 BSC
1.00 BSC
15.00 BSC
15.30
17.00 BSC
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICALPRIMARY DATUM C AND SEATING
EXACT SHAPE AND SIZE OF THIS FEATURE
MAXIMUM SOLDER BALL DIAMETER,DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
IS OPTIONAL.
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
--ccc
ddd -
aaa
bbb
e
b
S
M/N
D/E
B/C
-
-
0.50
-
-
0.60
14.80
bbb
DIMENSIONS AND TOLERANCES PER ANSI Y14.5M.
ddd
4 C
C
A
b
3
e
.10
.25
M
M
C
C B
S
e
L
T
R
P
N
M
K
J
H
G
F
N
Cccc
SYMBOL
A
A2
A1
C
MIN.
1.30
0.30
0.30
1.70
0.50
0.50
NOM.
4X6
A
C
0.35
0.20
0.20
0.25
0.70
15.80
2.10
0.70
0.70
MAX.
2
1
AA
E
A1 CORNER
INDEX AREA
1415 0161 111213 139 45678 2
M
E
D
C
B
A
aaa(4X)
AD
B
5
B
BOTTOM VIEW
TOP VIEW
SIDE VIEW
-
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 87
82. 208-Pin PQFP Package Dimensions in Millimeters
0° MIN.
0.20 MIN.
-
NOM.
-
3.40
30.60 BSC
0.60
30.60 BSC
28.00 BSC
28.00 BSC
208
0.50 BSC
-
0.20
0.12
-
3. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
TO THE LOWEST POINT ON THE PACKAGE BODY .
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
4. 0 DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1
5. 0 THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
THESE DIMENSI ONS APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
7. 0 A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
EXACT SHAPE OF EXPOSED HEATSINK IS OPTIONAL.9.
6. 0 SECTION B-B:
8.
DIMENSIONS.
OF THE PACKAGE BY 0.15 MM.
c1 0.09
N
e
b
b1
c 0.09
0.17
0.17
E
E1
L
D1
0.45
2. 0 ALL DIMENSIONS ARE IN MILLI METERS.
1. 0 DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
c
BASE METAL1b
c1
A
SYMBOL
A1
A2
D
0.25
3.20
-
MIN.
L
1.30 REF.
LEAD FINISHb
R. MIN.0.08
0.16
0.23
0.20
0.27
0.75
0-8°
0.50
3.60
4.10
MAX.
GAGE PLANE
0.25
0.08/0.25 R.
SECTION B - B
DETAIL "A"
TOP VIEW
BOTTOM VIEW
SEE DETAIL "A"
(N-4)X
NOTES:
0.08 M C DA-B
PLANE
C
SEATING
0.08
b
e
CA1
A A2
H
D
8
A3
1
N
PIN 1 INDICATOR
3
D 3
B
E E1
0.25 A-B 4X
D1
A-BH0.20 D 4X
DC
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
88 FPGA-DS-02053-6.3
83. 225-Ball ucBGA Package Dimensions in Millimeters
C4 ddd
bbb C
C1A
A2
A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
30.20 0.25b
0.40 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.10
0.10
NOM.
5.60 BSC
7.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
0.10
MAX.
1.00
0.90
- -
--
6
--
b
.05
.153
BMM
CC A
e
N
e
M
aaa
4X 6
D
E
B
A
5(4X)
PIN #1 ID FIDUCIAL LOCATED IN THIS AREA
BOTTOM VIEW TOP VIEW
SIDE VIEW
0.30
0.10
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 89
84. 237-Ball ftBGA Package Dimensions in Millimeters
C
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
A1 BALL I.D.IDENTIFIER
b
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
.10
.25
2.
1.
3
3B
MM
CC A
4
ddd
e
S
N
S
e
M
0.40 0.50 06.0b
1.0 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.15
0.20
1.55
NOM.
0.50 BSC
15.0 BSC
17.0 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
1.40
0.30
bbb C
C
MAX.
1.70
1A
aaa
4X6
D
E
A2A
B
A
5(4X)
- -
-
DEPOPULATED 13G TO 13R, 10G TO 10K,AND 9F TO 9L.7
7
- 1.24
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B
CD
E
F
GH
J
K
L
M
NP
RT
0.25
BOTTOM VIEW TOP VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
90 FPGA-DS-02053-6.3
85. 256-Ball caBGA Package Dimensions in Millimeters
C
4
ddd
bbb C
C1A
A2A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.40 0.45 05.0b
0.80 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.20
0.15
NOM.
0.40 BSC
12.0 BSC
14.0 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.25
MAX.
1.70
-
-
-
-0.65
REFERENCE JEDEC MO-275, VARIATION JJAB-2.7.
A1 CORNERINDEX AREA
aaa
4X6
D
E
B
A
5(4X)
b
.08
.153
BMM
CC A
e
S
N
S
e
M
-
-
0.20
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 91
86. 256-Ball csfBGA Package Dimensions in Millimeters
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM C.MAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.30b
0.50 BSC
aaa
ccc
bbb
e
0.10
0.08
0.10
NOM.
0.25 BSC
7.50 BSC
9.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.15
MAX.
1.00- -
0.66
M A1 CORNERINDEX AREA aaa
4X6
D
E
B
A
5
(4X)
N
e
b
eeeddd
3B
MM
CC A
S
e
C
4
ccc
bbb C
CA
A2A
1
0.24 -
0.25 0.35
- -
eee
ddd
0.05
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
BC
D
EF
GH
J
KL
M
NP
RT
0.15
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
92 FPGA-DS-02053-6.3
87. 256-Ball ftBGA Package Option 1: ispMACH 4000, MachXO, LatticeXP2
Dimensions in Millimeters
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS. 4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM C
MAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.40 0.50 b
1.00 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.12
0.20
1.40
NOM.
0.50 BSC
15.0 BSC
17.0 BSC
MIN. SYMBOL
A2
A1
D/E
M/N
A
S
1.25
0.30
MAX.
1.55
1.25
-
- -
C
4
ddd
bbb C
C
1 A
A 2 A b
.10
.25 3
B
M
M
C
C A
e
S
N
S
e
M
A1 BALL I.D. IDENTIFIER
aaa
4X 6
D
E
B
A
5 (4X)
0.60
0.25
-
BOTTOM VIEW TOP VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 93
88. 256-Ball ftBGA Package Option 2: LatticeECP3™ Dimensions in Millimeters
C
4
ddd
bbb C
C1A
A 2A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
b
1.0 BSC
aaa
ddd
bbb
e
-
-
-
NOM.
0.50 BSC
15.0 BSC
17.0 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
1.30
0.30
MAX.
1.40 REF
0.50
1.70
0.50
0.20
0.25
0.20
-
-
-
b
.10
.253
BMM
CC A
e
S
N
S
e
M
aaa
4X6
D
E
B
A
5(4X)
INDEX AREAA1 CORNER
2.10
0.70
0.60 0.70
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
94 FPGA-DS-02053-6.3
89. 256-Ball ftBGA Package Option 3: MachXO2 Dimensions in Millimeters
C
4
ddd
bbb C
C1A
A 2A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.40 0.50 06.0b
1.0 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.12
0.20
1.55
NOM.
0.50 BSC
15.0 BSC
17.0 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
1.40
0.30
MAX.
1.70
- -
- -1.00
A1 BALL I.D.IDENTIFIER
aaa
4X6
D
E
B
A
5(4X)
b
.10
.253
BMM
CC A
e
S
N
S
e
M
0.25
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 95
90. 256-Ball fpBGA Package Dimensions in Millimeters
AD
4X
ccc
ddd
aaa
bbb
M/N
D/E
B/C
SYMBOLNOTES: UNLESS OTHERWISE SPECIFIED
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICALPRIMARY DATUM C AND SEATING
EXACT SHAPE AND SIZE OF THIS FEATURE
MAXIMUM SOLDER BALL DIAMETER,DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
IS OPTIONAL.
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
DIMENSIONS AND TOLERANCES
PER ANSI Y14.5M.
4
6
5
2.
3
1.
12
M
M
b
3 .10
.25
S
e
141516 13
4
ddd C
A
C
C
S
e
Cccc
C
Cbbb
L
T
R
P
N
M
K
J
H
G
F
N
10 9 4567811
M
123
E
D
C
B
A
-
-
-
-
1.00 BSC
0.60
-
-
-
-
0.50
e
b
0.35
0.20
0.20
0.25
0.70
0.50 BSC
15.00 BSC
15.30
17.00 BSC
1.70
0.50
0.50
NOM.
14.80
S
MIN.
1.30
0.30
0.30
A
A2
A1
15.80
2.10
0.70
0.70
MAX.
6
1
A
A2A
C
B
E
B
A1 CORNER
INDEX AREA (4X) aaa
5 TOP VIEW
BOTTOM VIEW
SIDE VIEW
B
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
96 FPGA-DS-02053-6.3
91. 256-Ball SBGA Package Dimensions in Millimeters
A-A SECTION VIEW
Y
W
P
R
T
U
V
K
L
M
N
E
F
G
H
J
A
B
C
D
DIMENSIONS AND TOLERANCES
IS OPTIONAL.
PARALLEL TO PRIMARY DATUM C
PER ANSI Y14.5M.
CROWNS OF THE SOLDER BALLS.
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICALPRIMARY DATUM C AND SEATING
EXACT SHAPE AND SIZE OF THIS FEATURE
MAXIMUM SOLDER BALL DIAMETER,
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
NOTES: UNLESS OTHERWISE SPECIFIED
4
6
5
3
2.
1.
0.20
1.00
1.70
0.90
0.20
0.25
0.80
--A
1.27 BSCe
-
0.25
0.10
-
-
aaa
ddd
bbb
A4
Q
-
-
-
-
-
0.80
0.60
0.50
M/N
S
b
D/E
A2
A1
0.75
0.635 BSC
24.13 BSC
0.90
27.00 BSC
0.65
MIN.SYMBOL NOM.
-
-
MAX.
Q
1
C
ddd
bbb
4
C
C
4A AA2A
b
3 .15
.30M
M
C
C
e
S
A
e
S
A A
N
M
4X6
A1 BALL I.D.
IDENTIFIER
5(4X)
aaa
D
E
AB
TOP VIEWBOTTOM VIEW
SIDE VIEW
B
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 97
92. 272-Ball BGA Package Dimensions in Millimeters
1.
NOTES: UNLESS OTHERWISE SPECIFIED
6
5
4
3
2.
0.635 BSC
1.27 BSC
24.13 BSC
27.00 BSC
0.650.50A1PER ANSI Y14.5M.
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
PRIMARY DATUM C AND SEATING
EXACT SHAPE AND SIZE OF THIS FEATURE
MAXIMUM SOLDER BALL DIAMETER,
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
IS OPTIONAL.
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
ddd
ccc
bbb
-
-
-
-
-
-
M/N
aaa
e
b
S
B/C
D/E
A2
-
0.60
-
0.75
23.80
0.28
24.30
0.54
DIMENSIONS AND TOLERANCES
SYMBOL
A
MIN.
1.90
NOM.
2.25
0.80
0.20
0.35
0.25
0.20
0.90
24.80
0.80
MAX.
2.80
4ddd C
bbb
C
CC
ccc
1A
A2A
SG
b
3
e
M
M
.15
.30 BA
C
C
Se
U
Y
W
V
M
P
N
R
T
J
H
L
KN
8182019 15
1617 11
1213
149
10
M
7 56 2
34
C
F
E
D
1
B
A
4X6
C E
A1 BALL I.D.
IDENTIFIER
aaa
B
D
(4X) 5
B
A
TOP VIEW
BOTTOM VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
98 FPGA-DS-02053-6.3
93. 284-Ball csBGA Package Dimensions in Millimeters
C
4
ddd
bbb C
C1A
A2A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.25 0.31 73.0b
0.50 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.08
0.10
NOM.
0.25 BSC
10.50 BSC
12.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.15
MAX.
1.00
0.85
-
--
-
A1 BALL I.D.IDENTIFIER
aaa
4X6
D
E
B
A
5(4X)
b
.05
.153
BMM
CC A
e
S
N
S
e
M
-
-
0.10
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 99
94. 285-Ball csfBGA Package Dimensions in Millimeters
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.30b
0.50 BSC
aaa
ccc
bbb
e
0.10
0.08
0.10
NOM.
0.25 BSC
8.50 BSC
10.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.15
MAX.
1.30- -
1.00
MA1 CORNER
INDEX AREAaaa
4X6
D
E
B
A
5(4X)
N
e
b
eeeddd
3B
MM
CC A
S
e
C
4
ccc
bbb C
CA
A2A
1
-
0.25 0.35
-
eee
ddd
0.05
-
-
18
17
16
1514
1312
1110
98
76
54
32
1
AB
C
DE
FG
H
JK
L
M
N
PR
T
UV
0.15
BOTTOM VIEW TOP VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
100 FPGA-DS-02053-6.3
95. 289-Ball csBGA Package (9.5 mm x 9.5 mm Body) Dimensions in Millimeters
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 101
96. 320-Ball SBGA Package Dimensions in Millimeters
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
102 FPGA-DS-02053-6.3
97. 324-Ball caBGA Package Dimensions in Millimeters
C
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM C.MAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
4
ddd
0.40 0.45 05.0b
0.80 BSC
aaa
ddd
ccc
e
-
-
-
-
-
-
0.20
0.15
NOM.
0.40 BSC
13.6 BSC
15.0 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.25
ccc C
C
MAX.
1.70
1A
A2A
0.35
1.00
- -
-0.80
N
A1 CORNERINDEX AREA
aaa
4X 6
D
E
B
A
5(4X)
M
S
e
b
.08
.153
BMM
CC A
S
e
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
-
0.20
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 103
98. 324-Ball csfBGA Package Dimensions in Millimeters
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM C.MAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.30b
0.50 BSC
aaa
ccc
bbb
e
0.10
0.08
0.10
NOM.
0.25 BSC
8.50 BSC
10.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.15
MAX.
1.00- -
0.66
MA1 CORNER
INDEX AREAaaa
4X6
D
E
B
A
5(4X)
N
e
b
eeeddd
3B
MM
CC A
S
e
C
4
ccc
bbb C
CA
A2A
1
0.24 -
0.25 0.35
- -
eee
ddd 0.15
0.05
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
104 FPGA-DS-02053-6.3
99. 324-Ball ftBGA Package Dimensions in Millimeters
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS. 4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM C MAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.40 0.60 07.0 b
1.00 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.20
0.20
1.50
NOM.
0.50 BSC
17.0 BSC
19.0 BSC
MIN. SYMBOL
A2
A1
D/E
M/N
A
S
1.25
0.30
MAX.
1.70
1.40
-
- -
C
4
ddd
bbb C
C
1 A
A 2 A b
.10
.25 3
B M M
C C A
e
S
N
S
e
M
A1 BALL I.D. IDENTIFIER
aaa
4X 6
D
E
B
A
5 (4X)
BOTTOM VIEW TOP VIEW
SIDE VIEW
0.25
-
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 105
100. 328-Ball csBGA Package Dimensions in Millimeters
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.25b
0.50 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.08
0.10
NOM.
9.00 BSC
10.0 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
0.15
MAX.
1.50
- -
-
1.351.05
-
A1 BALL
IDENTIFIER
aaa
4X6
D
E
B
A
5(4X)
b
.05
.153
BMM
CC A
e
N
e
M
C
4
ddd
bbb C
C
1A
A 2A
BOTTOM VIEW TOP VIEW
SIDE VIEW
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.50 BSC
aaa
ddd
bbb
e
-
-
-
-
-
NOM.
9.00 BSC
10.0 BSC
MIN.
A2
A1
D/E
M/N
A
0.15
MAX.
1.351.05
-
A1 BALL
IDENTIFIER
aaa
4X6
D
E
B
A
5(4X)
b
.05
.153
BCC A
e
N
e
M
C
4
ddd
bbb C
C
1A
A 2A
BOTTOM VIEW TOP VIEW
SIDE VIEW
0.10
1.20
0.350.30
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
106 FPGA-DS-02053-6.3
101. 332-Ball caBGA Package Dimensions in Millimeters
C
4
ddd
bbb C
CA
A 2A
1
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.40 0.45 05.0b
0.80 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.20
0.15
NOM.
0.40 BSC
15.2 BSC
17.0 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.25
MAX.
2.00
- -
- -
0.65
A1 CORNERINDEX AREA
aaa
4X6
D
E
B
A
5(4X)
b
.08
.153
BMM
CC A
e
S
N
S
e
M
BOTTOM VIEWTOP VIEW
SIDE VIEW
0.20
- -
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 107
102. 352-Ball SBGA Package Dimensions in Millimeters
Cddd
Q4 C
A 4
A
bbb C
1A 2 A
AD
AC
AB
AL
e
3
b
BM.15 C
S
.30 M C A
Y
AF
AE
AA
W
T
U
V
M
N
P
R
S
M
B
G
H
J
K
C
D
E
F
A
A
e
N
4X6
aaa
A1 BALL I.D.IDENTIFIER
(4X) 5
D A
E
B
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICALPRIMARY DATUM C AND SEATING
EXACT SHAPE AND SIZE OF THIS FEATURE
MAXIMUM SOLDER BALL DIAMETER,DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
NOTES: UNLESS OTHERWISE SPECIFIED
4
5
6 IS OPTIONAL.
A-A SECTION VIEW
1.
3
2.
PER ANSI Y14.5M.
1.00
1.70
0.20
0.90
0.25
0.20
0.80
MAX.
A4
Q
ddd
bbb
aaa
e
--
0.10
-
-
0.25
-
-
-
1.27 BSC
-
b
S
M/N
D/E
A2
A1
A
SYMBOL
0.650.50
0.635 BSC
31.75 BSC
35.00 BSC
0.60
0.80
0.75
0.90
-
MIN. NOM.
-
-
-
BOTTOM VIEW
TOP VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
108 FPGA-DS-02053-6.3
103. 381-Ball caBGA Package Dimensions in Millimeters
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERAN CE ZONE IS APPLIED
PLANE AR E DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSIO N "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS O THERWISE SPECIFIED
DIMENSIONS AND TOLERAN CES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.35 0.40b
0.80 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.12
0.15
NOM.
0.40 BSC
15.20 BSC
17.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.25
MAX.
1.76
0.30
- -
0.80
A1 CORNERINDEX AREA
aaa
4X6
D
E
B
A
5(4X)M
N
e
b
.08
.153
BMM
CC A
S
e
C
4
ddd
bbb C
CA
A2A
1
0.35
- -
0.20
0.45
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 109
104. 388-Ball BGA Package Dimensions in Millimeters
ddd4
1
C
C
bbb CCccc
AA
2A
SJ
3
b
e
A.30 C
.15 CM
S
B
e
V
AC
AD
AE
AF
W
Y
AA
AB
PN
R
T
U
K
L
M
N
13
M
202425
2632 12
2217
1819
61 4115
21 0111
81
F
E
G
H
B
C
D
A
4X6
C E
aaa
A1 BALL I.D.IDENTIFIER
AD
B
(4X) 5
B
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICALPRIMARY DATUM C AND SEATING
EXACT SHAPE AND SIZE OF THIS FEATURE
MAXIMUM SOLDER BALL DIAMETER,DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
NOTES: UNLESS OTHERWISE SPECIFIED
6
5
IS OPTIONAL.
2.
4
3
1.PER ANSI Y14.5M.
1.27 BSCe
0.20
0.35
0.25
0.20ddd
ccc
bbb
aaa
-
-
-
-
-
-
-
-
0.80
3.25
33.80
0.90
0.80
MAX.
M/N
D/E
B/C
A2
A1
A
SYMBOL
b
S 0.635 BSC
31.75 BSC
35.00 BSC
0.60
29.80
0.75
31.80
1.90
0.28
0.50
MIN.
2.80
0.54
0.65
NOM.
BOTTOM VIEWTOP VIEW
SIDE VIEW
76
54
32
M
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
110 FPGA-DS-02053-6.3
105. 388-Ball fpBGA Package Dimensions in Millimeters
S
1.
2.
NOTES: UNLESS OTHERWISE SPECIFIED
6
4
5
3
0.50 BSC
1.00 BSC
21.00 BSC
19.80
23.00 BSC
A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICALPRIMARY DATUM C AND SEATING
EXACT SHAPE AND SIZE OF THIS FEATURE
MAXIMUM SOLDER BALL DIAMETER,DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
IS OPTIONAL.
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
--ccc
ddd
aaa
bbb
e
b
S
M/N
D/E
B/C
-
-
0.50
-
-
0.60
19.30
B
M
M
.103
.25C
C
4
DIMENSIONS AND TOLERANCES PER ANSI Y14.5M.
Cddd
C
bbb C
e
b
S
Y
e
AB
AA
P
V
U
T
R
W
M
L
K
J
NN
SYMBOL
A
A2
A1
ccc C
MIN.
1.70
0.30
0.30
2.15
0.50
0.50
NOM.
64X
A
0.35
0.20
0.20
0.25
0.70
20.30
1
2.60
0.70
0.70
MAX.
2A
C E
A1 CORNER
INDEX AREA
2122 1720 91 81 141516 13
M
491012 11 578 6
G
F
E
D
C
H
3 2 1
A
B
(4X)aaa
B
D
5
B
ABOTTOM VIEW
TOP VIEW
SIDE VIEW
A
--
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 111
106. 400-Ball caBGA Package Dimensions in Millimeters
ALL DIMENSIONS ARE IN MILLIMETERS.
PARALLEL TO PRIMARY DATUM C.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
MAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.40 0.45 05.0b
0.80 BSC
aaa
ddd
ccc
e
-
-
-
-
-
-
0.20
0.15
NOM.
0.40 BSC
15.2 BSC
17.0 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.25
MAX.
1.70
0.35 -
- -
0.80
S
e
b
.08
.153
BMM
CC A
S
e
N
M
A1 CORNERINDEX AREA
aaa
4X6
D
E
B
A
5(4X)
C
4
ddd
ccc C
CA
A2 A
1
2019
1817
1615
1413
12
1110
9
8
7
6
5
4
3
2
1
A
BC
D
E
F
G
HJ
KL
M
N
P
R
T
UV
WY
0.20
1.00 -
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
112 FPGA-DS-02053-6.3
107. 416-Ball fpBGA Package Dimensions in Millimeters
NN
IS OPTIONAL.
ALL DIMENSIONS ARE IN MILLIMETERS.
EXACT SHAPE AND SIZE OF THIS FEATURE
NOTES: UNLESS OTHERWISE SPECIFIED
6
5
4
3
2.
1.
3
b
e
0.70
2.60
25.80
0.20
0.70
0.35
0.25
0.20
0.70
MAX.
PER ANSI Y14.5M.
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICALPRIMARY DATUM C AND SEATING
MAXIMUM SOLDER BALL DIAMETER,DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
--bbb
ddd
ccc
-
-
-
-
0.30
23.80
0.50
e
aaa
b
S
M/N
D/E
B/C
A2
0.60
0.50 BSC
1.00 BSC
--
0.50
25.00 BSC
24.80
27.00 BSC
ccc
B.25 C
DIMENSIONS AND TOLERANCES
M.10 C
4
bbb
Cddd
C
C
Se
AF
AE
W
AD
AC
AB
AA
Y
V
U
T
R
P
1.70
0.30
MIN.SYMBOL
A1
A
C
2.15
0.50
NOM.
4X6
A
C
2AA 1
E
S
A1 CORNER
18
23
26 24
25
22 20
21 19
M
1416
17 15
12 10
13 11
A
G
M
L
K
J
H
F
E
D
C
B
IND EX AREA
5
8 6
9 7
4
3
2
1
5
aaa (4X)
D
B
A
B
BOTTOM VIEWTOP VIEW
SIDE VIEW
AM
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 113
108. 432-Ball SBGA Package Dimensions in Millimeters
DIMENSIO NS AND TOLERANCES
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED B Y THE SPHERICAL
PRIMARY DATUM C AND SEATING
EXACT SHAPE AND SIZE OF THIS FEATURE
MAXIMUM SOLDER BALL DIAMETER,
DIMENSIO N "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
NOTES: UNLESS OTHERWISE SPECIFIED
5
6 IS OPTIONAL.
3
4
2.
1.
PER ANSI Y14.5M.
A-A SECTION VIEW
A4 0.10 --
0.20
0.25
0.20ddd
bbb
aaa
-
-
-
-
-
-
1.00
1.70
0.90
0.80
MAX.
M/N
D/E
A2
A1
A
e
Q
b
S
38.10 BSC
0.00 BSC
1.27 BSC
0.25
0.60
-
0.75
40.00 BSC
0.80
0.50
-
0.90
0.65
-
SYMBOL MIN. NOM.
-
4A
Q
2
Cddd
4 C
bbb C
AA 1
A
3
b
e
A
.15
.30
M C
M C
S
B
e
M
A S
N
A
4X6
aaaA1 BALL I.D.
IDENTIFIER
5(4X)
D A
E
B
AG
AK
AJ
AH
AL
AF
AE
AD
AC
V
Y
AB
AA
W
P
R
T
U
J
K
L
M
N
E
F
G
H
A
B
C
D
BOTTOM VIEW
TOP VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
114 FPGA-DS-02053-6.3
109. 484-Ball caBGA Package (19 mm x 19 mm Body) Dimensions in Millimeters
M
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
21
A
BC
DE
F
G
HJ
K
LN
MN
P
R
T
U
VW
Y
AAAB
e
S
e
b
3 eee M C A BCfff M
A1 CORNERINDEX AREA aaa (4X)
5
D A
B
E
64X
ccc C
4
ddd CC
A2 A
A1
NOTES: UNLESS OTHERWISE SPECIFIED
1. DIMENSIONS AND TOLERANCES PER ANSI Y14.5M.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C
4. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
5. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY.
6. EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.
7. JEDEC REFERENCE: MO-275A
SYMBOL
A
A1
A2
D/E
M/N
S
b
e
aaa
ccc
ddd
eee
fff
MIN. NOM. MAX.
1.70
0.25
0.65
19.0 BSC
16.8 BSC
0.40 BSC
0.40 0.45 0.50
0.80 BSC
0.15
0.20
0.20
0.15
0.08
S
BOTTOM VIEW TOP VIEW
SIDE VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 115
110. 484-Ball fpBGA Package Dimensions in Millimeters
S
1.
2.
NOTES: UNLESS OTHERWISE SPECIFIED
6
4
5
3
0.50 BSC
1.00 BSC
21.00 BSC
19.80
23.00 BSC
A
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICALPRIMARY DATUM C AND SEATING
EXACT SHAPE AND SIZE OF THIS FEATURE
MAXIMUM SOLDER BALL DIAMETER,DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
IS OPTIONAL.
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
--ccc
ddd
aaa
bbb
e
b
S
M/N
D/E
B/C
-
-
0.50
-
-
0.60
19.30
B
M
M
.103
.25C
C
4
DIMENSIONS AND TOLERANCES PER ANSI Y14.5M.
Cddd
C
bbb C
e
b
S
Y
e
AB
AA
P
V
U
T
R
W
M
L
K
J
NN
SYMBOL
A
A2
A1
ccc C
MIN.
1.70
0.30
0.30
2.15
0.50
0.50
NOM.
64X
A
0.35
0.20
0.20
0.25
0.70
20.30
1
2.60
0.70
0.70
MAX.
2A
C E
A1 CORNER
INDEX AREA
2122 1720 91 81 141516 13 491012 11 578 6
G
F
E
D
C
H
3 2 1
A
B
M
(4X)
aaa
B
D
5
B
ABOTTOM VIEW
TOP VIEW
SIDE VIEW
A
--
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
116 FPGA-DS-02053-6.3
111. 484-Ball fcBGA Package: Mach™-NX
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
b
0.80 BSC
aaa*
ccc
bbb*
e
-
-
-
NOM.
0.40 BSC
16.80 BSC
19.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
-
0.27
MAX.
2.086 REF
- -
- 2.736
0.45 0.50 0.55
0.20
0.25
0.35
-
-
-
ddd 0.20JEDEC REFERENCE: JEP95 DR4.57.
* THESE VALUES ARE BASED ON SUBCON CAPABILITY
SIDE VIEW
TOP VIEW
BOTTOM VIEW
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 117
112. 516-Ball fpBGA Package Dimensions in Millimeters
R
ECN
.10
.25
IS OPTIONAL.
ALL DIMENSIONS ARE IN MILLIMETERS.
EXACT SHAPE AND SIZE OF THIS FEATURE
NOTES: UNLESS OTHERWISE SPECIFIED
6
5
4
3
2.
3
1.
b
e
0.70
2.60
29.30
0.20
0.70
0.35
0.25
0.20
0.70
MAX.
PER ANSI Y14.5M.
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICALPRIMARY DATUM C AND SEATING
MAXIMUM SOLDER BALL DIAMETER,DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
--bbb
ddd
ccc
-
-
-
-
0.30
25.80
0.50
e
aaa
b
S
M/N
D/E
B/C
A2
0.60
0.50 BSC
1.00 BSC
--
0.50
29.00 BSC
27.55
31.00 BSC
M C
DIMENSIONS AND TOLERANCES
4
bbb
ddd C
C
C
AC B
S
A F
e
A K
A J
A H
A G
A A
A E
A D
A C
A B
Y
W
V
U
T
1.70
0.30
MIN.SYMBOL
A1
A
Cccc
2.15
0.50
NOM.
4X6
A1A
A2
27
S
30 28
29
INDEX AREA
1826 24 22 20
2325 21 19
16 14 12 10
17 15 13 11
M
C
J
P
N
M
L
K
H
G
F
E
D
8 6 4 2
59 7 3 1
A
B
A1 CORNER
aaa (4X)
B
D
5
B
A
6
OPTIONAL FEATURE
(HEAT SINK)
BOTTOM VIEWTOP VIEW
SIDE VIEW
M
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
118 FPGA-DS-02053-6.3
113. 554-Ball caBGA Package Dimensions in Millimeters
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.35 0.40 54.0b
0.80 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.12
0.15
NOM.
0.40 BSC
20.0 BSC
23.0 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
S
0.25
MAX.
1.76
0.30
- -
0.80 -
M
A1 CORNERINDEX AREA
aaa
4X6
D
E
B
A
5(4X)
N
e
b
.08
.153
BMM
CC A
S
e
C
4
ddd
bbb C
CA
A2A
1
25
1826 24 22 20
2123 19
16 14 12 10
17 15 13 11
8 6 4 2
59 7 3 1
R
AF
AA
AE
AD
AC
AB
Y
WV
U
T
C
J
P
N
M
L
K
H
G
F
E
D
A
B
0.20
0.35
-
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 119
114. 672-Ball fpBGA Package Dimensions in Millimeters
NN
IS OPTIONAL.
ALL DIMENSIONS ARE IN MILLIMETERS.
EXACT SHAPE AND SIZE OF THIS FEATURE
NOTES: UNLESS OTHERWISE SPECIFIED
6
5
4
3
2.
1.
3
b
e
0.70
2.60
25.80
0.20
0.70
0.35
0.25
0.20
0.70
MAX.
PER ANSI Y14.5M.
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICALPRIMARY DATUM C AND SEATING
MAXIMUM SOLDER BALL DIAMETER,DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
--bbb
ddd
ccc
-
-
-
-
0.30
23.80
0.50
e
aaa
b
S
M/N
D/E
B/C
A2
0.60
0.50 BSC
1.00 BSC
--
0.50
25.00 BSC
24.80
27.00 BSC
ccc
B.25 C
DIMENSIONS AND TOLERANCES
M.10 C
4
bbb
Cddd
C
C
Se
AF
AE
W
AD
AC
AB
AA
Y
V
U
T
R
P
1.70
0.30
MIN.SYMBOL
A1
A
C
2.15
0.50
NOM.
4X6
A
C
2AA 1
E
S
A1 CORNER
18
23
26 24
25
22 20
21 19
M
1416
17 15
12 10
13 11
A
G
M
L
K
J
H
F
E
D
C
B
IND EX AREA
5
8 6
9 7
4
3
2
1
5
aaa (4X)
D
B
A
B
BOTTOM VIEWTOP VIEW
SIDE VIEW
AM
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
120 FPGA-DS-02053-6.3
115. 676-Ball fpBGA Package Dimensions in Millimeters
A C
MIN.
0.30
1.70
0.30
25.80
0.50
.25
.10
NOTES: UNLESS OTHERWISE SPECIFIED
6
4
5
3
2.
1.
b
3
e
A
ALL DIMENSIONS ARE IN MILLIMETERS.
EXACT SHAPE AND SIZE OF THIS FEATURE
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICALPRIMARY DATUM C AND SEATING
MAXIMUM SOLDER BALL DIAMETER,DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
DIMENSIONS AND TOLERANCES
IS OPTIONAL.
PER ANSI Y14.5M.
S
bbb
ccc
ddd
e
b
aaa
B/C
D/E
M/N
A1
A2
4
Cddd
BCM A
CM
S
Cbbb
C
ccc
SYMBOL
C
e
A D
A E
A G
A H
A J
A K
A F
64X
2.602.15
0.50 BSC
1.00 BSC
-
-
-
-
-
-
-
0.60
-
0.25
0.35
0.20
0.70
0.20
31.00 BSC
29.00 BSC
27.55
0.50
0.50
29.30
0.70
0.70
A 2A
NOM. MAX.
1
A
28
S
29
30
5INDEX AREAA1 CORNER
15
22
25 23
2426
27 17
16
1921
20 18
M
8
91113
101214
37 5
2
F
P
T
U
V
W
Y
A B
A A
NR
G
H
K
L
M
N
J
B
A
1
D
E
C
aaa (4X)
B
EC
B
D A
BOTTOM VIEW
TOP VIEW
SIDE VIEW
6 4
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 121
116. 676-Ball fcBGA Package Dimensions in Millimeters
A 1
ddd
DIMENSIONS AND TO LERANCES
TO EACH SIDE OF THE PACKAGE BODY.
DIMENSION "b" IS MEASURED AT THEMAXIMUM SOLDER BALL DIAMETER,
PRIMARY DATUM C AND SEATINGPLANE ARE DEFINED BY THE SPHERICAL
BILATERAL TOLERANCE ZONE IS APPLIED
CROWNS OF THE SOLDER BALLS.
PARALLEL TO PRIMARY DATUM C
NOTES: UNLESS OTHERW ISE SPECIFIED
EXACT SHAPE AND SIZE OF THIS FEATURE
ALL DIMENSIONS ARE IN MILLIMETERS.
5
6 IS OPTIONAL.
PER ANSI Y14.5M.
4
3
2.
1.
4
- -aaa
ddd
ccc
bbb
-
-
-
-
-
0.20
-
M/N
b
e
S
D/E
B/C
A2
25.00 BSC
1.00 BSC
0.50 BSC
0.600.50 0.70
27.00 BSC
26.60
1.20 REF
26.55 26.65
SYMBOL
A
A1
ccc
C
C
bbb CC
NOM.
0.50
2.902.55
0.40
MIN.
3.25
0.60
MAX.
A1 CORNER
A
C
2A
E
A
(4X)aaaINDEX AREA
B
D
5
B
64X
0.35
G
F
F/G 18.6018.55 18.65
NN
3
b
e
B.25 CM.10 C
S e
AF
AE
W
AD
AC
AB
AA
Y
V
U
T
R
P
S
18
23
26 24
25
22 20
21 19
M
1416
17 15
12 10
13 11
A
G
M
L
K
J
H
F
E
D
C
B
5
8 6
9 7
4
3
2
1
BOTTOM VIEWTOP VIEW
SIDE VIEW
AM
0.20
0.25
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
122 FPGA-DS-02053-6.3
117. 680-Ball fpBGA Package (with or without Internal Heat Spreader) Dimensions in Millimeters
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICALPRIMARY DATUM C AND SEATING
EXACT SHAPE AND SIZE OF THIS FEATURE
MAXIMUM SOLDER BALL DIAMETER,DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
NOTES: UNLESS OTHERWISE SPECIFIED
6
5
IS OPTIONAL.
2.
4
3
1.PER ANSI Y14.5M.
1.00 BSCe
0.20
0.35
0.25
0.20ddd
ccc
bbb
aaa
-
-
-
-
-
-
-
-
0.80
30.80
0.70
0.70
2.60
MAX.
M/N
D/E
B/C
A2
A1
A
SYMBOL
b
S
30.3029.80
0.50 BSC
33.00 BSC
35.00 BSC
0.50
1.90
0.40
0.30
MIN.
2.25
0.60
0.50
NOM.
ddd4
1
Cbbb
C
C
Cccc
AA 2A
N
e
b
3
eS
M
.15
.30M
BCC
S
M
A
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
C
DE
FG
HJ
KL
MN
PR
TU
VW
YAA
ABAC
ADAE
AFAG
AHAJ
AKAL
AMAN
AP
EC
4X6
aaaA1 CORNERINDEX AREA
B
(4X)
D
5
A
B
OP TIO NAL FEATURE
6
(HEAT SINK)
BOTTOM VIEW
TOP VIEW
SIDE VIEW
A
0.60
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 123
118. 680-Ball fpSBGA Package Dimensions in Millimeters
A-A SECTION VIEW
SEATING PLANE
C
bbb C
ddd
AA
DIM ENS IONS AND TOLERANCES
IS OPTIONAL.
PARAL LEL TO PRIMARY DA TUM C
PER ANS I Y14.5M.
CROWNS OF THE SOLDER BALL S.
ALL DIMENS IONS A RE IN M ILL IM ETERS.
BILATER AL TOLERANCE ZONE IS A PPLIED
PLANE A RE DEFINED BY THE SPHERICAL
PRIMARY DATUM C AND SEATING
EXA CT SHAPE A ND SIZE OF THIS FEATURE
MA XIM UM S OLDER BALL DIA METER,
DIM ENS ION "b" IS MEASURED AT THE
TO EACH S IDE OF THE PACKAGE BODY.
NOTES: UNLESS OTHERWISE SPECIF IED
5
6
4
1.
3
2.
b
3 C
C
.10
.25
M
M B
A
e
0.00 BSCS
1.00 BSC
0.10A4
bbb
ddd
aaa
-
-
-
e
Q
b
0.25
0.50
--
-
-
-
0.25
0.20
0.20
-
0.65
-
0.80
38.00 BSC
40.00 BSC
0.45A1
D/E
M/N
A2 0.90
SYMBOL
A -
MIN.
0.600.53
0.98
NOM.
- 1.70
MAX.
Q
4A
A
1A
A 2A
4X
S
AN
AWAV
e
AU
ARAT
AP
AG
AL
AJ
AM
AK
AH
AE
AC
AF
AD
AB
6
4
2238 36 34 32 30 28 26 24
S
3139 37 35 33 2729 25 23
aaa
20 18 16 14 12 10 8 6 4 2
131721 19 15 11 9 7 5
JK
R
W
U
Y
V
T
N
N
L
P
M
D
G
E
H
F
C
A
3 1
B
A1 B ALL I.D.
IDENTIFIER
M
(4X) 5
DB
E
A
BOTTOM VIEWTOP VIEW
SIDE VIEW
A
1.05
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
124 FPGA-DS-02053-6.3
119. 756-Ball caBGA Package Dimensions in Millimeters
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICAL
EXACT SHAPE AND SIZE OF THIS FEATURE
DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
PRIMARY DATUM C AND SEATING
IS OPTIONAL.
CROWNS OF THE SOLDER BALLS.4
5
6
PER ANSI Y14.5M.
NOTES: UNLESS OTHERWISE SPECIFIED
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM CMAXIMUM SOLDER BALL DIAMETER,
2.
1.
3
0.35 0.40 54.0b
0.80 BSC
aaa
ddd
bbb
e
-
-
-
-
-
-
0.12
0.15
NOM.
24.80 BSC
27.00 BSC
MIN.SYMBOL
A2
A1
D/E
M/N
A
0.25
MAX.
1.76
0.30
- -
0.80 -
6
5
4
3
0.40 BSCS
A1 CORNERINDEX AREA
aaa
4X
D
E
B
A
(4X)
A
AA
M
e
b
.08
.15 BMM
CC A
e
N
S
Cddd
bbb C
C
2
1
0.35
-
0.20
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 125
120. 900-Ball fpBGA Package Dimensions in Millimeters
RECN
.10
.25
IS OPTIONAL.
ALL DIMENSIONS ARE IN MILLIMETERS.
EXACT SHAPE AND SIZE OF THIS FEATURE
NOTES: UNLESS OTHERWISE SPECIFIED
6
5
4
3
2.
3
1.
b
e
0.70
2.60
29.30
0.20
0.70
0.35
0.25
0.20
0.70
MAX.
PER ANSI Y14.5M.
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
BILATERAL TO LERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICALPRIMARY DATUM C AND SEATING
MAXIMUM SO LDER BALL DIAMETER,DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
--bbb
ddd
ccc
-
-
-
-
0.30
25.80
0.50
e
aaa
b
S
M/N
D/E
B/C
A2
0.60
0.50 BSC
1.00 BSC
--
0.50
29.00 BSC
27.55
31.00 BSC
M C
DIMENSIONS AND TOLERANCES
4
bbb
ddd C
C
C
AC B
S
AF
e
AK
AJ
AH
AG
AA
AE
AD
AC
AB
Y
W
V
U
T
1.70
0.30
MIN.SYMBOL
A1
A
Cccc
2.15
0.50
NOM.
4X6
A1A
A2
27
S
30 28
29
INDEX AREA
1826 24 22 20
2325 21 19
16 14 12 10
17 15 13 11
M
C
J
P
N
M
L
K
H
G
F
E
D
8 6 4 2
59 7 3 1
A
B
A1 CORNERaaa (4X)
B
D
5
B
A
BOTTOM VIEW TOP VIEW
SIDE VIEW
M
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
126 FPGA-DS-02053-6.3
121. 1020-Ball Organic fcBGA Package Dimensions in Millimeters
A 1
ddd
DIMENSIONS AND TOLERANCES
TO EACH SIDE OF THE PACKAGE BODY.
DIMENSION "b" IS MEASURED AT THEMAXIMUM SOLDER BALL DIAMETER,
PRIMARY DATUM C AND SEATINGPLANE ARE DEFINED BY THE SPHERICAL
BILATERAL TOLERANCE ZONE IS APPLIED
CROWNS OF THE SOLDER BALLS.
PARALLEL TO PRIMARY DATUM C
NOTES: UNLESS OTHERWISE SPECIFIED
EXACT SHAPE AND SIZE OF THIS FEATURE
ALL DIMENSIONS ARE IN MILLIMETERS.
5
6 IS OPTIONAL.
PER ANSI Y14.5M.
4
3
2.
1.
4
- -aaa
ddd
ccc
bbb
-
-
-
-
-
0.20
0.35
-
M/N
b
e
S
D/E
B/C
A2
31.00 BSC
1.00 BSC
0.50 BSC
0.600.50 0.70
33.00 BSC
32.00
1.24 REF
31.10 32.90
SYMBOL
A
A1
ccc
C
C
bbb CC
NOM.
0.50
3.122.52
0.30
MIN.
3.82
0.70
MAX.
A1 CORNER
b
e
S
S
e
A
C
2A
E
A
(4X)aaaINDEX AREA
B
D
5
B
3 .10.25 AC B
M C
4
29
30 16
2327 25
82 62 24
21 1719
2022 18
M
10
1315 11
14 12
79 5
8 6
13
2
31
32
A
AA
AF
AH
AK
AJ
AG
AB
AD
AE
AC
L
T
NV
Y
W
U
M
P
R
N
F
H
K
J
G
B
D
E
C
AM
AL
64X
BOTTOM VIEWTOP VIEW
SIDE VIEW
M
0.25
0.20
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 127
122. 1020-Ball Organic fcBGA Package Rev. 2 Dimensions in Millimeters
A 1
ddd
DIMENSIONS AND TOLERANCES
TO EACH SIDE OF THE PACKAGE BODY.
DIMENSION "b" IS MEASURED AT THEMAXIMUM SOLDER BALL DIAMETER,
PRIMARY DATUM C AND SEATINGPLANE ARE DEFINED BY THE SPHERICAL
BILATERAL TOLERANCE ZONE IS APPLIED
CROWNS OF THE SOLDER BALLS.
PARALLEL TO PRIMARY DATUM C
NOTES: UNLESS OTHERWISE SPECIFIED
EXACT SHAPE AND SIZE OF THIS FEATURE
ALL DIMENSIONS ARE IN MILLIMETERS.
5
6 IS OPTIONAL.
PER ANSI Y14.5M.
4
3
2.
1.
4
- -aaa
ddd
ccc
bbb
-
-
-
-
-
0.20
-
M/N
b
e
S
D/E
B/C
A2
31.00 BSC
1.00 BSC
0.50 BSC
0.600.50 0.70
33.00 BSC
32.60
1.20 REF
32.40 32.80
SYMBOL
A
A1
ccc
C
C
bbb CC
NOM.
0.50
2.902.55
0.40
MIN.
3.25
0.60
MAX.
A1 CORNER
b
e
S
S
e
A
C
2A
E
A
(4X)aaaIND EX AREA
B
D
5
B
3 .10.25 AC B
M C
4
29
30 16
2327 25
82 62 24
21 1719
2022 18
M
10
1315 11
14 12
79 5
8 6
13
2
31
32
A
AA
AF
AH
AK
AJ
AG
AB
AD
AE
AC
L
TN
V
Y
W
U
M
P
R
N
F
H
K
J
G
B
D
E
C
AM
AL
64X
0.35
G
F
F/G 24.6024.50 24.70
102 0X
BOTTOM VIEW
TOP VIEW
SIDE VIEW
M
0.20
0.25
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
128 FPGA-DS-02053-6.3
123. 1036-Ball ftSBGA Package Dimensions in Millimeters
Cbbb
NOTES: UNLESS OTHERWISE SPECIFIED
TO EACH SIDE OF THE PACKAGE BODY.
DIMENSIO N "b" IS MEASURED AT THEMAXIMUM SOLDER BALL DIAMETER,
EXACT SHAPE AND SIZE OF THIS FEATURE
PRIMARY DATUM C AND SEATINGPLANE AR E DEFINED BY THE SPHERICAL
BILATERAL TOLERAN CE ZONE IS APPLIED
ALL DIMENSIONS ARE IN MILLIMETERS.
CROWNS OF THE SOLDER BALLS.
PARALLEL TO PRIMARY DATUM C
DIMENSIO NS AND TOLERANCES
6
5
IS OPTIONAL.
4
3
2.
1.PER ANSI Y14.5M.
A-A SECTION VIEW
Q
4
A4
--0.25Q
ddd
aaa
bbb
A4
-
-
-
0.10
- 0.20
- 0.35
- -
-A 1.80
M/N
b
e
S
A2
D/E
A1
43.00 BSC
0.65
1.00 BSC
0.50 BSC
0.50 0.80
0.55
0.98
45.00 BSC
0.90
0.40
1.10
0.70
SYMBOL
C
ddd C
NOM.MIN. MAX.
3
b
e
S
CM.30 A.10 CM
B
A
S
M
A
e
4X6
A
N
12A A
E
A
aaa
A
IDENTIFIERA1 BALL I.D.
5
(4X)
DB
C
E
G
J
L
N
R
U
W
AA
AC
AE
AG
AJ
AL
AN
AR
AU
AW
BA
BC
B
D
F
H
K
M
P
T
V
Y
AB
AD
AF
AH
AK
AM
AP
AT
AV
AY
BB
BD
-
BOTTOM VIEW TOP VIEW
SIDE VIEW
0.20-
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 129
124. 1152-Ball Organic fcBGA Package Option 1: LatticeSC/SCM40
Dimensions in Millimeters
A 1
ddd
DIMENSIONS AND TOLERANCES
TO EACH SIDE OF THE PACKAGE BODY.
DIMENSION "b" IS MEASURED AT THEMAXIMUM SOLDER BALL DIAMETER,
PRIMARY DATUM C AND SEATINGPLANE ARE DEFINED BY THE SPHERICAL
BILATERAL TOLERANCE ZONE IS APPLIED
CROWNS OF THE SOLDER BALLS.
PARALLEL TO PRIMARY DATUM C
NOTES: UNLESS OTHERWISE SPECIFIED
EXACT SHAPE AND SIZE OF THIS FEATURE
ALL DIMENSIONS ARE IN MILLIMETERS.
5
6 IS OPTIONAL.
PER ANSI Y14.5M.
4
3
2.
1.
4
- -aaa
ddd
ccc
bbb
-
-
-
-
-
0.20
-
M/N
b
e
S
D/E
B/C
A2
33.00 BSC
1.00 BSC
0.50 BSC
0.600.50 0.70
35.00 BSC
34.50
1.20 REF
34.25 34.75
SYMBOL
A
A1
ccc
C
C
bbb CC
NOM.
0.50
2.902.55
0.35
MIN.
3.25
0.65
MAX.
A1 CORNER
b
e
S
S
e
A
C
2A
E
A
(4X)aaaIND EX AREA
B
D
5
B
3 .10.25 AC B
M C
4
29
30 16
2327 25
82 62 24
21 1719
2022 18
M
10
1315 11
14 12
79 5
8 6
13
2
31
32
A
AA
AF
AH
AK
AJ
AG
AB
AD
AE
AC
L
T
NV
Y
W
U
M
P
R
N
F
H
K
J
G
B
D
E
C
AM
AL
64X
0.35
33
34
AP
AN
26.6 REF
26
.6 REF
(115 2X)
BOTTOM VIEW
TOP VIEW
SIDE VIEW
M
0.20
0.25
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
130 FPGA-DS-02053-6.3
125. 1152-Ball Organic fcBGA Package Option 2: LatticeSC/SCM80 & SC/SCM115
Dimensions in Millimeters
A 1
ddd
DIMENSIONS AND TOLERANCES
TO EACH SIDE OF THE PACKAGE BODY.
DIMENSION "b" IS MEASURED AT THEMAXIMUM SOLDER BALL DIAMETER,
PRIMARY DATUM C AND SEATINGPLANE ARE DEFINED BY THE SPHERICAL
BILATERAL TOLERANCE ZONE IS APPLIED
CROWNS OF THE SOLDER BALLS.
PARALLEL TO PRIMARY DATUM C
NOTES: UNLESS OTHERWISE SPECIFIED
EXACT SHAPE AND SIZE OF THIS FEATURE
ALL DIMENSIONS ARE IN MILLIMETERS.
5
6 IS OPTIONAL.
PER ANSI Y14.5M.
4
3
2.
1.
4
-aaa
ddd
ccc
bbb
-
-
-
-
-
0.23
-
M/N
b
e
S
D/E
B/C
A2
33.00 BSC
1.00 BSC
0.50 BSC
0.600.50 0.70
35.00 BSC
34.60
1.20 REF
34.30 34.90
SYMBOL
A
A1
ccc
C
C
bbb CC
NOM.
0.50
3.152.80
0.35
MIN.
3.50
0.65
MAX.
A1 CORNER
b
e
S
S
e
A
C
2A
E
A
(4X)aaa
INDEX AREA
B
D
5
B
3 .10
.25 AC B
M C
4
29
30 16
2327 25
82 62 24
21 1719
2022 18
M
10
1315 11
14 12
79 5
8 6
13
2
31
32
A
AA
AF
AH
AK
AJ
AG
AB
AD
AE
AC
L
T
NV
Y
W
U
M
P
R
N
F
H
K
J
G
B
D
E
C
AM
AL
64X
0.35
33
34
AP
AN
(11 52X)
6
A1 CORNERINDEX AREA
6
BOTTOM VIEW
TOP VIEW
SIDE VIEW
M
0.20
0.25
-
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 131
126. 1152-Ball Ceramic fcBGA Package Dimensions in Millimeters
A 1
ddd
DIMENSIONS AND TOLERANCES
TO EACH SIDE OF THE PACKAGE BODY.
DIMENSION "b" IS MEASURED AT THEMAXIMUM SOLDER BALL DIAMETER,
PRIMARY DATUM C AND SEATINGPLANE ARE DEFINED BY THE SPHERICAL
BILATERAL TOLERANCE ZONE IS APPLIED
CROWNS OF THE SOLDER BALLS.
PARALLEL TO PRIMARY DATUM C
NOTES: UNLESS OTHERWISE SPECIFIED
EXACT SHAPE AND SIZE OF THIS FEATURE
ALL DIMENSIONS ARE IN MILLIMETERS.
5
6 IS OPTIONAL.
PER ANSI Y14.5M.
4
3
2.
1.
4
-aaa
ddd
ccc
bbb
-
-
-
-
-
0.20
0.35
-
M/N
b
e
S
D/E
B/C
A2
33.00 BSC
1.00 BSC
0.50 BSC
0.600.50
35.00 BSC
34.00
1.40 REF
33.10
SYMBOL
A
A1
ccc
C
C
bbb CC
NOM.
0.50
4.604.00
0.30
MIN.
5.20
0.70
MAX.
4
b
e
S
S
29
30 16
2327 25
82 62 24
21 1719
2022 18
M
10
1315 11
14 12
79 5
8 6
A
AA
e 64X
AF
AH
AK
AJ
AG
AB
AD
AE
AC
A
L
T
NV
Y
W
U
M
P
R
N
F
H
K
J
G
B
D
E
C
C
2A
E
A
(4X)aaa
13
2
B
D
5
B
3 .10
.25 AC B
M C
3133
34 32
AM
AN
AP
AL
A1 CORNER
INDEX AREABOTTOM VIEWTOP VIEW
SIDE VIEW
M
34.90
0.70
0.20
0.25
-
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
132 FPGA-DS-02053-6.3
127. 1152-Ball fpBGA Package Dimensions in Millimeters
ECN
e
ddd
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICALPRIMARY DATUM C AND SEATING
EXACT SHAPE AND SIZE OF THIS FEATURE
MAXIMUM SOLDER BALL DIAMETER,DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
NOTES: UNLESS OTHERWISE SPECIFIED
6
5
IS OPTIONAL.
2.
4
3
1.PER ANSI Y14.5M.
b
3
eS
M
.10
.25M
BCC
4
1.00 BSCe
0.20
0.35
0.25
0.20ddd
ccc
bbb
aaa
-
-
-
-
-
-
-
-
0.80
30.80
0.70
0.70
2.60
MAX.
1
M/N
D/E
B/C
A2
A1
A
SYMBOL
b
S
30.3029.80
0.50 BSC
33.00 BSC
35.00 BSC
0.50 0.60
1.90
0.40
0.30
MIN.
2.25
0.60
0.50
NOM.
Cbbb
C
C
Cccc
4X6
AA 2A
S
M
A
B
1
2
aaaA1 CORNERINDEX AREA
B
(4X)
D
5
A
B
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
C
DE
FG
HJ
KL
MN
PR
TU
VW
YAA
ABAC
ADAE
AFAG
AHAJ
AKAL
AMAN
AP
Note: Depopulated ball locations areM12, M23, AC12, and AC23.
BOTTOM VIEW
TOP VIEW
SIDE VIEW
A
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 133
128. 1156-Ball fpBGA Package Dimensions in Millimeters
DIMENSIONS AND TOLERANCES
PARALLEL TO PRIMARY DATUM C
CROWNS OF THE SOLDER BALLS.
ALL DIMENSIONS ARE IN MILLIMETERS.
BILATERAL TOLERANCE ZONE IS APPLIED
PLANE ARE DEFINED BY THE SPHERICALPRIMARY DATUM C AND SEATING
EXACT SHAPE AND SIZE OF THIS FEATURE
MAXIMUM SOLDER BALL DIAMETER,DIMENSION "b" IS MEASURED AT THE
TO EACH SIDE OF THE PACKAGE BODY.
NOTES: UNLESS OTHERWISE SPECIFIED
6
5
IS OPTIONAL.
2.
4
3
1.PER ANSI Y14.5M.
1.00 BSCe
0.20
0.35
0.25
0.20ddd
ccc
bbb
aaa
-
-
-
-
-
-
-
-
0.80
30.80
0.70
0.70
2.60
MAX.
M/N
D/E
B/C
A2
A1
A
SYMBOL
b
S
30.3029.80
0.50 BSC
33.00 BSC
35.00 BSC
0.50 0.60
1.90
0.40
0.30
MIN.
2.25
0.60
0.50
NOM.
ddd4
1
Cbbb
C
C
Cccc
AA 2A
N
e
b
3
eS
M
.10
.25M
BCC
S
M
A
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
C
DE
FG
HJ
KL
MN
PR
TU
VW
YAA
ABAC
ADAE
AFAG
AHAJ
AKAL
AMAN
AP
EC
4X6
aaaA1 CORNERINDEX AREA
B
(4X)
D
5
A
B
BOTTOM VIEW
TOP VIEW
SIDE VIEW
A
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
134 FPGA-DS-02053-6.3
129. 1704-Ball Organic fcBGA Package Dimensions in Millimeters
A 1
ddd
DIMENSIONS AND TOLERANCES
TO EACH SIDE OF THE PACKAGE BODY.
DIMENSION "b" IS MEASURED AT THEMAXIMUM SOLDER BALL DIAMETER,
PRIMARY DATUM C AND SEATINGPLANE ARE DEFINED BY THE SPHERICAL
BILATERAL TOLERANCE ZONE IS APPLIED
CROWNS OF THE SOLDER BALLS.
PARALLEL TO PRIMARY DATUM C
NOTES: UNLESS OTHERWISE SPECIFIED
EXACT SHAPE AND SIZE OF THIS FEATURE
ALL DIMENSIONS ARE IN MILLIMETERS.
5
6 IS OPTIONAL.
PER ANSI Y14.5M.
4
3
2.
1.
4
-aaa
ddd
ccc
bbb
-
-
-
-
-
0.23
-
M/N
b
e
S
D/E
B/C
A2
42.50 BSC
1.00 BSC
0.50 BSC
0.600.50
42.50 BSC
42.00
1.20 REF
41.70 42.30
SYMBOL
A
A1
ccc
C
C
bbb CC
NOM.
0.50
2.902.55
0.35
MIN.
3.25
0.65
MAX.
A1 CORNER
b
e
S
S
e
A
C
2A
E
A
(4X)aaa
INDEX AREA
B
D
5
B
3 .10.25 AC B
M C
64X
0.35
4
29
30 16
2327 25
82 62 24
21 1719
2022 18
M
10
1315 11
14 12
79 5
8 6
13
2
31
32
33
34
35
36
37
38
39
40
41
42
A
AA
AF
AH
AK
AJ
AG
AB
AD
AE
AC
L
T
N
V
Y
W
U
M
P
R
N
F
H
K
J
G
B
D
E
C
AM
AL
AP
AN
AT
AR
AV
AU
AY
AW
BB
BA
(1704X)
BOTTOM VIEW
TOP VIEW
SIDE VIEW
M
0.70
0.20
0.25
-
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 135
130. 1704-Ball Ceramic fcBGA Package Dimensions in Millimeters
AV
PACKAGE BODY INCLUDES SUBSTRA TE AND LID.
bbb
DIMENSIONS AND TOLERANCES
TO EACH SIDE OF THE PACKAGE BODY.
DIMENSION "b" IS MEASURED AT THEMAXIMUM SOLDER BALL DIAMETER,
PRIMARY DATUM C AND SEATINGPLANE ARE DEF INED BY THE SPHERICAL
BILATERAL TOLERANCE ZONE IS APPLIED
CROWNS OF THE SOLDER BALLS.
PARALLEL TO PRIMARY DATUM C
NOTES: UNLESS OTHERWISE SPECIF IED
ALL DIMENSIONS ARE IN MILLIMETERS.
EXACT SHAPE AND SIZE OF THIS FEATURE
IS OPTIONAL.6
4
5
3
PER ANSI Y14.5M.
2.
1.
3
4ddd C
C
C.10 M.25 M A B
b S
ddd
ccc
-
-
-
-
0.20
0.35
2
SYMBOL
M/N
e
aaa
bbb
b
S
D/E
A2
A
A1
41.00 BSC
0.50 BSC
1.00 BSC
-
-
-
-
0.50
0.20
0.25
0.70
42.50 BSC
1.30
4.30
0.30
MIN.
4.80
0.50
NOM.
1.90
5.30
0.70
MAX.
ccc C
C
C
e
B B
AY
AW
B A
4X 6
A 1
AA
A1 BALL I.D.
IDENTIFIER
1 0
e
S
2 7
3 64 04 2
4 1 3 9
3 8
3 7 3 1
3 2
3 5
3 4
3 3
03 82
2 9
1 8
2 3
2 6
2 5
2 4
1 92 1
2 2 2 0
M
1 4
1 51 7
1 6
1 11 3
1 2
H
AC
AL
AT
AR
AU
AP
AM
AN
AG
AH
AK
AJ
AF
AD
AE
T
AA
AB
Y
N
V
W
U
M
P
R
N
L
K
J
A
F
G
E
B
D
C
17
6
9
8
3
2
5
4
aaa (4X)
5
D A
E
B
MAXIMUM OFFSET: 0.20 mm
BOTTOM VIEWTOP VIEW
SIDE VIEW
1.60
0.60
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
136 FPGA-DS-02053-6.3
Appendix A. Package Archive
32-Pin QFN (Punch Singulated) Package Dimensions in Millimeters
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 137
Technical Support Assistance Submit a technical support case through www.latticesemi.com/techsupport.
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
138 FPGA-DS-02053-6.3
Revision History
Revision 6.3, April 2021
Section Change Summary
44-Pin TQFP Package Removed (1.0 mm thick)
44-Pin LQFP Package Changed TQFP to LQFP. Removed (1.4 mm thick)
48-Pin TQFP Package Removed (1.0 mm thick)
48-Pin LQFP Package Removed (1.4 mm thick)
64-Pin LQFP Package Changed TQFP to LQFP.
100-Pin LQFP Package Option 1: MachXO2, MachXO™, ispMACH® 4000
Changed TQFP to LQFP.
144-Pin LQFP Package Changed TQFP to LQFP.
128-Pin LQFP Package Changed TQFP to LQFP.
176-Pin LQFP Package Changed TQFP to LQFP.
Revision 6.2, March 2021
Section Change Summary
— Removed 48-Pin QFN Package Option 1.
48-Pin QFN Package: L-ASC10, iCE40 Ultra, iCE40 UltraPlus, MachXO2
Removed Option 2 from heading.
Revision 6.1, January 2021
Section Change Summary
36-Ball WLCSP Package Option 2: MachXO2, MachXO3™
Added MachXO2.
36-Ball WLCSP Package Option 3: CrossLink™
Added ball labels and changed LIFMD to CrossLink.
72-Pin QFN Package Option 1: CrossLink™-NX
Indicated Pin 1.
72-Pin QFN Package Option 2: MachXO3D
Indicated Pin 1.
Multiple Restored labels that indicate top. bottom, and side views in the following packages:
36-Ball ucBGA Package
81-Ball csfBGA Package
237-Ball ftBGA Package
256-Ball ftBGA Package Option 1: ispMACH 4000, MachXO, LatticeXP2
285-Ball csfBGA Package
484-Ball caBGA Package (19 mm x 19 mm Body)
Multiple Corrected alignment of pin order labeling.
Revision 6.0, December 2020
Section Change Summary
All Updated document template.
196-Ball caBGA Package Added 196-Ball caBGA Package.
484-Ball fcBGA Package for Mach-NX
Added 484-Ball fcBGA Package: Mach™-NX.
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 139
Revision 5.9, August 2020
Section Change Summary
All Added table of contents
Changed WLCS Package to WLCSP Package in all heading.
Moved Disclaimers to second page.
30-Ball WLCSP Package Corrected the 30-Ball WLCSP Package sD and sE values. Fixed heading typo.
72-Pin WLCSP Package: CrossLink-NX
Added 72-Pin WLCSP Package: CrossLink-NX.
121-Ball csBGA Package Updated D and E dimension lines in 121-Ball csBGA Package.
Revision 5.8, August 2020
Section Change Summary
36-Ball ucBGA Package Removed Option 1 from 36-Ball ucBGA Package heading.
48-Pin LQFP Package (1.4 mm thick)
Changed 48-Pin TQFP Package (1.4 mm thick) heading to 48-Pin LQFP Package (1.4 mm thick).
Multiple Specified device(s) in the following packages:
48-Pin QFN Package Option 1: L-ASC10, iCE40 LP, iCE40 UltraPlus, MachXO2
72-Pin QFN Package Option 1: CrossLink™-NX
72-Pin QFN Package Option 2: MachXO3D
289-Ball csBGA Package (9.5 mm x 9.5 mm Body).
Added 289-Ball csBGA Package (9.5 mm x 9.5 mm Body).
Revision 5.7, November 2019
Section Change Summary
48-Pin QFN Package Option 2: L-ASC10, iCE40 Ultra, iCE40 UltraPlus, MachXO2
Updated 48-Pin QFN Package Option 2: L-ASC10, iCE40 Ultra, iCE40 UltraPlus, MachXO2. Revised values for Lead Width (b) and Bottom Pad (E2, D2).
72-Pin QFN Package Option 2: MachXO3D
Added 72-Pin QFN Package Option 2: MachXO3D.
Disclaimers Added this section.
Revision 5.6, April 2019
Section Change Summary
All Changed document ID from pkg to FPGA-DS-02053. When downloaded from the Lattice website, the PDF file name is now FPGA-DS-02053-<X-X>-Package-Diagrams.pdf (previously PackageDiagrams.pdf).
72-Pin QFN Package Added 72-Pin QFN Package.
Revision 5.5, November 2017
Section Change Summary
80-Ball ckfBGA Package Added 80-Ball ckfBGA Package.
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
140 FPGA-DS-02053-6.3
Revision 5.4, March 2017
Section Change Summary
100-Pin TQFP Package Option 1: MachXO2, MachXO™, ispMACH® 4000
Added ispMACH 4000 to 100-Pin TQFP Package Option 1: MachXO2, MachXO™, ispMACH® 4000.
121-Ball caBGA Package (9 mm x 9 mm Body)
Added 121-Ball caBGA Package (9 mm x 9 mm Body).
Revision 5.3, December 2016
Section Change Summary
32-Pin QFN Package Updated “32-Pin QFNS Package” headings to “32-Pin QFN Package”.
32-Pin QFN Package Option 3: MachXO2 SG32C
Added 32-Pin QFN Package Option 3: MachXO2 SG32C.
30-Ball WLCSP Package Added 30-Ball WLCSP Package.
48-Pin QFN Package Option 2: L-ASC10, iCE40 Ultra, iCE40 UltraPlus, MachXO2
Added iCE40 UltraPlus and MachXO2 to 48-Pin QFN Package Option 2: L-ASC10, iCE40 Ultra, iCE40 UltraPlus, MachXO2.
484-Ball caBGA Package Added 484-Ball caBGA Package.
Revision 5.2, June 2016
Section Change Summary
285-ball csfBGA Package Updated 285-ball csfBGA package outline drawing.
36-Ball WLCSP Package Option 3: LIFMD
Added 36-Ball WLCSP Package Option 3: LIFMD.
48-Pin QFN Package Option 2: L-ASC10, iCE40 Ultra, iCE40 UltraPlus, MachXO2
Fixed typo in 48-Pin QFN Package Option 2: L-ASC10, iCE40 Ultra, iCE40 UltraPlus, MachXO2.
64-Ball ucfBGA Package Added 64-Ball ucfBGA Package.
72-Pin QFN Package Option 2: MachXO3D
Added 72-Pin QFN Package Option 2: MachXO3D.
81-Ball csfBGA Package Added 81-Ball csfBGA Package.
Revision 5.1, February 2015
Section Change Summary
36-Ball ucfBGA Package: iCE40 Ultra
Added 36-Ball ucfBGA Package: iCE40 Ultra.
36-Ball ucBGA Package Option 1 Updated 36-Ball ucBGA Package heading to 36-Ball ucBGA Package Option 1.
48-Pin QFN Package Option 2: L-ASC10, iCE40 Ultra
Updated 48-Pin QFN Package Option 2: L-ASC10 heading to 48-Pin QFN Package Option 2: L-ASC10, iCE40 Ultra.
Revision 5.0, January 2015
Section Change Summary
16-Ball WLCSP Package Option 2: iCE40 UltraLite
Added 16-Ball WLCSP Package Option 2: iCE40 UltraLite.
16-Ball WLCSP Package Option 1: iCE40 LP
Updated 16-Ball WLCSP Package heading to 16-Ball WLCSP Package Option 1: iCE40 LP.
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 141
Revision 4.9, October 2014
Section Change Summary
48-Pin QFN Package Updated 48-Pin QFN Package heading and moved the section after 48-Pin QFN Package Option 1 (previously Option 2).
Revision 4.8, October 2014
Section Change Summary
— Removed 20-Ball WLCSP Package.
Revision 4.7, October 2014
Section Change Summary
121-Ball csfBGA Package Updated 121-Ball csfBGA Package. Revised M/N dimension.
Revision 4.6, September 2014
Section Change Summary
84-Pin QFN Package Updated 84-Pin QFN Package. Revised pin numbers from A36 and B27 to A37 and B28.
Revision 4.5, August 2014
Section Change Summary
16-Ball WLCSP Package Updated 16-Ball WLCSP Package. Changed second E to e in REF. column.
36-Ball WLCSP Package Option 1: iCE40 Ultra
Updated 36-Ball WLCSP Package Option 1: iCE40 Ultra heading.
36-Ball WLCSP Package Option 2: MachXO3
Added 36-Ball WLCSP Package Option 2: MachXO3.
81-Ball WLCSP Package Added 81-Ball WLCSP Package.
121-Ball csfBGA Package Added 121-Ball csfBGA Package.
256-Ball csfBGA Package Added 256-Ball csfBGA Package.
324-Ball caBGA Package Added 324-Ball caBGA Package.
324-Ball csfBGA Package Added 324-Ball csfBGA Package.
400-Ball caBGA Package Added 400-Ball caBGA Package.
84-Pin QFN Package Updated 84-Pin QFN Package. Revised dimension “b” maximum value.
256-Ball ftBGA Package Option 1: ispMACH 4000, MachXO, LatticeXP2
Updated 256-Ball ftBGA Package Option 1: ispMACH 4000, MachXO, LatticeXP2. Revised dimension “A” values.
Revision 4.4, June 2014
Section Change Summary
48-Pin QFN Package Updated 48-Pin QFNS Package to 48-Pin QFN Package.
48-Pin QFN Package Option 2 Added 48-Pin QFN Package Option 2.
49-Ball WLCSP Package Added 49-Ball WLCSP Package.
237-Ball ftBGA Package Added 237-Ball ftBGA Package.
285-Ball csfBGA Package Added 285-Ball csfBGA Package.
20-Ball WLCSP Package Added 20-Ball WLCSP Package.
36-Ball WLCSP Package Added 36-Ball WLCSP Package.
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
142 FPGA-DS-02053-6.3
Revision 4.3, March 2014
Section Change Summary
All Restored references to indicate top. bottom, and side views.
381-Ball caBGA Package Added 381-Ball caBGA Package.
554-Ball caBGA Package Added 554-Ball caBGA Package.
756-Ball caBGA Package Added 756-Ball caBGA Package.
Revision 4.2, December 2013
Section Change Summary
100-Pin TQFP Package Option 1: MachXO2, MachXO
Added "1" and "N" characters to 100-Pin TQFP Package Option 1: MachXO2, MachXO diagram (Top View).
Revision 4.1, September 2013
Section Change Summary
16-ball WLCSP Package Added 16-ball WLCSP package.
25-Ball WLCSP Package (0.40 mm Pitch)
Revised 25-Ball WLCSP Package title to 25-Ball WLCSP Package (0.40mm Pitch).
25-Ball WLCSP Package (0.35 mm Pitch)
Added 25-Ball WLCSP Package (0.35mm Pitch).
All Added references to indicate top. bottom, and side views.
Revision 4.0, August 2013
Section Change Summary
144-pin TQFP Package Revised 144-pin TQFP package diagram.
Revision 3.9, February 2013
Section Change Summary
184-ball csBGA Package. Added 184-ball csBGA package.
Revision 3.8, November 2012
Section Change Summary
32-pin QFNS Option 1 Added iCE40 to the list of applicable products for the 32-pin QFNS Option 1 package.
Revision 3.7, October 2012
Section Change Summary
324-ball ftBGA Package Revised 324-ball ftBGA package drawing.
Revision 3.6, September 2012
Section Change Summary
iCE40 100-Pin VQFP Package Option 2
Nomenclature change – “iCE40 100-Pin TQFP Package Option 2” changed to “iCE40 100-Pin VQFP Package Option 2”.
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02053-6.3 143
Revision 3.5, August 2012
Section Change Summary
Multiple Added 36-ball ucBGA, 49-ball ucBGA, 81-ball ucBGA, 81-ball csBGA, 84-pin QFN, 100-pin TQFP Option 2, 121-ball csBGA, 121-ball ucBGA, 132-ball csBGA Option 2, 196-ball csBGA, 225-ball ucBGA, 284-ball csBGA packages.
Revision 3.4, July 2012
Section Change Summary
676-ball fcBGA Package Added 676-ball fcBGA package.
Revision 3.3, March 2012
Section Change Summary
Appendix A Added new 32-Pin QFNS Package Option 2 for MachXO2. Moved 32-pin QFN (punch singulated) package drawing to new Package Archive Appendix.
Revision 3.2, February 2012
Section Change Summary
All Updated document with new corporate logo.
Revision 3.1, December 2011
Section Change Summary
Multiple Updated WLCSP package offering.
Revision 3.0, October 2011
Section Change Summary
Multiple Added 49-ball WLCSP package and updated 25-ball WLCSP package.
Revision 2.9, October 2011
Section Change Summary
328-ball csBGA Package Added 328-ball csBGA package.
Revision 2.8, July 2011
Section Change Summary
Multiple Included revised diagrams for the following packages: 56-ball csBGA, 100-ball csBGA and 132-ball csBGA. Added new 256-ball ftBGA Option 3 package.
Revision 2.7, May 2011
Section Change Summary
256 ftBGA Option 1 Package Added MachXO2 to the list of applicable products for the 256 ftBGA Option 1 package outline.
Revision 2.6, November 2010
Section Change Summary
Multiple Added 25-ball WLCSP and 332-ball caBGA package drawings. Revised 100-pin PQFP, 120-pin PQFP, 128-pin PQFP, 160-pin PQFP and 208-pin PQFP package drawings. Removed obsolete packages including 144-, 240- and 304-pin PQFP packages.
Package Diagrams Data Sheet
© 2007-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
144 FPGA-DS-02053-6.3
Revision 2.5, October 2010
Section Change Summary
208-ball ftBGA Package Added 208-ball ftBGA package.
Revision 2.4, September 2010
Section Change Summary
Multiple Revised maximum coplanarity values on Organic 1152 Flip Chip BGA – Option 2 and on Organic 1704 Flip Chip BGA from 0.20 mm to 0.23 mm.
Revision 2.3, March 2010
Section Change Summary
Multiple Added new 1020-ball Organic fcBGA rev.2, 1152-ball Organic fcBGA, and 1704-ball Organic fcBGA package drawings. Removed obsolete 492-Ball BGA package.
Revision 2.2, February 2010
Section Change Summary
256-Ball caBGA Package Revised 256-ball caBGA nominal solder ball diameter from 0.5 mm to 0.45 mm to better match actual dimension.
Revision 2.1, December 2009
Section Change Summary
256-ball caBGA Package Revised 256-ball caBGA package to specify correct JEDEC reference number.
Revision 2.0, May 2009
Section Change Summary
Multiple Added new 256-ball caBGA and 256-ball ftBGA (Option A) packages.
Revision 1.9, April 2009
Section Change Summary
Multiple Added 24-pin QFNS package diagram. Removed discontinued and obsolete packages (16 SOIC, 20 SOIC, 24 SOIC, 28 SOIC, 16 PDIP, 240 MQFP, 269 fcBGA, 304 MQFP, 600 SBGA).
Revision 1.8, December 2008
Section Change Summary
Multiple Added 32-pin QFNS, 48-pin QFNS and 64-pin QFNS package diagrams.
Revision 1.7, November 2008
Section Change Summary
Multiple Added 64-ball ucBGA and 132-ball ucBGA package diagrams.
Revision 1.6, April 2008
Section Change Summary
Multiple Added 64-ball csBGA and 144-ball csBGA package diagrams.
Package Diagrams Data Sheet
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FPGA-DS-02053-6.3 145
Revision 1.5, November 2007
Section Change Summary
1152-ball fpBGA Package Added 1152-ball fpBGA package diagram.
Revision 1.4, October 2007
Section Change Summary
1036 ftSBGA Package Revised 1036 ftSBGA package diagram. Removed 1036 fpSBGA.
Revision 1.3, June 2007
Section Change Summary
1036 ftSBGA Package Added 1036 ftSBGA package diagram.
Revision 1.2, February 2007
Section Change Summary
1704 fcBGA Package Revised 1704 fcBGA package drawing: removed lid dimension, clarified package body dimension as the combination of substrate and lid.
Revision 1.1, January 2007
Section Change Summary
Multiple Added Marking Orientation text for all TQFP packages (1.0 mm and 1.4 mm thick).
Revision 1.0, January 2007
Section Change Summary
Multiple Added 64-pin TQFP and 1704-ball fcBGA package diagrams.