DDR SDRAM Memory Interface. Quick Start Training Agenda Why DDR? DDR vs. SDR Understanding DDR SDRAM...

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DDR SDRAM Memory Interface

Quick Start Training

Agenda

• Why DDR?• DDR vs. SDR• Understanding DDR SDRAM

– Bus timing

• CoolRunner-II and DDR SDRAM demo board• CoolRunner-II DDR SDRAM design

Why DDR?

• DDR = Double Data Rate• Provides ability to read or write two pieces of information

in each clock cycle• Doubles the bandwidth of the device without increasing

the clock speed or bus width

DDR vs. SDR Functionality

• Memory core of DDR and SDR are the same– Addressing scheme– Command control interface– Memory bank array structure– Refresh requirements

• The main difference is in the data interface:– SDR is fully synchronous (posedge of clk)– DDR is true source-synchronous meaning data is captured

twice per clock cycle, with a bi-directional data strobe (DQS)

Strobe-Based Data Bus

• To allow for higher data rates, data strobe signals were added to DDR devices:– DDR data strobes (DQS) are non-free-running signals

that are driven by the device which is driving the data signals

• Controller drives DQS for WRITE operations• DDR SDRAM drives DQS for READ operations

DDR Enhancements

• DDR utilizes a differential pair for the system clock (CLK and CLK#)

• Data is transmitted on both positive and negative edges of the clock• DDR devices incorporate an on-chip delay locked loop (DLL) • Data strobes are added to improve data capture reliability• SSTL_2 signaling techniques are used• DDR utilizes a 2n-prefetch architecture

– Internal data bus is twice the size of external data bus

SDR vs. DDR Summary

Source-Synchronous

SynchronousArchitecture2x Clock1x ClockData RateSSTL_2LVTTLSignal Interface

2.5V3.3VVDD and VDDQ

YesNoVrefYesNoCK# (System Clock)YesNoDQS (Data Strobe)YesNoDM (Data Mask)NoYesDQM

DDRSDRParameter

CoolRunner-II DDR SDRAM Evaluation Board

CR-II / DDR Demo Board

LP3964

LP3964 2.5 V

Xilinx CR-II

XC2C256

Micron 128 Mb DDR MT46V16M8

Micro Linear ML6554

Bus Terminator

VREF Out

VTT Out

2.5V/1.8V Regulator VTT & VREF Generation

CR-II & DDR SDRAM

SSTL_2 Termination

+-VREF

ZO = 50 Ohm

+-VREF

ZO = 50 Ohm

VTT VTT

CR-II / DDR Termination

ZO = 50 Ohm

VTT VTT

VTT 128 Mb DDR SDRAM

CPLD Design

• DDR SDRAM controller design fits into a XC2C256 (~50% utilization for DDR)

• Includes the following:– Initialization state machine– DDR controller– Refresh logic– Test read/write logic (LFSR)– Board interface

CPLD Block Diagram

DDR Controller

State Machine

ddr_dq

ddr_dqs

ddr_cke

ddr_clk

ddr_clkn

ddr_csddr_rasddr_cas

ddr_we

ddr_ba

Initialization / Test Logic State

Machine

int_cmd

int_data

int_addr

Refresh Logic

rfsh_flag

Board Logic

8-bit LFSR

DDR CommandsNOP Deselect DDR SDRAM. No new commands

executed.LOAD MODE REGISTER Defines operating mode of SDRAM.

ACTIVE Opens row in specified bank for access.

READ Initiates burst read operation.

WRITE Initiates burst write operation.

BURST TERMINATE Terminates a burst read.

PRECHARGE Deactivates open row in specified bank.

AUTO REFRESH Retains data in SDRAM.

SDRAM Addressing

• 23-bit system address bus = 128 MB memory• SDRAM data is organized into banks• Each bit location is specified with a row and column address

22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Load Mode Register Data

Column AddressRow AddressBank

Address

Initialization SequenceWait for stable power

& clock inputs

Precharge All Addresses

Extended Mode Register Write (Enable DLL)

Mode Register Write (Reset DLL)

Wait 200 Clock Cycles

Precharge All Addresses

Execute 2 Auto Refresh Commands

Mode Register Write (Set CAS & burst)

Controller State Machine

ACTIVE

READWRITE

WR_DATA

AUTO_RFSPRECHARGE

LOAD_MR

CAS_LAT

RD_DATA

BRST_TERM

cnt < BURST_LEN

cnt < CAS_LAT

cmd = BURST_TERM

cmd = PRECHARGE

cmd = LOAD MRcmd = READ or WRITE

cmd = AUTO_REFRESH

DDR Clock Requirements

DDR Clock Generation

ddr_clkTQ

sys_clk

RST3.3V IN GCK

OBUF 2.5V OUT

ddr_clknTQ

sys_clk

3.3V IN GCKOBUF 2.5V OUT

DDR Clock Timing

7.5 ns DDR Clock Period 15 ns(133 MHz) (66.67 MHz)

sys_clk

ddr_clktCO = 5 ns

ddr_clkn

T = 7.5 ns

T = 15 ns

DDR Clock Generation (TCO)

ddr_clk

sys_clk

ddr_clkn

DDR Clock Generation (VMP)

ddr_clk

sys_clk

ddr_clkn

Bank/Row Activation

• Prior to a READ/WRITE operation the specific bank/row must be activated

Typical Write Burst

• DQS generated by CPLD• DQS must be center aligned with DQ

Typical Read Burst

• DQS is edge aligned to DQ• Read interrupted with BURST TERMINATE command

Data Valid Read Window

sys_clk

ddr_clk

ddr_clkn

ddr_dq

ddr_dqs

DVW DVW

DVW = tCK/2 - tAC(max) + tAC(min) = 7.5 ns - (0.75 ns) + (-0.75 ns) = 6 ns

CPLD captures data

Data Valid Window

ddr_dqs

ddr_dq(2)

ddr_dq(1)

ddr_dq(0)

Read & Write (Burst 2)

ddr_clk

ddr_dqs

ddr_dq(0)

ddr_dq(1)

ddr_dqs

ddr_dq(0)

ddr_clkn

ddr_clk

ddr_dqs

ddr_dq(0)

ddr_clkn

ddr_clk

Precharge Operation

• Precharge deactivates the open row in a particular bank or all banks

• After a precharge, the specific row address must be activated with an ACTIVE command prior to use

• Auto PRECHARGE : A10 specifies precharge after current READ/WRITE operation

• Self PRECHARGE: separate command (must wait tRP)

Refresh Requirements

• Refresh is required at intervals of 15.625 µs– Only one refresh command is required

• Option to issue up to 8 refresh commands every 140.6 µs

DDR SDRAM Vendors

• Memory vendors providing DDR SDRAM: – Micron, Infineon, Cypress, Samsung, Hitachi, Fujitsu, Hyundai,

IDT, Mitsubishi, SiberCore, Toshiba...

Conclusion

• Reference board works up to 100 MHz on DDR SDRAM• Current DDR design can be modified for SDR SDRAM

applications• Check out application note XAPP384 on DDR &

CoolRunner-II reference design

Demo Slides

ddr_dq[7:0]

8-bit LFSR

Upper Byte Lower Byteint_data[15:0]

Burst = 2Test Control Logic

DDR Control Logic

DemoData wrote to DDR Data read from DDR

MSB … LSB MSB … LSB

Appendix

SDRAM Core

Internal Data Bus

DQM (SDR only)

Col0 (DDR only)

SDR Interface

DDR Interface

SSTL_2 Signaling

DDR Write Logic

ddr_dq[7:0]

ddr_dqs

ddr_write_en

DualEdge

ddr_dqs_t

ddr_clk

DualEdge

int_data(TEST SM Logic)

ddr_clk

DDR SM Logic

ddr_clk

8-bit LFSRD

Qlfsr_clk(TEST SM

Logic)

DDR Read Logic

ddr_dq[7:0] DQ

sys_clk

ddr_read_en

DualEdge

DDR SM Logic

ddr_clk

int_data_rd[15:8]

LED Board Logic

ddr_dq[7:0] DQ

sys_clk

int_data_rd[7:0]

ddr_dqs

CLK/CLK# Generation

DDR SDRAM Memory Interface. Quick Start Training Agenda Why DDR? DDR vs. SDR Understanding DDR SDRAM...

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