Design Flow

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IntroductionTypes of integrated circuits

Moore´s lawLayout – circuit - symbol

IC Design flow

Digital VLSI Design

Integrated Circuits (IC)

Standard - IC ASICApplication Specific IC

• Low Cost

• Proven (reliable)

• Available off-the-Shelf

• Many Sources

• High Performance

• Replace many IC:s

Integrated Circuits (IC)

Standard - IC

Programmable

Semi-custom

Cell-based (CBIC)

2 types: Standard-cell & gate arrayCells and mask

layers are customized

Full Custom

ASICApplication Specific IC

“Fuse” or programmable

memory

Intel 4004 Microprocessor

19711000 transistors0.1 MHz operation

The Full Custom Approach

Transition to Automation and Regular Structures

Intel 4004 (Intel 4004 (‘‘71)71)Intel 8080Intel 8080 Intel 8085Intel 8085

Intel 8286Intel 8286 Intel 8486Intel 8486Courtesy Intel

Moore´s law

Gordon Moore, one of the founders of Intel.

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.

He made a prediction that semiconductor technology will double its effectiveness every 18 months

Moore: ”Integrated circuits will lead to such wonders as home computers...and personal portable communications equipment.”

Moore´s law

Moore’s law:the number of transistors per chip doubles every 18 monthsG. Moore, ”Cramming more components onto integrated circuits”, Electronics, vol. 38, no. 8, 1965.

Moore´s law

Semi-custom approach

Routing channel requirements arereduced by presenceof more interconnectlayers

Functionalmodule(RAM,multiplier, …)

Routingchannel

Logic cellFeedthrough cellR

Standard Cell — Example

[Brodersen92]

All cells in the celllibrary are of thesame standard height

In this relatively olddesign cell rows and routing channels areclearly distinguishable

Standard Cell - Example

3-input NAND cell(from ST Microelectronics):C = Load capacitanceT = input rise/fall time

Simple delay formula:delay=intrinsic+fanout(C)+input(T)

Slow Fast

Place & Route (2-3 Met. Lay.)Placement of library cells Routing cell

LeafCell

Routing channel

Routing

Tools:

- Placer

- Router

Place & Route (3-10 Met. Lay.)Placement of library cells Routing

No Routing channels needed

LeafCell

Standard Cell – The New Generation

Cell-structurehidden underinterconnect layers

Place & Route”Automatic” often flat

Structured & hierarchical

Field-Programmable Gate Arrays

• Based on Configurable Logic Blocks (CLB)CLB CLB CLB CLBCLB CLB CLB

CLB CLB CLB CLBCLB CLB CLB

Field-Programmable Gate Arrays

• … and programmable switch matricesCLB CLB CLB CLBCLB CLB CLB

CLB CLB CLB CLBCLB CLB CLB

Gajski Y-Chart

Design Abstraction Levels

DEVICE

CIRCUIT

MODULE

SYSTEM

Design Flow

Circuit representation

• Layout– Boxes, graphical or coordinate based list– Abstract (subset)

• Schematic– graphical or component based netlist

• Symbol– For simulation and hierarchical schematics

Layout view

(CIF file 11-Mar-2003);DS 1 1 1;9 INVERTER;L prBoundary;B 450 1500 225,750;L CONT;B 40 40 100,340;L DIFF; B 100 240 320,420;L POLY1;B 80 35 190,425;L MET1;B 60 360 70,800;B 450 200 225,100;

Cell name

Cell size

Length Width Xcenter,Ycenter

Physical

Symbolic

Text based (0.35um tech.)

Layout view

Cadence Virtuoso tool

Schematic View/Netlist

Circuit Chart Schematic view (Graphical netlist)

Netlist(List-based schematic)

*nand gate* d g s bM1 2 1 0 0 NMOS L=0.35U W=0.6UM2 4 3 2 0 NMOS L=0.35U W=0.6UM3 4 3 5 5 PMOS L=0.35U W=0.9UM4 4 1 5 5 PMOS L=0.35U W=0.9UC1 3 0 1E-14

Cadence schematic capture tool

Symbol view

For simulation test bench & for hierarchical schematics

Capacitor (load)

Signal source

A symbol is introduced to represent the gate at the next level

Design Flow at the circuit level

Simulation

Extraction

Schematic

Layout

Post Lay Mod

DRC = Design Rule Checker

LVS = Layout Versus Schematic

Design Flow

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