Design of Mixed-Signal Microsystems in Nanometer CMOS · Design of Mixed-Signal Microsystems in...

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2012 BES Neutron and Photon Detector Workshop

Design of Mixed-Signal Microsystems in Nanometer CMOS

Carl Grace

Lawrence Berkeley National Laboratory

August 2, 2012 DOE BES Neutron and Photon Detector Workshop

Introduction •  Common themes in emerging detector requirements:

–  Need to capture dynamic processes –  More channels, higher speed, lower power/channel, decreased

system footprint, severe cost constraints

•  Integrated mixed-signal readout a must •  Example: Fast soft X-ray cameras over last 10 years

Conventional CCD Today (FCCD) Tomorrow

(cp-CCD)

1000X increase in readout channels (for Mpixel square sensor)

Integrated readout required to deal with huge amounts of data

SUBTITLE HERE IF NECESSARY

Why nanometer CMOS?

Nanometer CMOS is an enabling technology for future imaging and particle detection systems

•  Increased transistor density –  Enables increased channel/pixel count

and new functionality –  New, more digital–centric approaches to

design possible

•  Vastly improved performance

•  Lower power for a given level of functionality

•  Cheaper on a functionality basis

SMALLER, FASTER, CHEAPER

Performance Figure of Merit gm/I * ft

Opportunities and Challenges

K. Kundert

Mentor Graphics

Design Rules multiplying as processes shrink

Current design techniques inappropriate for system-level mixed-signal ASICs

IC Development Infrastructure

Software Infrastructure

The days of debugging a chip with an oscilloscope and a function generator are over

•  Design entry (schematic and physical layout design)

•  Simulation (analog, digital, mixed-mode)

•  Synthesis •  Automatic Place-and-Route •  DRC/LVS verification •  FPGA firmware development

environment •  Board development suite •  Test framework, instrument control •  Design-space exploration (MATLAB or

similar)

Required Team Competencies •  Transistor-level analog and mixed

-signal design •  Digital RTL development •  Physical Design and Verification •  System-level Validation •  Analog/Digital co-simulation •  Behavioral Modeling •  Project management •  Board-level circuit design •  FPGA firmware development •  Teststand software development •  Advanced test execution and debug

Designing a nanometer mixed-signal ASIC requires a competent and experienced team

Platform-Based Design •  Most readout systems look broadly

similar •  A platform can embody these

commonalities •  Individual readout ICs are

instances of the common platform •  Dramatic improvements in design

productivity and tractability •  Enables small teams to complete

projects that would be impossible using an ad-hoc approach

A. Sangiovanni Vincentelli, UC Berkeley

Leads directly to improved top-down design methodologies

Sow once Reap many times Each new chip is a platform instance instead of a scratch design

Platform-Based Design •  Platform is an integrated system designed for modification and

extensibility •  Choose flexible macros for reuse e.g. use Pipelined ADC over SAR •  Process, block interfaces, and characteristics standardized

–  e.g. 65nm CMOS, pitch matching, electrical interfaces, biasing requirements

•  Platform includes set of pin-accurate functional models in Verilog-AMS –  Models allow rapid development of platform instances

Enables digital-centric design approach lower cost and higher performance

Verilog-AMS

Verilog Verilog-A

Verilog-AMS allows full system simulation (analog + digital)

Analog Challenges in Nanometer CMOS

B. Murmann, Stanford University •  Low supply voltage •  Low device gain Analog design is hard! •  But… cheap and fast transistors •  Leverage cheap digital circuits to assist analog circuits

Logic Energy over Time

~1000x

90nm 65nm

B. Murmann, Stanford University

ADCs versus Logic in 1997/1998

Digital assistance affordable only for high-resolution ΔΣ

(decimation filtering)

ADCs versus Logic in 2012

~1000x

ADCs versus Logic in 2012

~1000x

Today, it is feasible to use digital signal processing to assist moderate resolution

Digital-Centric System Design (optical comms)

Agazzi, et al. 2008 ISSCC

Challenging analog design requires large design team and multiple silicon spins

Digital-centric design has vastly improved system performance, functional on first silicon

Well-understood digital circuits can compensate for analog shortcomings

50X performance improvement due to digital-centric design

K. Kundert

155 Mb/s data rate 10 Gb/s data rate

HIPPO: High-Speed Image Pre-Processor with Oversampling

16-channel prototype fabricated in 2011

HIPPO Platform in 65nm CMOS

Front end specific to initial application: Column-Parallel CCD readout for soft X-rays

Back end more general for signal acquisition and data conversion

Functional blocks developed with standard interfaces and Verilog-AMS models to allow accelerated redeployment

Digital-Centric HIPPO Platform Payoff

Low-accuracy analog system plus digital assistance = high-accuracy mixed-signal system

Result to be presented at NSS 2012

HIPPO ADC designed for good noise performance with relaxed linearity

POM – an instance of the HIPPO platform

21,600 gas-filled straws. Each straw has dedicated channel of electronics. Example of BES-supported platform development enabling accelerated development of high-performance readout IC for HEP

Mu2e tracker - Fermilab Processor of Muon Decays

Mu2e: experiment to observe neutinoless muon decay

POM Behavioral Simulation (enabled by Platform-Based Design methodology)

18 19 20 21 22 More

TDC electron hits (mid-straw)

135 136 137 138 139 140 141 142 143 144 145 More

TDC electron hits (edge of longest straw)

•  Functional circuit blocks modeled with Verilog-AMS •  Input straw pulses provided by FNAL using GARFIELD •  System-level simulation conducted before detailed design

Spreading due to dispersion in straw model

THIS IS TOP-DOWN DESIGN

POM Design Reuse

BLOCK REUSE Block Development time reduction

ADC Core structure adapted from silicon-proven HIPPO. Modified to lower power and area.

Shaper Silicon-proven op amp architecture ported from HIPPO.

S2DIFF S2DIFF architecture adapted from Multiplying DAC circuit used in HIPPO ADC.

LVDS Silicon-proven LVDS driver and receiver from HIPPO reused in POM.

Masterbias Silicon-proven current bias generation and distribution block from HIPPO reused in POM.

Configuration Register

Silicon-proven, radiation-tolerant configuration register from HIPPO reused in POM.

Standard Cells Standard cell library used in HIPPO reused in POM. 100%

Pads Pad library used in HIPPO reused in POM. 75% (estimate)

Digital Backend Experience gained in HIPPO synthesis and place-and-route cycle greatly reduced development time.

2012 BES Neutron and Photon Detector Workshop 21

Design Reuse example Pipelined ADC

HIPPO ADC (2011): 12-bit, 80 MSPS, 50 mW

POM ADC (2012): 8-bit, 65 MSPS, 3 mW

80% shorter development time due to HIPPO platform

The Virtuous Circle of Platform-Based Design

•  Refinements made to POM ADC and improved digital expertise will be directly applied to HIPPO 2, a planned 128-channel readout IC to instrument cp-CCD image sensors.

•  Platform-based design allows each project to be used as a springboard to improve the performance and lower the cost of the next project

HIPPO POM HIPPO 2

Platform-Based Design as enabling technology

POM would have required severe compromises in functionality or performance without Platform-Based Design

Highly leveraged from HIPPO development

Conclusion •  Science requirements demand increases in detector

channel count and performance •  To meet these needs we need readout ICs that are:

–  Platform-Based –  Digital Centric –  Developed using a top-down methodology

•  These are enabling technologies. They represent an industry-proven path to improve the productivity and reach of existing design teams

•  Development costs can be spread across projects and application domains for maximum impact

Design of Mixed-Signal Microsystems in Nanometer CMOS · Design of Mixed-Signal Microsystems in...

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