Design-Technology Co-Optimization for 5nm Node and · PDF fileDesign-Technology...

transcript

Victor Moroz

July 12, 2016

Semicon West 2016

Design-Technology Co-Optimization

for 5nm Node and Beyond

Why Scaling?

When What scales? When does it end?

1965Moore’s Law (Fairchild):

Double transistor density every couple of years

• By 2043, there will be 1 atom per transistor

• But you can go up (3D IC)

• Great for planning and aligning the industry

Claasen’s Law (Philips CEO):

Usefulness = log(Technology), or:

Technology = exp(Usefulness)

Forever?

Koomey’s Law (Stanford Professor):

"at a fixed computing load, the amount of battery you need will fall by a factor of two every year and a half.“

• By the second law of thermodynamics and Landauer's principle, irreversible computing cannot continue to be made more energy efficient forever. As of 2011, computers have a computing efficiency of about 0.00001%. The Landauer bound will be reached in 2048. Thus, after 2048, the law could no longer hold.

• With reversible computing, however, Landauer's principle is not applicable. With reversible computing, though, computational efficiency is still bounded by the Margolus–Levitin theorem. By the theorem, Koomey's law has the potential to be valid for about 125 years.

nsisto

Existing Early Design Rule Evaluation

GDS: Maxwell

or Laker

Litho:

Sentaurus

Design rule

Existing Early Design Rule Evaluation

GDS: Maxwell

or Laker

Litho:

Sentaurus

Design rule

• Missing process proximity effects outside of litho

• Missing process interaction with design

• Gives design window, but no guidance within the window

Proposed DTCO: Pre-Si PowerPerformanceArea Evaluation

GDS: Maxwell

or Laker

Process T Time Etch

Process1 480 C 25 min 12 nm

Litho:

Sentaurus

3D structure:

Process

Explorer

Switching

behavior:

Design rule

Design ruleP

rocess c

onditio

nDesign rule

cess c

onditio

GDS: Maxwell

or Laker

Process T Time Etch

Litho:

Sentaurus

3D structure:

Process

Explorer

Switching

behavior:

Design rule

Design ruleP

rocess c

onditio

nDesign rule

cess c

onditio

GDS: Maxwell

or Laker

Process T Time Etch

Litho:

Sentaurus

3D structure:

Process

Explorer

Switching

behavior:

Design rule

Design ruleP

rocess c

onditio

nDesign rule

cess c

onditio

• Provides quick PPA estimate

• Includes process effects

• Enables process-design feedback

• Reasonable TAT

2-Input NAND Standard Library Cell

• 2-input NAND library cell with a load of:

– Fan-out of 2

– Metal wire that is 70 metal pitches long

• Cload = 2*Cpin + Cwire

• Cwire = 0.34 fF

• Typical Cload is 1 fF to 2 fF

Layout: 5nm 2-NAND Cell, 9 Tracks Tall

contact

M2 (PWR)

3 Gate Pitches wide

M2 (GND)

GP = 32nmMP = 24nmFP = 18nm

3D Library Cell in Process Explorer

Transistors

Power-Performance-Area Evaluation in TCAD

• Transient analysis of the switching behavior in Sentaurus-Device

• Time delay is the averaged pull-up and pull-down delays

• Rigorous current flow analysis in the 3D structure

0 2E-11 4E-11 6E-11 8E-11 1E-10

Time, s

Low_ROutput

3D current crowding

0 5 10 15 20 25

Switching delay, ps

FF 2x, low MG R

NW 2x2

NW 2x1

NW 1x2

5nm Technology Evaluation: PowerPerformanceArea @TCAD

Load: Fan-out of 2 plus 70 pitches long BEOL wire

3D current flow in TCAD

2-NAND logic cell

Reference 2-fin FF cell

0 5 10 15 20 25

Switching delay, ps

FF 2x, low MG R

NW 2x2

NW 2x1

NW 1x2

2-NAND logic cell

Low MG resistance:10% power reduction

Insight Into Metal Gate Resistance Effect

• Due to metal resistance, the input signal takes time to get to the fins

• Different parts of the gate experience different biases at any given time

• This is a new effect, due to the lack of space inside MG for tungsten fill, so MG resistivity increases from ~20 mW.cm to ~200 mW.cm

• It gets worse for 3 and 4 fins

2D cut across the gate

PMOS Gate

NMOS Gate

NMOS fins

PMOS fins

2-NAND cell

Electrostatic potential map

Input signal arrives here first

0 5 10 15 20 25

Switching delay, ps

FF 2x, low MG R

NW 2x2

NW 2x1

NW 1x2

2-NAND logic cell

Fin depopulation from 2 to 1:30% power reduction

0 5 10 15 20 25

Switching delay, ps

FF 2x, low MG R

NW 2x2

NW 2x1

NW 1x2

2-NAND logic cell

Nano-wires: 44% better

0 5 10 15 20 25

Switching delay, ps

FF 2x, low MG R

NW 2x2

NW 2x1

NW 1x2

2-NAND logic cell

Nano-wire depopulation: 50% power reduction

0 5 10 15 20 25

Switching delay, ps

FF 2x, low MG R

NW 2x2

NW 2x1

NW 1x2

2-NAND logic cell

FinFET

2 fins

0 5 10 15 20 25

Switching delay, ps

FF 2x, low MG R

NW 2x2

NW 2x1

NW 1x2

2-NAND logic cell

FinFET

2 fins

FF 2xFF 1x

NW 2x2NW 2x1

NW 1x2

0.54 0.54

Cpin, fF

Ion, normalized

0 5 10 15 20 25

Switching delay, ps

FF 2x, low MG R

NW 2x2

NW 2x1

NW 1x2

2-NAND logic cell

FinFET

2 fins

FF 2xFF 1x

NW 2x2NW 2x1

NW 1x2

0.54 0.54

Cpin, fF

Ion, normalized50%

0 5 10 15 20 25

Switching delay, ps

FF 2x, low MG R

NW 2x2

NW 2x1

NW 1x2

2-NAND logic cell

FinFET

2 fins

FF 2xFF 1x

NW 2x2NW 2x1

NW 1x2

0.54 0.54

Cpin, fF

Ion, normalized

0 5 10 15 20 25

Switching delay, ps

FF 2x, low MG R

NW 2x2

NW 2x1

NW 1x2

2-NAND logic cell

FinFET

2 fins

FF 2xFF 1x

NW 2x2NW 2x1

NW 1x2

0.54 0.54

Cpin, fF

Ion, normalized

•MOL capacitance engineering rules!

Why Variability is Important

• Technology A

Design spec:

Nominal – 3s

Nominal

Performance A• What matters is

nominal – 3s

• Therefore variability affects chip area

Why Variability is Important

• Technology A

• Technology B

NominalDesign spec:

Nominal – 3s

Nominal

Performance B

Performance A• What matters is

nominal – 3s

• Therefore variability affects chip area

• There is no “good enough” variability –the target is zero!

Fin Depopulation Adds Pressure to Variability Scaling

sVt ~ 1 / sqrt(# of fins)

Fin Depopulation Adds Pressure to Variability Scaling

sVt ~ 1 / sqrt(# of fins)

• Other considerations:

• Electromigration

• Power density

• Fin pitch

Variability Evolution: Planar to FinFET

n-poly

L CD&LER

W CD&LER

fin height

sigma pVt

sigma nVt

• Encouraging trend

• Several “reset buttons”

• There is nothing that can be done to eliminate RDF, so it kept getting worse for planar

• The FinFETs are more sensitive to geometry, which can be better controlled by the equipment

V. Moroz, WMED 2013

Variability Evolution: Planar to FinFET

n-poly

L CD&LER

W CD&LER

fin height

sigma pVt

sigma nVt

V. Moroz, WMED 2013

Measured data from S. Natarajan et al., IEDM 2014

The lower Sigma Vt values here are due to low Vt process

Planar to FinFET Transition

• FinFETs improve variability

• Planar MOSFETs suffered from RDF

• FinFETs are insensitive to channel doping RDF

110100

Technology node, nm

Variability Evolution

Planar FinFET NW

HKMG Grains Introduce Gate Workfunction Variation

• At 10nm and 7nm nodes, HKMG becomes the dominant variability mechanism

• Introduction of amorphous MG at 7nm would solve this issue

110100

Technology node, nm

Variability EvolutionTotal

Geometry

• Planar MOSFETs are insensitive to geometry

• FinFETs and NW are more sensitive to geometry

• NW are less sensitive to L than FinFET, but more sensitive to W

• This data is based on 1 geometry sigma staying at 5% of CD0

110100

Technology node, nm

Variability Evolution Total

Geometry

RDF (Random Dopant Fluctuations)

• Planar MOSFETs suffered from RDF

• FinFETs are insensitive to channel doping RDF

110100

Technology node, nm

Variability Evolution Total

Geometry

FinFET to Nanowire Transition: Counting Particles

• NW variability depends on how many S/D dopants get into the channel

110100

Technology node, nm

Variability EvolutionTotal

Geometry

0 dopants

1 dopant

Summary

• 5nm technology has multiple trade-offs in transistor architecture and MOL RC that require holistic engineering

• Ideal variability is zero, and fin depopulation adds even more pressure

• Several key factors suggest fin depopulation towards 1 fin and beyond (i.e. fractional fins a.k.a. nano-wires):

– PPA

–MOL RC

–Electrostatics (DIBL)

–Electromigration and power density

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