Determinism,Electricity, and Intuitionism Gérard Berry Collège de France Algorithms, Machines,...

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Determinism,Electricity,and Intuitionism

Gérard Berryhttp://www-sop.inria.fr/members/Gerard.Berry/

Collège

de France

Algorithms,

Machines, and

Languages

Martin-Honoris Abadi-

Causa, June 26t

h, 2015

G. Berry, Colloque Abadi

Recognizing Automata

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Deterministic Non-deterministic

(w.r.t. s0 and b)

G. Berry, Colloque Abadi 25/06/2015

Derivatives of Regular Languages

b-1(L)

a-1(L) ba, abba, bba, abbabba, bbbbababbbbba,...

ba, abba, bba, abbabba, bbbbababbbbba,...

ba, abba, bba, abbabba, bbbbababbbbba,...L

u-1(L) { v | u v L } ua-1(L) a-1(u-1(L))what remains to be written after writing u

Derivatives of Regular Expressions

• a-1(0) 0• a-1(1) 0• a-1(b) 0 if b a• a-1(a) 1• a-1(e e’) a-1(e) a-1(e’)

• a-1(e · e’) a-1(e) · e’ (e) · a-1(e’)

• a-1(e* ) a-1(e) · e*

a-1(e) regular expression generating a-1(L(e))

• e e0 (ab b)* ba

• a-1(e0) b (ab b)* ba e1

• b-1(e0) (ab b)* ba a e2

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Convergent Iterative Process

• a-1(e1) 0

• b-1(e1) (ab b)* ba e0

• a-1(e2) b (ab b)* ba 1 e3

• b-1(e2) (ab b)* ba a e2

• a-1(e3) 0

• b-1(e3) (ab b)* ba e0

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• a-1(e0) e1

• b-1(e0) e2

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Constructing the Deterministic Automaton

• a-1(e1) 0

• b-1(e1) e0

• a-1(e2) e3

• b-1(e2) e2

• a-1(e3) 0

• b-1(e3) e0

• (e3) 1

deterministic automaton(Brzozoswki)

• an expression is linear if it contains each letter at most once

• linearize expressions by uniquely indexing letters

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Linear Expression

s0 (a0b1 b2)* b3a4

a0-1(s0) b1(a0b1 b2)* b3a4 s1

b2-1(s0) (a0b1 b2)* b3a4 s0

b3-1(s0) a4 s2

b1-1(s1) s0

a4-1(s0) s3

Non-Deterministic Automaton

berase

indices

Non-deterministic automatonrecognizing L(e0)

Implementation by Boolean Circuits

The Deterministic Case : 1-hot encoding

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(ab+b)*ba

1-hot encoding(only one ri to 1)

size explosion!fanout explosion !

The Non-Deterministic Case

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(ab+b)*ba no size explosionÞ much better!

On-The-Fly Subset Construction

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(ab+b)*ba

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(ab+b)*ba

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(ab+b)*ba

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(ab+b)*ba

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(ab+b)*ba

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(ab+b)*ba

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(ab+b)*ba

abbabb

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(ab+b)*ba

abbabb

Fundamental Practical Result

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Any regular expression of size n is recognized

by a circuit with n+1 registers and at most n2 gates

• Scales up in size, is always superfast

• Almost always better than determinization

• The circuit can be cleverly optimized and formally verified (using BDDs or SAT)

When coding the DFA in HW, why one register per state? Number states in binary log(n) regs !

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Alternative: Dense Encoding ?

Not Quite ! State transition logic can be

exponential in the number of registers.

Furthermore, n! numberings to try,

and no heuristics for that!

Expensive commercial systems cannot

handle really useful DFAs with 12 states

Saving One More Exponential : ABRO

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Emit O as soon as A and B have arrivedReset behavior each time R is received

Memory writeR : RequestA : AddressB : DataO : Write

A / B /

A / OB / O

A B / O

SyncCharts (C. André)

A / B /

Hierarchical synchronousconcurrent automata

(Synchronous Statecharts)

loop abort { await A || await B }; emit O ; halt when Rend loop

ABCRO : from exponential to linear

flat automaton Hierarchical automatonlinear

The Hierarchical ABRO Circuit

loop abort { await A || await B }; emit O ; halt when Rend loop

• Should we still beleive in DFAs?

• NFAs are deterministic if use in the proper way ! … and they save an exponential

• Synchronous languages a la Esterel / SyncCharts save at least another exponential (see D. Harel) !

• They can be efficiently implemented in HW and SW always better than human designs !

• Analysis and verification can be performed by symbolic techniques (BDDs, SAT, SMT)

…which might be exponential but do work quite well in practice

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Conclusion 1

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Resource Sharing Combinational Cycles

O if C then F(G(I)) else G(F(I))

Sharad Malik, Analysis of Cyclic Combinational CircuitsIEEE Transactions on Computer-Aided Design of Integrated

Circuits and Systems, vol. 13, no. 7, July 1994

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O if C then F(G(I)) else G(F(I))

cycle F

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C 1 O if C then F(G(I)) else G(F(I))

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The cycle is logically soundand electrically sound !

C 0 O if C then F(G(I)) else G(F(I))

• 16-bytes circular buffer, bytes coming in randomly

• Instruction length depending on the first byte and a variable number of other bytes in the instruction text

• Instruction length potentially arbitrary

• Naturally cyclic design, hard to make acyclic23/04/2014 31G. Berry, IHP

ILD Instruction Length Decoder

• Bad : no electrical stabilization, no unique logical solution X X X X

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The Three Kinds of Cyclic Circuits

• Good : electrical stabilization, logical consistency previous examples

• Weird : unique logical solution, but electrical stabilization depending on wire and gate delays ToBe ToBe ToBe

no electrical stabilization when starting from ToBe 0 with D2 and E5

• Logical gates : zero-delay, grouping possible– polynomial notation : y1 x, s2 s1xs2 s1xs2

• Explicit delay nodes

• At least one delay per cycle

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Circuits With Delays

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UN-Delay and Stability d

UN-delay : dℝ+

ht,ub and td u h’td,ub

• A history h is stable at b after a delay d if hd,∞ b• Otherwise, h is called unstable or oscillating

• Goal : to represent the not gate– x stable to 1 : ht,u ⊨ x– logical opposite : ht,u ⊨ x– but the logical opposite is satisfied by any unstable

signal– we want x stable to 0, i.e. x x, which is different!

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Intuitionistic Negation

ht,u ⊨ iff t’,u’⊂t,u. ht’,u’ ⊨ is never satisfied by h on t,u different from is not satisfied by h !

0 t uneither ht,u) ⊨ x nor ht,u) ⊨ x

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Summary of UN-Logic Definition

ht,u ⊨ if ht,u ⊨ and ht,u ⊨

ht,u ⊨ if ht,u ⊨ or ht,u ⊨

ht,u ⊨ R if ∈t,u. h∈R

ht,u ⊨ if t’,u’⊂t,u. ht’,u’ ⊨ ht’,u’ ⊨

ht,u ⊨ if t’,u’⊂t,u. ht’,u’ ⊨

ht,u ⊨ if t’,u’⊂t,u. ht’,u’ ⊨ ht’,u’ ⊨

ht,u ⊨ d if td u if htd,u ⊨

Notation : ⊨ iff h,t,u. ht,u ⊨ ht,u ⊨

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Deductive Calculus Formulae : ⊢ vs. ⊨

Timed region : dR

Timed region : kK k for K finite or infinite

C,I ⊨ model :

C,I ⊢

• Syntactic sequents

sS s d e)

xI1 0x yI0 0y

Horn clauses ⊢

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Computation Deduction (Curry-Howard)

1. C,I ⊢ dR

iff there exists a sequence d0R0, d1R1,..., dnRn dR

such that, for all i, di is in (i.e., an input value)

or derivable from the dj, ji by a deduction rule

2. C,I ⊢ kK k

iff their exists kK such that C,I ⊢ k

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Deduction Rules

true d1

booldR d e R⊆S

dR R ⊃eSchain

maxd,eS∩Tjoin gate inputs gathering

weakening

+ classical Boolean rules for regions (OK since applied only to stable signals)+ arithmetic operations on delays

for C,I fixed, C,I ⊢ ... implicit everywhere

transition chainingy e x x ⊃ey)x ⊃ ey

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max(d1,d2) s1s2

case x0i.e. 0x

C s1 d1 x s2 d2 xs1s2

chain0xs1s2

x0 region s1s2 reached in time max(d1,d2)

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case x1i.e. 0x

0xchain

d1xs1s2bool

d1d2s2

joind1s1

0xchain

max(d1, d1d2) s1s2

x1 region s1s2 reached in time d1d2

• Theorem 2 : equivalence of ⊨ and ⊢ for circuits

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The Key Theorems

C,I,. C,I ⊨ C,I ⊢

• Theorem 3 : Intuitionism of ⊨

C,I,. C,I ⊨ . C,I ⊨

A disjunction (even infinite) can only by validated by oneof its members (immediate from Theorem 2 and definition of C,I ⊢ )

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Corollary : stabilization is deterministicLet s a delay assignment for C and I an input vector. Then the histories h of s in C,I have only two possible behaviors:

1. all the h stabilize to the same value2. there is at least one oscillating valid history h

A circuit is constructive iff its outputs cannot oscillate

Proof : let 1s 1s 2s 2s 3s 3s ...Preuve ::then (infinite) expresses that s stabilizes eventually

case 1 : C,I ⊨ . Then C,I ⊨ k for some k by thm.3

(intuitionism), for instance k ms.

Hence h. h ⊨ C,I h ⊢ ms, any h stabilizes to 1case 2 : C,I ⊨ . Then h. h ⊨ C,I h ⊨ is impossible.

Hence h. h ⊨ C,I h ⊨ , and this h oscillates for s

The Central Result

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Constructive Boolean Circuit Logic

e e’ 1

e’ 1

e e’ 1 e e’ 0

e 0 e’ 0

• Circuit C, input vector : I inputs → {0,1}• formulae : I ⊢ e b, written e b when I constant

x e C e b

e e’ 0

e’ 0

e e’ 0 e e’ 1

e 1 e’ 1

e 1I I(I)I input

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Proof Transformation Example

max(d1,d2) s1s2

cas x0i.e. 0x

chain0xs1s2

I(x)0 ⊢ x0xs1s2 1s1x C s2 xs1s

UN-logic

Constructive Boolean Logic

s11 s21

• For given delays, UN-provability vs. ⊢ is a necessary

and sufficient condition for UN-stabilization vs. ⊨

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There We Are !

• But any proof with delays can be transformed into a proof without delays, and conversely

Which means: Provability in Constructive Boolean Logic exactly Which means: reflects electrical constructivity for all delays

Bonus: given the delays, proof-construction based simulationcomputes the maximal reaction time w.r.t. each input

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• Etude complète de la stabilisation des circuits cycliques

dans le modèle de délais UN, en reliant modèle ⊨ et

déduction syntaxique ⊢, et en ignorant transitoires, oscillations, métastabilité etc. (qu’on peut aussi étudier)

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Conclusion

• stabilisation électrique prouvabilité constructive booléenne

(avec délais) des sorties (sans délais)

• A suivre au prochain cours : – constructivité pour toutes entrées– constructivité des circuits séquentiels (avec registres)– algorithmes efficaces de calcul de la constructivité

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References

Constructive Boolean Circuits and the Exactness of Timed Ternary Simulation M. Mendler, T. Shiple et G. Berry. Formal Methods in System Design, Vol.40, No.3, pp. 283-329, Springer (2012).

Constructive Analysis of Cyclic CircuitsT. Shiple, G. Berry et H. Touati. Proc. Int. Design and Testing Conference IDTC'96, Paris, France (1996).

Asynchronous CircuitsJ. Brzozowski et C-J. Seger.Springer-Verlag (1995).

Determinism,Electricity, and Intuitionism Gérard Berry Collège de France Algorithms, Machines,...

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