Digital Design: Principles and Practices Chapter 4 Combinational Logic Design Principles.

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Digital Design:Principles and Practices

Chapter 4Combinational Logic Design Principles

Introduction

• Combinational Logic CircuitOutputs depend only on current inputs Example: The rotary channel selector knob on an old-fashioned TV

• Sequential Logic CircuitOutputs depend on current inputs and on past inputs Feedback loop Example: The channel selector controlled by the up and down

pushbuttons on a TV remote control

Introduction (cont’d)

• Analysis Logic diagram Formal description of the function

• Synthesis Formal description Logic diagram

• Combinational circuits may have one or more outputs.• In this chapter, we focus on single-output circuits.

4.1 Switching Algebra

Boolean Algebra• Invented by English mathematician George Boole in 1854

• Two-valued algebraic system 0 or 1 (LOW or HIGH)

• Symbolic variables (such as W, X, Y, and Z) are used

• The opposite (or complement) of an input signal level We use a prime (’) to denote an inverter’s function

• Logic multiplication Logical AND: ( ． )

• Logical addition Logical OR: ( + )

Algebraic Notation for Logic Gates

• The axioms (or postulates) of a mathematical system are a minimal set of basic definitions that we assume to be true, from which all other information about the system can be derived.

Axiom (cont’d)

• An axiom is any mathematical statement that serves as a starting point from which other statements are logically derived. Unlike theorems, axioms (unless redundant) cannot be derived by principles of deduction, nor are they demonstrable by mathematical proofs, simply because they are starting points; there is nothing else from which they logically follow (otherwise they would be classified as theorems).

(Source: http://en.wikipedia.org/wiki/Axiom)

Axioms

(A1) X = 0 if X ≠ 1 (A1’) X = 1 if X ≠ 0

(A2) If X = 0, then X’ = 1 (A2’) If X = 1, then X’ = 0

(A3) 0 ． 0 = 0 (A3’) 1 + 1 = 1

(A4) 1 ． 1 = 1 (A4’) 0 + 0 = 0

(A5) 0 ． 1 = 1 ． 0 = 0 (A5’) 1 + 0 = 0 + 1 = 1

Theorems (One Variable)

Perfect Induction

• To prove theorem T1 ( X + 0 = X ): [X = 0] 0 + 0 = 0 (true, according to

axiom A4’) [X = 1] 1 + 0 = 1 (true, according to

axiom A5’)

Theorems (2 or 3 Variables)

Proofs

• Theorem T9• Theorem T11

• Replace each variable with an arbitrary logic expression: (X + Y’) + Z’ = X + (Y’ + Z’) (based on T7)

(V’ + X) ． (W ． (Y’ + Z)) + (V’+X) ． (W ． (Y’+Z))’ = V’ + X (based on T10)

Theorems (n variables)

DeMorgan’s Theorems

• Theorem T13

DeMorgan’s Theorems

• Theorem T13’

DeMorgan’s Theorems – An Example

• F(W, X, Y, Z) = (W’ ． X) + (X ． Y) + (W ． (X’ + Z’))

• Prove that:[F(W, X, Y, Z)]’ = (W + X’) ． (X’ + Y’) ． (W’ + (X ． Z))

Duality• The primed version of each axiom (e.g., A5’) is obtained from

the unprimed version (e.g., A5) by simply swapping 0 and 1 and, if present, “ ．” and “ + ”.

• Metatheorem A metatheorem is a theorem about theorems.

• Principle of DualityAny theorem or identity in switching algebra remains true if 0 and 1 are swapped and “ ．” and “+” are swapped throughout.

Operator Precedence

• Logic AND ( ． ) has higher precedence than Logic OR ( + ).

• Apply Principle of Duality on Theorem T9 X + X ． Y = X [T9]

X + (X ． Y) = X

X ． (X + Y) = X [T9’]

Truth Table

20• The truth table for an n-variable logic function has 2n rows.

Definitions

• Literal• Product term• Sum-of-products (SOP) expression• Sum term• Product-of-sums (POS) expressions• Normal term• Minterm• Maxterm

Literal

• A literal is a variable or the complement of a variable.

• Examples: X Y X’ Y’

Product Term

• A product term is a single literal or a logical product (‘ ．’ ) of two or more literals.

• Examples: Z’ W ． X ． Y X ． Y’ ． Z W’ ． Y’ ． Z

Sum-of-Products (SOP) Expression

• A sum-of-products expression is a logical sum of product terms.

• Examples: Z’ + W ． X ． Y + X ． Y’ ． Z + W’ ． Y’ ． Z

Sum Term

• A sum term is a single literal or a logical sum of two or more literals.

• Examples: Z’ W + X + Y X + Y’ + Z W’ + Y’ + Z

Product-of-Sums (POS) Expression

• A product-of-sums expression is a logical product of sum terms.

• Examples: Z’ ． (W + X + Y) ． (X + Y’ + Z) ． (W’ + Y’ + Z)

Normal Term

• A normal term is a product or sum term in which no variable appears more than once.

• Examples of non-normal terms: W ． X ． X ． Y’ W + W + X’ + Y

• Examples of normal terms: W ． X ． Y’ W + X’ + Y

Minterm

• An n-variable minterm is a normal product term with n literals.

• Examples (4-variable minterms): W’ ． X’ ． Y’ ． Z’ W ． X ． Y’ ． Z W’ ． X’ ． Y ． Z’

Maxterm

• An n-variable maxterm is a normal sum term with n literals.

• Examples (4-variable maxterms): W’ + X’ + Y’ + Z’ W + X’ + Y’ + Z W’ + X’ + Y + Z’

Minterms and Maxterms

Canonical Sum

• The canonical sum of a logic function is a sum of minterms corresponding to truth-table rows (input combinations) for which the function produces a logic ‘1’ output.

• Table 4-5:F = X’ ． Y’ ． Z’ + X’ ． Y ． Z + X ． Y’ ． Z’ + X ． Y ． Z’ + X ． Y ． Z

Minterm List (Σ notation)

• Table 4-5:F = ΣX,Y,Z(0,3,4,6,7)

Canonical Product

• The canonical product of a logic function is a product of the maxterms corresponding to input combinations for which the function produces a logic ‘0’ output.

• Table 4-5:F = (X + Y + Z’) ． (X + Y’ + Z) ． (X’ + Y + Z’)

Maxterm List (Π notation)

• Table 4-5:F = ΠX,Y,Z(1,2,5)

We Have Learned …

• Five possible representations for a combinational logic function:

1) Truth Table

2) Canonical sum (a type of SOP expression)

3) Minterm list (Σ notation)

4) Canonical product (a type of POS expression)

5) Maxterm list (Π notation)

4.2 Combinational-CircuitAnalysis

A 3-Input, 1-Output Logic Circuit

A 3-Input, 1-Output Logic Circuit(cont’d)

F = ( (X + Y’) ． Z) + (X’ ． Y ． Z’) = X ． Z + Y’ ． Z + X’ ． Y ． Z’

F = ( (X + Y’) ． Z) + (X’ ． Y ． Z’) = X ． Z + Y’ ． Z + X’ ． Y ． Z’ = (X + Y’ + Z’) ． (X’ + Z) ． (Y + Z)

Logic Circuits with Equivalent Function

4.3 Combinational-CircuitSynthesis

Combinational Circuit Synthesis

• Hardware Description Language (HDL) Verilog, VHDL Circuit synthesis software (automatic circuit synthesis)

• Target Devices FPGA ASIC cell library

• Circuit synthesis by hand

A 4-bit Prime-Number Detector

• Given a 4-bit input combination N = N3N2N1N0, produce a 1 (HIGH) output for N = 1, 2, 3, 5, 7, 11, 13, and 0 (LOW) otherwise.

• Answer:F = ΣN3,N2,N1,N0(1, 2, 3, 5, 7, 11, 13)

= N3’ ． N2’ ． N1’ ． N0 + N3’ ． N2’ ． N1 ． N0’ + N3’ ． N2’ ． N1 ． N0 + N3’ ． N2 ． N1’ ． N0 + N3’ ． N2 ． N1 ． N0 + N3 ． N2’ ． N1 ． N0 + N3 ． N2 ． N1’ ． N0

A 4-bit Prime-Number Detector(cont’d)

Circuit Manipulations

• Any sum-of-produces (SOP) expression can be realized as: An AND-OR circuit; or A NAND-NADN circuit

• Any product-of-sums (POS) expression can be realized as: An OR-AND circuit; or A NOR-NOR circuit

• In most logic technologies, inverting gates (like NAND and NOR) are faster than noninverting gates like AND and OR.

Circuit Manipulations - SOP

Circuit Manipulations - POS

Circuit Manipulations

Theorems (2 or 3 Variables)

F = ΣN3,N2,N1,N0(1, 2, 3, 5, 7, 11, 13)

= ( N3’ ． N2’ ． N1’ ． N0 + N3’ ． N2’ ． N1 ． N0 ) + ( N3’ ． N2 ． N1’ ． N0 + N3’ ． N2 ． N1 ． N0 ) + …

= ( N3’ ． N2’ ． N0 ) + ( N3’ ． N2 ． N0 ) + …

= N3’ ． N0

Combinational-Circuit Minimization(The Prime-Number Detector)

Karnaugh Map (K-map)• Phonetic Pronunciation: KAR-no• Pronounce

• The Karnaugh Map for an n-input logic function is an array with 2n cells, one for each possible input combination or minterm.

• The small number inside each cell is the corresponding minterm number in the truth table.

• To represent a logic function on a Karnaugh map, we simply copy 1s and 0s from the truth table or equivalent to the corresponding cells of the map.

Karnaugh Map

Minimized Circuit

Karnaugh Map

使用 K-map 做邏輯簡化 - Summary( 簡化為 Minimum SOP Expression)

1) 每 2i 個 cells 一組2) 每一組內的所有 cells 都必須為 1 ( 或是 don’t

cares)

3) 每一組在 K-map 上必須為長方形 / 正方形4) 每一組 ( 長方形 ) 必須要盡可能的愈大愈好5) 每個 K-map 上的 1 都要被涵蓋6) 愈少組愈好

Karnaugh Map

Minimal Sum

• A minimal sum of a logic function F(X1, …, Xn) is a sum-of-products (SOP) expression for F such that no SOP expression for F has fewer product terms, and any SOP expression with the same number of product terms has at least as many literals. Minimal SOP expression

Minimum SOP expression

Prime Implicant• A logic function P(X1, …, Xn) implies a logic function F(X1, …, Xn)

if for every input combination such that P = 1, then F = 1. P F F includes P, F covers P

• A prime implicant of a logic function F(X1, …, Xn) is a normal product term P(X1, …, Xn) that implies F, such that if any variable is removed from P, then the resulting product term does not imply F.

• [Prime-Implicant Theorem]A minimal sum is a sum of prime implicants.

K-Map Simplification of SOP ExpressionsEXAMPLE 4-28Use a Karnaugh map to minimize the following

(standard) SOP expression:

CBACBACBABCACBA

Ans: B’ + A’ ． C74

K-Map Simplification of SOP ExpressionsEXAMPLE 4-29Use a Karnaugh map to minimize the following SOP

expression:

CDBACDBADCABDCBADCB

DCBADABCDBCADCBA

Ans: D’ + B’ ． C75

K-Map Simplification of SOP Expressions

EXAMPLE 4-29 (Related Problem)Use a Karnaugh map to simplify the following SOP

expression:

W XYZ W XYZ W XYZ WYZ W XYZ

Ans: X’Y’Z’ + WX’Z + W’YZ76

Converting Between POS and SOP

EXAMPLE 4-33Using a Karnaugh map, convert the following standard

POS expression into a minimum POS expression and a minimum SOP expression.

( )( )( )A B C D A B C D A B C D

Ans: Minimum POS: (A+B+C’)(B’+C+D)(B+C+D’) Minimum SOP: AC + BC + BD +B’C’D’

“Don’t Care” Condition

K-map with “don’t cares”

EXAMPLE:Write the minimum SOP expression for the following Karnaugh map (Note that the ‘X’s in the truth table denote don’t care terms.):

CD AB 00 01 11 10

00 1 0 X X01 1 0 0 111 0 X 0 X10 X 0 1 1

K-map with “don’t cares”

EXAMPLE:Write the minimum SOP expression for the following Karnaugh map (Note that the ‘X’s in the truth table denote don’t care terms.):

5-Variable Karnaugh Map

Ans:DE’ + B’CE + A’BD’ + BC’D’E

Digital Design: Principles and Practices Chapter 4 Combinational Logic Design Principles.

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