Post on 02-Jan-2016
description
transcript
Digital System Clocking:Digital System Clocking:Digital System Clocking:Digital System Clocking:High-Performance and Low-Power AspectsHigh-Performance and Low-Power Aspects
Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic
Wiley-Interscience and IEEE Press, January 2003
Chapter 5: High-Performance System Issues
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 2
Absorbing Clock Uncertainties• Clock uncertainties
– Clock skew– Clock jitter
• Trends:– Clock distribution becomes progressively
difficult due to: • load mismatch• Process, voltage, and temperature variations.
– The clock uncertainties occupy increasing portion of the cycle time; typically 2 FO4.
• The ability to reduce impact of these uncertainties is one of the most important properties of the high-performance system.
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 3
Clock Generation and Distribution Non-idealities
• Jitter– Temporal variation of the clock signal manifested as
uncertainty of consecutive edges of a periodic clock signal.
– It is caused by temporal noise events– Manifested as:
- cycle-to-cycle or short-term jitter, tJS
- long-term jitter, tJL
– Mainly characteristic of clock generation system
• Skew– Time difference between temporally-equivalent or
concurrent edges of two periodic signals– Caused by spatial variations in signal propagation – Manifests as CSE-to-CSE fluctuation of clock arrival at
the same time instance– Characteristic of clock distribution system
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 4
Clock Uncertainties
Ref_Clock
Received Clock
T
skewtskewt
jitt jitt
RCV_CLKt
DRV_CLKt
Clockuncertainty:jitter+skew
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 5
Clock Uncertainty Absorption Using Soft Clock Edge
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 6
Output of a flip-flop in the presence of clock jitter: Partovi et al. 1996
A recent design of a Flip-Flop, controlled by a narrow, locally generated clock pulse, with negative Setup Time exhibits some degree of clock uncertainty absorption.
Smaller variation in Qb arrival
Large initial variation in Clk arrival
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 7
200
220
240
260
280
300
-30 -20 -10 0 10 20 30 40 50 60
C lk arrival tim e [ps]
D-Q
del
ay [p
s]
tC U
D D Q m
D D Q M
N om inalC lk
C lk
Data-to-output characteristics in the presence of clock uncertainty
Data-to-Output Delay versus Clock Arrival Time when the data arrival time is constant. When no clock uncertainties are present, the clock is scheduled to arrive so that D-Q delay (tDQm) is smallest, in order to minimize the CSE overhead.
Q
Soft clock edge: short transparency window timing less dependent on clock
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 8
Dependence of data-to-output delay on clock arrival
Clock uncertainty tCU
D
Q
Clk
Worst-case DDQ
Nominal DD-Clk
DDQm
DDQM
Early DD-Clk
Late DD-ClkTNominal=0
The key role of a CSE is to minimize the propagation of clock uncertainty to the CSE output:
max [ ( )], [ / 2, / 2]DQM DQ Opt CU CUt
D D U t t t t
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 9
Timing Analysis with Clock Uncertainty Absorption
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 10
Total delay versus clock uncertainty
tCU=100ps
44ps
UOpt=30ps
DDQM=261ps
tCU=30ps
3ps
UOpt=-5ps
DDQM=220ps
Clk
D
Q
Clk
D
Q
(b) tCU=100ps (aCU=56%)(a) tCU=30ps (aCU=90%)We formulate clock uncertainty absorption CU of a storage element as the portion of the total clock uncertainty not reflected at the output:
CU
DQ
CU
DQmDQMCUCU t
D
t
DDt
1
PDtD LMCUCUDQm )1(
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 11
Critical race in the presence of clock uncertainty
D1 D2Q1 Q2
ClkA
BufA
BufB
BufC
ClkB
ClkC
ClkB
ClkC
BufB, BufCjitter
DCQ
HDLm
tCU
tCU
D1
Q1
D2
Earlyarrival
Latearrival
Fastpath
ClkA
Hold timeviolation
LogicD Q D Q
ClkB, ClkCskew
CULmCQm tHDD
Clock uncertainties induced prior to ClkA have no effect to fast paths
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 12
Idealized D-Q delay characteristic as a function of clock arrival
200
220
240
260
280
300
320
340
100 80 60 40 20 0 -20 -40 -60
D -C lk d ela y [p s]
D-Q
del
ay [
ps]
earlyC lk
nom inalC lk
lateC lk
D D Q= 238psregardless of clock
arrival
C lk
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 13
Time Borrowing
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 14
Time Borrowing
Classification:• Dynamic time borrowing
– Scheduling data to arrive to CSE when CSE is transparent• No “hard” boundaries between stages
– Occurs in latch-based level sensitive and soft-edge clocking.
• Static time borrowing– Inserting delay between clock inputs of the clocked
storage elements. – Clocks are scheduled to arrive so that the slower paths
obtain more time to evaluate, taking away the time from faster paths.
– It can operate with conventional hard-edge Flip-Flops. – Also called opportunistic skew scheduling
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 15
Dynamic Time Borrowing
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 16
Timing of two-phase level-sensitive pipeline with time borrowing
a
Borrowed timeof Stage2a
1
a
b
c
d
e
f
g
h
d1
P/2
L1 + Stage1a < P/2
Total borrowedtime at node f
2
1
Stage 1bStage 1a Stage 2a Stage 2bL1
c
2
L2
b e
1
L3
d g
2
L4
f h
1
L5
Stage 1 Stage 2
P/2
d2
d1 d2
d1 d2
d1
L2 + Stage1b > P/2
d2
d1 d2
L3 + Stage2a > P/2
d1 d2
d2d1
d1 d2
L4 + Stage 2b delay < P/2
D Q D Q D Q D Q D Q
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 17
Timing Analysis with Time Borrowing: Late Data Arrival
The minimum clock cycle time of the pipeline is not determined by the delay of the slowest stage in the pipeline. It is rather the average delay of the logic and latches through all stages.
Assumptions: 1) all logic blocks are used in time borrowing, 2) after N stages, the pipeline produces data at the same point in the cycle at which the input data was acquired
N
iiLogiciDQ DD
NP
2
1,, )(
1
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 18
Fast-path hazard
H
DCQ
late arrival due totime borrowing,
no hold time violation
earliest arrival,no time borrowing,hold-time violation
Stage 2ae
1
L3
d g
2
L4
f
1
2
d
e
f
In fast paths, analysis must assume that the data arrives at earliest possible time -> disregard effects of time borrowing
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 19
Time borrowing and signal loops
ALU
mux
Clk
The timing of signals in the loops, should be treated separately. If the overall propagation delay through the loop occur later with each cycle, it will result in a Setup Time violation. Any signal loop that borrows time from itself will eventually cause a timing violation.
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 20
Static Time Borrowing (Opportunistic Skew Scheduling)
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 21
Opportunistic skew scheduling
Clk1
Q1 D2
Clk2 Clk3
CSE2
Clk1,Clk3
Q1
D2
Clk2
Q2
D3
Stage 1
Slower Faster
Q3
Stage 1 Stage 2
Ref Clk
Borrowedtime =
D QCSE1
D Q Logic 1Q2 D3Logic 2
CSE3
D Q
Stage 2Q3
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 22
Opportunistic skew schedulingAdvantages:• It can operate with conventional Flip-Flops. • It places fewer constraints onto the circuit design,
allowing additional time slack where necessary. useful in localized critical paths where every
improvement directly increases the system clock rate
Disadvantages:• It increases the complexity of the clock distribution
system. • It is hard to control the inserted delays over
process, supply and temperature variations. • The analysis of clock skew is also complicated in
this asymmetric clock distribution network. impractical on a large-scale level
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 23
Time Borrowing and Clock Uncertainty
Level sensitive clocking, Soft clock edge
Clock uncertainty absorption Time borrowing
Varying clock arrival
Varying data arrival
Clock uncertainty absorption and time borrowing exploit the same data transparency property of CSE
Clocked storage elements
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 24
Clock Uncertainty Absorption with Level-Sensitive Clocking
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 25
Clock uncertainty immunity in single stage
D
TL
TLTT TT
tD
DD-Clk
Q
DDQ
DCQTLM
tt=0 t=tA(D)
UT
TM
W
tB
W/2 U UU
D D Q Q
C
2/WDDtT CQDQBL
UtWT BT 2/
HVDDTT LmCQmTL 21 ,,
System tolerates up to
to keep borrowing time
before violating hold time
System tolerates up to
before violating setup time
System tolerates up to
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 26
Clock uncertainty immunity in multiple stages D1
1
Stage 1 Stage 2 Stage 3
U
D1
Q1
D4
Q4
D7
3 P + W - tCU
1
2
DCQ
W
Pedge1
(late arrival)edge8
(early arrival)
edge2 edge3 edge4 edge7edge6edge5
Logic 1a Logic 1b Logic 2a Logic 2b Logic 3a Logic 3bL1
D QL2
D QL3
D QL4
D QL5
D QL6
D QL7
D Q
Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7
212121
Logic 1a, L2, Logic 1b,L3, Logic 2a
Logic 2b, L5, Logic 3a,L6, Logic 3b
WPUDDDDt CQCU 3)( 71133
)( 711 CUCQ tWUDDDDP
impact of the clock uncertainties reduced over multiple stages
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 27
Summary: Effects of clock uncertainties to a system with level-sensitive clocking
• Decreasing of the margins for time borrowing.
• The pipeline absorbs the uncertainties for the data that arrives during the transparency period of the Latch.
• The effect of the uncertainties is reduced to an average uncertainty over all stages in the path.
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 28
Soft-Edge Sensitive Clocking
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 29
Time borrowing with uncertainty-absorbing clocked storage elements
tCU
tCU
Borrowed time (tB)
NominalLogic 1 delay
ActualLogic 1 delay
nominalarrival
actual arrival due totime borrowing
Clk1
tD arrival
DDQ
Clk1,Clk3
Q1
D2
Clk2
Q2
D3
Stage 1 Stage 2D1 Q1
D QCSE1
Logic 1 D QCSE2
Logic 2 D QCSE3
D2 Q2 D3 Q3
Clk2 Clk3
NominalLogic 2 delay
ActualLogic 2 delay
tCU tCU tCU
]1)[( CUCUBDQ ttD
Nov. 14, 2003
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic 30
Conclusion
• High-performance CSE requirements: – Speed– Clock uncertainty absorption to accommodate
increasing effect of clock skew and jitter– Time borrowing to eliminate effects of imbalanced
stage delays
• Essential circuit technique: eliminate hard edges in critical paths
• Flip-flops with soft clock edge, level-sensitive latches become preferred choice of CSE
• Clock uncertainty absorption capability can be traded for time borrowing