Unit 2Inverters and Logic gates

Driving Large Capacitive LoadsSuper Buffers

Driving Large Capacitive Loads

• Large capacitive loads arises when signals must be propagated from the chip to off chip destinations.

• Long buses• CL >= 104 Cg (typically)• This must be driven through low resistances,• Else, will increase the delay (By increasing rise

and fall time), because, delay α CL

Contd..

• Three solutions 1. Cascading Inverters as drivers2. Super Buffers3. BiCMOS Drivers

Cascading Inverters as drivers

Contd..• fopt = e (k +fopt )/ fopt

• k = Cd / CgWhere Cd and Cg – Drain and Gate

Capacitance respectively.• k – Varies according to technology• Eg. For 1 um technology • k = Cd / Cg = .0043 / .02 = 0.215• Substitute different values for fopt in the above

equation and find the minimum value.• fopt = 2.93 (approx = 3)

Graph to find the stage ratio value

Super Buffers

• Inverting buffer• Non-inverting buffer

Inverting Super buffer

Operation

• Case (i) : Vin = 1– Transistors T1 and T2 On– Gate of T3 is pulled down to 0 (T3 = Off)– T4 is On (Since the gate is connected to Vin)– Hence the O/P is pulled down quickly.

Operation (Contd..)• Case (ii) : Vin =0– Transistor T2 is Off– T4 is Off (Since the gate is connected to Vin)– T3 is allowed to rise quickly to Vdd (On) as its gate

is connected Vdd by Transistor T1.– As Vg is connected to Vdd and transistor assumes

twice the average gate to source voltage Vgs (Since the channel exists already).

– Ids α Vgs (and hence charges the load quickly)– Hence equal transition time for rise and fall time.

Non-Inverting Super Buffer

BiCMOS Drivers (Inverter)

BiCMOS NAND Gate

BiCMOS Drivers

Effect of Temperature