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SubCode/Name:EC2303-COMPUTER ARCHITECTURE & ORGANIZATION

Unit : I Branch : EC Semester: V

UNIT I : INTRODUCTION

Syllabus:Computing and Computers, Evolution of Computers, VLSI Era, System

Design- Register Level, Processor - Level, CPU Organization, Data Representation, Fixed – Point Numbers, Floating Point Numbers, Instruction Formats, Instruction Types. Addressingmodes.

Objective: To have a thorough understanding of the basic structure, design and operation of a digital computer.

Session No.

Topics to be covered Time Ref Teaching Method

1. Functional units of a computer and basic operational concepts

50m 1(1-11) BB

2. Evolution of Computers – The different Generations

50m 1(12-34),2 (19-21),5(1-37)

BB

3. VLSI Era – ICs, Processor Architecture, System Architecture

50m 1(35-55) BB

4. System Design – System representation, Design Process, the gate level

50m 1(64-82)5(38-80)

BB

5. Register Level – Register level components, programmable logic devices, register level design

50m 1(83-113) BB

6. Processor – Level – Processor level components, processor level design

50m 1(114-125) BB

7. CPU Organization – Fundamentals, additional features

50m 1(137-159) BB

8. Data Representation - Fixed – Point Numbers, Floating Point Numbers

50m 1(160-177) BB

9. Instruction Formats, Instruction Types. Addressing modes

50m 1(178-210), 2(48-56)

BB

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SubCode/Name:EC2303-COMPUTER ARCHITECTURE & ORGANIZATION

Unit : II Branch : EC Semester: V

UNIT II : DATA PATH DESIGN Syllabus:

Fixed Point Arithmetic, Addition, Subtraction, Multiplication and Division, Combinational and Sequential ALUs, Carry look ahead adder, Robertson algorithm, booth’s algorithm, non-restoring division algorithm, Floating Point Arithmetic, Coprocessor, Pipeline Processing, Pipeline Design, Modified booth’s Algorithm.Objective: To discuss in detail the operation of the arithmetic unit including the algorithms & implementation of fixed-point and floating-point addition, subtraction, multiplication & division.

Session No.

Topics to be covered Time Ref Teaching Method

10. Fixed Point Arithmetic – Basic adders and subtractors

50m 1(223-227)2(369-371)

BB

11. High Speed Adders – Carry-lookahead adder 50m 1(228-232) 2(371-375)

BB

12. Multiplication – Twos – complement Multiplier 50m 1(233-238)2(383-389)4(197-205)

BB

13. Robertson algorithm 50m 1(238-239)

14. Booth’s algorithm 50m 1(239-244)2(380-382)

BB

15. Division algorithm 50m 1(245-251)2(390-392)4(206-213)

BB

16. Combinational ALUs 50m 1(252-255) BB

17. Sequential ALUs 50m 1(256-265) BB

18. Floating Point Arithmetic - Basic Operations, Floating Point Units, Addition Algorithm

50m 1(266-271)2(393-400)4(219-233)

BB

19. Coprocessor 50m 1(272-275) BB

20. Pipeline Processing, Pipeline Design 50m 1(276-292) BB21. CAT – I 75m - -

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SubCode/Name:EC2303-COMPUTER ARCHITECTURE & ORGANIZATION

Unit : III Branch : EC Semester: V

UNIT III : CONTROL DESIGN

Syllabus:Hardwired Control, Microprogrammed Control, Multiplier Control Unit,

CPU Control Unit, Pipeline Control, Instruction Pipelines, Pipeline Performance, Superscalar Processing,Nano Programming.

Objective: To study in detail the different types of control and the concept of pipelining

Session No.

Topics to be covered Time Ref Teaching Method

22. Control Design – Basic Concepts 50m 1(303-308) BB

23. Hardwired control – Design Methods 50m 1(308-331)5(332-346)

BB

24. Hardwired control – Design Examples 50m 1(308-331) BB

25. Micro programmed control-micro instructions, micro program sequencing

50m 1(332-343) BB

26. Micro programmed control 50m 1(332-343)5(348-380)

BB

27. Multiplier Control Unit 50m 1(344-353) BB

28. CPU Control Unit 50m 1(354-361) BB

29. Pipeline Control – Instruction Pipeline 50m 1(364-371)

4(289-290)

BB

30. Pipeline basics and performance 50m 1(371-383) BB

31. Superscalar Processing 50m 1(384-390)2(481-486)

BB

32. Nano Programming 50m 1(361-364) BB

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SubCode/Name:EC2303-COMPUTER ARCHITECTURE & ORGANIZATION

Unit : IV Branch : EC Semester: V

UNIT IV : MEMORY ORGANIZATION

Syllabus:Random Access Memories, Serial - Access Memories, RAM Interfaces,

Magnetic Surface Recording, Optical Memories, multilevel memories, Cache & Virtual Memory, Memory Allocation, Associative Memory.

Objective: To study the hierarchical memory system including cache memories and virtual memory.

Session No.

Topics to be covered Time Ref Teaching Method

33. Random Access Memories – Organization, Design 50m 1(407-417)2(292-308)

BB

34. Serial - Access Memories – Access methods,

Organization, Magnetic surface recording

50m 1(418-421) BB

35. Optical Memories, Multilevel Memories 50m 1(424-431)2(352-357)5(483-485)

BB

36. Cache Memories – Main features, Organization, Operation

50m 1(452-457)2(314-325)4(335-345)

BB

37. Virtual memory-address translation methods 50m 1(428-432)2(337-343)4(371-382)5(496-513)

BB

38. Memory Allocation – Non-preemptive allocation,

preemptive allocation, replacement policies

50m 1(443-452) BB

39. Associative Memory 50m 1(458-462)5(485-491)

BB

40. CAT-II 75m - -

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SubCode/Name:EC2303-COMPUTER ARCHITECTURE & ORGANIZATION

Unit : V Branch : EC Semester: V

UNIT V : SYSTEM ORGANIZATION

Syllabus:Communication methods, Buses, Bus Control, Bus Interfacing, Bus

arbitration, IO and system control, IO interface circuits, Handshaking, DMA and interrupts, vectored interrupts, PCI interrupts, pipeline interrupts, IOP organization, operation systems, multiprocessors, fault tolerance, RISC and CISC processors, Superscalar and vector processor.

Objective: To study the different ways of communicating with I/O devices and

standard I/O interfacesSession

No.Topics to be covered Time Ref Teaching

Method41. Communication methods – Basic Concepts, Buses 50m 1(480-483) BB

42. Bus Control, Interfacing, Arbitration 50m 1(491-504) BB

43. IO and system control - IO interface circuits, Handshaking

50m 1(504-510) BB

44. DMA – Direct Memory Access 50m 1(511-515) BB

45. Interrupts - vectored interrupts 50m 1(515-519 BB

46. PCI interrupts, Pipeline interrupts 50m 1(519-523) BB

47. IOP organization, Operation systems 50m 1(525-538) BB

48. Multiprocessors 50m 1(550-565) BB

49. Fault Tolerance 50m 1(567-578) BB

50. RISC and CISC processors 50m 3(282-290) BB

51. Superscalar and vector processor 50m 2(481-483) 4(493-499)

BB

52. CAT III 75m - -

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SubCode/Name:EC2303-COMPUTER ARCHITECTURE & ORGANIZATION

Branch : EC Semester: V

Course Delivery Plan:

Week 1 2 3 4 5 6 7 8 9 10 11 12 13

I II I II I II I II I II I II I II I II I II I II I II I II I II

Units I II III IV V

TEXTBOOKS:

1. John P.Hayes, ‘Computer architecture and Organisation’, Tata McGraw-

Hill, Third edition, 1998.

2. V.Carl Hamacher, Zvonko G. Varanesic and Safat G. Zaky, “ Computer

Organisation“, V edition, McGraw-Hill Inc, 1996.

REFERENCES:

3. Morris Mano, “Computer System Architecture”, Prentice-Hall of India, 2000.

4. Behrooz Parhami, “Computer Architecture”, Oxford Press.

5. P.Pal Chaudhuri, , “Computer organization and design”, 2nd Ed., Prentice

Hall of India, 2007.

6. G.Kane & J.Heinrich, ‘ MIPS RISC Architecture ‘, Englewood cliffs,

New Jersey, Prentice Hall, 1992.

Prepared by Approved by

Signature

Name G. PADMAVATHI PROF. E.G. GOVINDAN

Designation ASSISTANT PROFESSOR HOD/EC

Date 28/06/2010 28/06/2010