ECE 448: Spring 2013 Lab 5 FPGA Design Flow Based on Aldec Active-HDL Fast Reflex Game

transcript

ECE 448: Spring 2013Lab 5

FPGA Design Flow Based on Aldec Active-HDL

Fast Reflex Game

Part 1: Distribution of FPGA boards

Part 2: Diagnostics of FPGA boards

Part 3: Introduction to FPGA Design Flow based on Aldec Active-HDL

Part 4: Introduction to Lab 5

Part 5: Demos of Lab 4 & late demos of Lab 3

Agenda for today

Parts 1 & 2

Distribution and Diagnostics

of FPGA Boards

Part 3

Hands-on Session on

FPGA Design Flow

based on Aldec Active-HDL

Part 4

Introduction to Lab 5

Task 1

Experimental Testing of

Lab 4 for Task 5

& Lab 4 for Task 6

LAB4 for TASK5BTNL BTNR BTNU BTND BTNS

loadA loadB step run

BTNL BTNR BTNU BTND BTNS

BUTTON_UNIT SWITCH_UNIT

IVA IVB

SEG AN

hex0hex1hex2hex3

SSD_DRIVER

XSGN YSGN Xout Yout Aout Bout k

XSGN YSGN X Y A B k

next_out

CLK_RST_1

clk rst

clkrst

88 8 8 8 8

rstclk

enCNTRUP

rstclk

enMISR

rst clk

enLFSR

X”00” 8

IVBloadB

rst clk

enLFSR

X”00” 8

IVAloadA

clkclk

En ‘0’

clkrst

nextorst

enMISR

clkrst

= X”3FF”10

rstclk

AND not done

step run

LAB3eXout Aout

Bout kout

Debouncer RED loadA

Debouncer RED

runD Q‘1’

BTNR Debouncer RED loadB

clk clk

BUTTON_UNIT

BTNU Debouncer RED step

BTND Debouncer RED next_out

clk rst

Debouncer

rst clk

Generics of the Debouncer

k – size of the counter

DD – debouncing period in clock cycles

Please make sure that:

DD TCLK ≈ 10 ms

2k > DD

Rising Edge Detector - RED

output

SW IVA

SWITCH_UNIT

Counter UPCOUNTER UP

Counter UP

q(k-1..k-2)

Counter UP

SEG(6..0)

Counter UP

Counter UPrst

SSD_DRIVER

OC – One’s Complement

Multiplexing Digits

Generics of the SSD_DRIVER

1 ms ≤ Refresh period ≤ 16 ms

1 ms ≤ 2k TCLK ≤ 16 ms

fCLK = 100 MHz

k – size of the internal counter. Refresh period = 2k clock cycles.

CLK_RST_1

BTNRrst

IVA IVB

SEG AN

hex0hex1hex2hex3

SSD_DRIVER

XSGN YSGN X Y A B k

next_out

CLK_RST_2

clk rst

clkrst

88 8 8 8 8

CLK_RST_2

DCM_SP

IBUFG BUFGCLOCK

locked

clk_ibufg clk100

rstBTNL

rst_or

clkfxclkfx

clkBUFGclkfx_obufg

clk0_obufg

‘0’

BUFGMUX

Task 2

Verifying Maximum

Experimental Clock Frequency

CLK_RST_3

IBUFG BUFGCLOCK

locked

clk_ibufg clk100

rstBTNL

rst_or

clkfxclkfx

clkBUFGclkfx_obufg

clk0_obufg

BUFGMUX

ODDR2D0 D1 C0 C1 CE R S

CLOCKFX

‘1’ ‘0’ ‘1’ ‘0’ ‘0’

clkfx clkfx_180

ODDR2D0 D1 C0 C1 CE R S

CLOCK100

‘1’ ‘0’ ‘1’ ‘0’ ‘0’

clk100 clk100_180

clk180

clkfx180

BUFGclk100_180

clk180_obufg

BUFGclkfx_180

clkfx180_obufg

IVA IVB

SEG AN

hex0hex1hex2hex3

SSD_DRIVER

XSGN YSGN X Y A B k

next_out

CLK_RST_3

clk rst

clkrst

88 8 8 8 8

CLOCKFX

CLOCK100

Verifying Maximum Clock Frequency

The circuit should work correctly for

SW(0) = 1 => clk = clk100 => fCLK = 100 MHz

The circuit should fail for

SW(0) = 0 => clk = clkfx => fCLK > maximum fCLK

DCM_SP_inst : DCM_SPgeneric map ( CLKDV_DIVIDE => 2.0,-- CLKDV divide value-- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).-- Divide value on CLKFX outputs - D - (1-32)-- Multiply value on CLKFX outputs - M - (2-32)-- CLKIN divide by two (TRUE/FALSE)-- Input clock period specified in nS-- Output phase shift (NONE, FIXED, VARIABLE)-- Feedback source (NONE, 1X, 2X)CLKFX_DIVIDE => ………….,CLKFX_MULTIPLY => ………,CLKIN_DIVIDE_BY_2 => FALSE,CLKIN_PERIOD => 10.0,CLKOUT_PHASE_SHIFT => "NONE",CLK_FEEDBACK => "1X”,

Setting frequency of clkFX during DCM_SP Instantiation

Observing CLOCK100 and CLOCKFXusing Oscilloscope

Using oscilloscope and two versions of your implementation(with different values of generics of DCM_SP)show the clock signal for the following three cases:

A.fCLK = 100 MHz

B.fCLK = maximum clock frequency returned by the tools

C.fCLK = 10 MHz

Document your findings using digital photos.Discuss your observations.

NET "CLOCK100" LOC = "…….." | IOSTANDARD = "LVCMOS33";

NET "CLOCKFX" LOC = "…….." | IOSTANDARD = "LVCMOS33”;

New Lines in theUser Constraint File (UCF)

Select two arbitrary board pins that would be the most easy

to observe, and have a relatively large physical distance

from each other (to avoid interference).

Task 3

Fast Reflex Game

Rules of the Game (1)

BCD Counter is initialized with 10.00 seconds.

After pressing start_stop the counter starts counting down every 0.01 second: 9.99, 9.98, 9.97, …, 0.02, 0.01, 0.00, -0.01, -0.02 …

The goal is to press the start_stop button againas close as possible to 0.00.

After the second press, the counter is stopped.

Rules of the Game (2)The last obtained result can be a. stored with the press of the store button b. skipped with the press of the skip button.After performing these operations the counter is againinitialized to 10.00.

Only the last 4 stored results are remembered by the system.

The minimum and the maximum absolute value of these last 4 stored results is calculated.

The clear button clears the storage, and initializesthe counter to 10.00.

Meaning of Buttons

clear start_stop next_out

BTNL BTNR

Rules of the Game (3)The next_out button allows displaying

1. current value of the counter 2. the last stored result 3. the result with the minimum absolute value 4. the result with the maximum absolute value.

After each press of the next_out button, the mode of display changes to the next one in the wrap-around fashion.

The current mode is also indicated with an appropriate number of the rightmost LEDs turned on(1 for the current value of the counter, 2 for the last stored result, etc.)

CD_mod_9 b(3)

X”1”4

b(4)enbout

rstrst clk

CD_mod_9

X”0”4

enbout

rstrst clk

CD_mod_9

X”0”4

enbout

rstrst clk

CD_mod_9 b(0)=bin

X”0”4

enbout

rstrst clk

b(2) b(1)

initclk

4-digit BCD Counter DownBCD_CD

clk rst

CD_mod_9 – Counter Down mod 9bin – borrow in

bout – borrow out

minimumminimum = 1 Counter = -9.99

dir = 0 : count downdir = 1 : count up

Result Storage & Processing - RSP

rstrst

storeresult

lastlast

MAXABS

maxMINABS min

output13

sel_out2

0 1 2 3

min maxlastresult

clk rst

MAXABS – Maximum Absolute Value

MINABS – Minimum Absolute Value

Debouncer RED clear

Debouncer RED

BTNR Debouncer RED next_out

BUTTON_UNIT

BTNU Debouncer RED store

BTND Debouncer RED skip

start_stop

CLK_RST_4

BTNDrst

Top-Level of Fast Reflex Game

CU_mod_N: Counter Up mod N

next_out

start_stop

BUTTON_UNIT

CONTROLLER

CU_mod_N

SEG AN

hex0hex1hex2hex3

SSD_DRIVER

clk rst

BCD_CD

OUT_FORMAT

result

sel_outoutput

binminus & D(2..0)

hex0hex1hex2hex3

CLK_RST_4

clk rst

clk rstrst

sel_out

rstrst

sel_out

store_res

clear_res

minimumminimum

clear_res

rst clk

Part 5

Demos of Lab 4

Late Demos of Lab 3

ECE 448: Spring 2013 Lab 5 FPGA Design Flow Based on Aldec Active-HDL Fast Reflex Game

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