ECE 511: Digital System & Microprocessor

Course Outline

Week Subject

W1 Digital Logic Review

W2-W3 Microprocessor Architecture & Overview

W3-W6 Microprocessor Instruction Set & Programming

W7-W9 Memory Interfacing

W10-W12 Parallel I/O Interfacing

References

J. L. Antonakos, “The 68000 Microprocessor: Hardware and Software Principles & Applications,” 5th Ed., Pearson Prentice-Hall, 2004.

C. M. Gilmore, “Microprocessors: Principles & Applications,” 2nd Ed., McGraw-Hill, 1995.

A. Clements, “Microprocessor System Design,” PWS-Kent, 1992.

Course Evaluation

Tests x 2 30% Quizzes x 3 20% Mini Projects 50%

If you have problems, please contact me:

Ahmad Ihsan bin Mohd Yassin

Rm. T2-A13-1A, Dept. of Comp. Eng.

Faculty of Elect. Eng.

UiTM, Shah Alam.

03-55436118, 017-2576295

*Please call before you see me.

Digital Logic Review: Part I

ECE 511: Digital System & Microprocessor.

What we will learn in this session:

Review of logic gates. Flip-flops. Decoders. Universal representation of logic gates.

Gates

What are gates? Gates are:

Simple electronic devices. Constructed using transistors. Used to design digital systems.

Three Basic Gates: AND OR NOT

Basic Gates can be combined into Extended Gates. Usually packed into ICs.

Gates as Building Blocks

Basic Gate - AND

The AND gate is similar to multiply operation.

AAND

BC

A B C

0

1

0

1

0

0

1

1

0

0

0

1

TRUTH TABLE

CBA CBA

Basic Gate - OR

The OR gate is similar to add operation.

ORA

BC

CBA CBA

A B C

0

1

0

1

0

0

1

1

0

1

1

1

TRUTH TABLE

Basic Gate - NOT

The NOT gate performs the inverse operation.

NOTA B

BA BA

TRUTH TABLE

A B

0

1

1

0

Extended Gates

Combination of basic gates to perform complex functions:NANDNORXOR XNORFlip-Flops

NAND Gate

Adds NOT after AND gate. AND outputs are inverted NAND (NOT-AND).

AAND

BCNOT

ANAND

BC

CBA

A B C

0

1

0

1

0

0

1

1

1

1

1

0

TRUTH TABLE

NOR Gate

Adds NOT after OR gate. OR outputs are inverted NOR (NOT-OR).

ORA

BCNOT CNOR

A

B

CBA A B C

0

1

0

1

0

0

1

1

1

0

0

0

TRUTH TABLE

XOR Gate XOR performs the Exclusive Or operation. When A=B, C=0; when A≠B, C=1.

)

A B C

0

1

0

1

0

0

1

1

0

1

1

0

TRUTH TABLE

CBA CBABA

XOR

A

B ) C

XNOR Gate Adds NOT after XOR gate. XOR outputs inverted XNOR (NOT XOR).

)

A B C

0

1

0

1

0

0

1

1

1

0

0

1

TRUTH TABLE

CBABA

XOR

A

B ) CNOT XOR

A

B ) C

Flip-Flops

Flip-Flops

An extended gate used as memory:Each FF stores 1 bit.

2 gates, feedback connections. 2 inputs, 2 outputs. More complex ones may:

Use timing from CLK.Perform bit toggle.

Reset-Set (RS) Flip-Flop

4 states: Three stable (Set, Reset, and Keep). One not stable (Unused).

2 inputs, 2 outputs. May also contain clock (CLK) signal.

RS Flip-Flop

*Assuming initial condition:S = 0, R = 0, Q = 0

Qprev S R Q

N/A 0 0 0

0 1 0 1

1 0 1 0

Doesn’tmatter 1 1 N/AUnstable

KEEP: Output unchanged

SET: Output set (Q = 1)

RESET: Output reset (Q = 0)

Q’

1

0

1

N/A

*As long as S=0 and R=0, Q will always remain at previous state.

RSFF

R

S

Q

Q’

Clocked RS Flip-Flop

*Assuming initial condition:S = 0, R = 0, Q = 0

Unstable

KEEP: Output unchanged

SET: Output set (Q = 1)

RESET: Output reset (Q = 0)

RSFF

R

S

Q

Q’

CLK

Only active when CLKis ↑

Reduced sensitivity to noise.

Qprev S R Q

N/A 0 0 0

0 1 0 1

1 0 1 0

Doesn’tmatter 1 1 N/A

Q’

1

0

1

N/A

CLK

↑

↑

↑

↑

0 Doesn’t matter

Doesn’t matter 0 1↓

JK Flip-Flop

Same as RS, but forbidden state used to toggle bit.

Can also be clocked using CLK.

Qprev J K Q

N/A 0 0 0

0 1 0 1

1 0 1 0

Q 1 1 QToggle

Output unchanged

Output set (Q = 1)

Output reset (Q = 0)

Q’

1

0

1

Q

*Assuming initial condition:J = 0, K = 0, Q = 0

JK Flip-Flop

Qprev S R Q

N/A 0 0 0

0 1 0 1

1 0 1 0

Q 1 1 QToggle

Output unchanged

Output set (Q = 1)

Output reset (Q = 0)

Q’

1

0

1

Q

J

K

Q

Q

*Assuming initial condition:J = 0, K = 0, Q = 0

Clocked JK

Qprev S R Q

N/A 0 0 0

0 1 0 1

1 0 1 0

Q 1 1 QToggle

Output unchanged

Output set (Q = 1)

Output reset (Q = 0)

CLK

↑

↑

↑

↑

CLK

J

K

Q

Q

0 Doesn’t matter

Doesn’t matter 0↓Only active when CLK

is ↑

Reduced sensitivity to noise.

D-Flip-Flop

Data latch. Modification of RSFF. Stores 1-bit of information.

Can be combined to store more. Data are stored in memory using millions

of DFFs.

D-Flip-Flop

Qprev D Q

Doesn’t Matter 1 1

Doesn’t Matter 0 0

Output set (Q = 1)

Output reset (Q = 0)

Q’

0

1

EN

1

1

*Only active when ENis 1

DFF

D

EN

Q

Q’

QPREVDoesn’t Matter

QPREV Q’PREV0

D-Flip-Flop: Timing Diagram

D

EN

Q

Storing 8-bits using DFF (RAM)

DFF DFFDFF DFFDFF DFF DFF DFF

Q3 Q5 Q6 Q7Q1 Q2 Q4Q0

EN

D3 D5 D6 D7D1 D2 D4D0

Data Bus

Asynchronous Latch

Allows both synchronous & asynchronous operations:Synchronous: CLK driven (Clocked JK).Asynchronous: similar to RSFF.

5 inputs, 2 outputs:J, K and CLK for synch. operation.PR, CLR for asynch. operation.

Asynchronous Latch

PRE CLR Q0 0 Follows J, K, CLK (Synch. JK)0 1 Q = 0, resets output.1 0 Q = 1, sets output.1 1 Not valid.

CLK

J

K

Q

Q

CLR(R)

PRE(S)

Universal Gates – NAND and NOR

NAND and NOR as Universal Gates In industry, NAND and NOR gates are

most common. Reason?

Can be used to represent any gate (functionally complete).

Easiest & cheapest to produce.

NAND Logic

NOT

NAND

AND NAND NAND

NAND Logic

OR

NAND

NAND

NAND

XOR

NAND

NAND

NANDNAND

NOR Logic

NOT

NOR

AND

NOR

NOR

NOR

NOR Logic

NOR NOROR

NOR

NOR

NOR

NOR

NOR

XOR

IC 4011 IC 7402

Decoders

Decoder

A digital circuit that detects a specific combination of input bits (code), and indicates the presence of the code by a specific output.

Typically has n inputs and 2n outputs, but other combinations also exist.

However, the number of inputs is always less than the outputs (noInputs < noOutputs).

Each combination of inputs will generate a unique pattern at the output.

Example: Active High 2-4 Decoder

2-4 Decoder

I0

I1

Y0

Y1

Y2

Y3

1

0

0

0

0

1

0

0

0

0

1

0

Y0

0

0

0

1

I0

0

1

0

1

I1

0

0

1

1

Y3 Y2 Y1

A specific pattern at the inputs.

Will activate a specific bit

at the outputs.

Example: Active Low 2-4 Decoder

2-4 Decoder

I0

I1

Y’0Y’1Y’2Y’3

0

1

1

1

1

0

1

1

1

1

0

1

Y’0

1

1

1

0

I0

0

1

0

1

I1

0

0

1

1

Y’3 Y’2 Y’1

A specific pattern at the inputs.

Will activate a specific bit

at the outputs.

Example: Active High 3-8 Decoder

0

1

0 0

0 0

10 0

110

1

1

0 0

1 0

11 0

111

0 0 0 0 0 0 0 1

0 0 0 0 0 0 01

1

0 0

0 0 0

0 0 0 0

0 0 0 0 0

0 0 0 0 0 0 1

0

1

1

1

1

0 0 0 0 0

0 0 0 0 0

0 0 0 0

0

0 0 0

0

0

0

A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

Example: Active Low 3-8 Decoder

0

1

0 0

0 0

10 0

110

1

1

0 0

1 0

11 0

111

1 1 1 1 1 1 1 0

1 1 1 1 1 1 10

0

1 1

1 1 1

1 1 1 1

1 1 1 1 1

1 1 1 1 1 1 0

1

0

0

0

0

1 1 1 1 1

1 1 1 1 1

1 1 1 1

1

1 1 1

1

1

1

A B C Y7’ Y6’ Y5’ Y4’ Y3’ Y2’ Y1’ Y0’

Encoder vs. Decoder8 3 Encoder

I0

I7

I6

I5

I4

I3

I2

I1

I4 I5 I6 I7 Y0 Y1 Y2I0 I1 I2 I3

00

1 10

00000

01

11

11

11

1

00000

0000

000

00 0

00000

0

0

00000

000000

000000

0000

000

0 0 0010 000 110 1

1 0 0110

11 1

0

Y2

Y0

Y1

Encoder vs. Decoder3 8 Decoder

I0

I7

I6

I5

I4

I3

I2

I1

Y2

Y0

Y1

1 1

0 0010 000 110 1

1 0 0110

11 1

0

00

0

00000

01

11

11

11

1

00000

0000

000

000

00000

0

0

00000

000000

0 00000

0000

000

0

I4 I5 I6 I7Y0 Y1 Y2 I0 I1 I2 I3

What Goes on Inside a Decoder?Y0

Y1

Y2

I0 = Y0Y1Y2

I2 = Y0Y1Y2

I3 = Y0Y1Y2

I4 = Y0Y1Y2

I5 = Y0Y1Y2

I6 = Y0Y1Y2

I7 = Y0Y1Y2

I1 = Y0Y1Y2

Decoders

In this subject, you need to familiarize yourself with two types of decoders:74LS139 Dual 2-4 Line Decoder.74LS138 3-8 Line Decoder

Decoders are used to:Activate devices for use by µP.Memory, I/O interfacing.

74LS139 Dual 2-4 Line Decoder

Motorola active low 2-4 decoder. 2 x decoders in one IC. 16 pins total:

2 x (2 inputs, 4 outputs).Vcc (±5V) and GND.2 x Enable pins.

Adobe Acrobat 7.0 Document

74LS139 Dual 2-4 Line Decoder

Ea

A0a

A1a

O0a

O1a

O2a

O3a

Eb

A0b

A1b

O0b

O1b

O2b

O3b

74LS139 Truth Table

E I0I1 O3 O0O1O2

1 XX 1 111

0 00 1 011

0 10 1 101

0 01 1 110

0 11 0 111

74LS138 3-8 Line Decoder

Motorola 3-8 active low decoder. 1 x decoder in one IC. 16 pins total:

3 inputs, 8 outputs (active low).Vcc (±5V) and GND.3 x Enable pins.

Adobe Acrobat 7.0 Document

74LS138 3-8 Line Decoder

E1

A0

A1

O0

O1

O2

O3

O4

O5

O6

O7

E2

E3

A2

E1 I0I1 O3 O0O1O2

1 XX 1 111

X XX 1 111

X XX 1 111

0 00 1 011

0 10 1 101

E2

X

1

X

0

0

E3

X

X

0

1

1

I2

X

X

X

0

0

O7 O4O5O6

1 111

1 111

1 111

1 111

1 111

0 01 1 1100 1 0 1 111

0 11 0 1110 1 0 1 111

0 00 1 111

0 10 1 111

0

0

1

1

1

1

1 011

1 101

0 01 1 1110 1 1 1 110

0 11 1 1110 1 1 0 11174LS

138

Tru

th T

able

Conclusion

Conclusion

Gates: most basic elements in circuits. Gates can be extended to perform

advanced functions. Some types are universal (NAND, NOR).

Conclusion

Flip-flops can store data – feedback:Can store previous data.

Decoders transform code into original signals.Used in memory interfacing (Chapter 4).

Tutorial

Tutorial

Name the three basic gates. What are extended gates? What’s the

difference between extended gates and basic gates?

What is the flip-flop used for?

Tutorial

Describe the RS, JK, D and Asynchronous flip-flops and draw the truth tables for them.

Why are NAND and NOR gates called universal gates? Why are they special?

Tutorial

Give the definition of decoder. Draw the truth table of the 74LS138 and

74LS139 decoder.

The End