1

1

EE 459/500 – HDL Based Digital

Design with Programmable Logic

Lecture 16

Timing and Clock Issues

Overview

Sequential system timing requirements

Impact of clock skew on timing

Impact of clock jitter on timing

Clock distribution

2

2

Clocked Synchronous State Machine

Flip-Flop Timing Parameters

3

Latch Timing Parameters

State Machine Timing

4

Satisfying Timing Requirements

The period must be long enough for the data to propagate through the registers and logic and to be set up at the destination register before the next rising edge of the clock. Satisfied by making T long enough. Cycle time: TCLK > tc-q + tlogic + tsu

The hold time at the destination register must be shorter than

the minimum propagation delay through the logic network. This requirement is independent of system clock; manufacturer’s minimum delay specifications are needed. Guarantee that minimum combinational logic delay is larger than hold time. Race margin: thold < tc-q,cd + tlogic,cd

Clock Uncertainties

2

4

3

Power Supply

Interconnect

5 Temperature

6 Capacitive Load

7 Coupling to Adjacent Lines

1 Clock Generation

Devices

5

Clock Nonidealities

Clock Skew

• Spatial variations in equivalent clock edges

• Mostly deterministic

Clock Jitter

• Temporal variations in consecutive clock edges

• Mostly random

Pulse Width Variation

Clock Skew and Clock Jitter

Clk

Clk

tSK

tJS

Clock skew and jitter can affect the cycle times

Clock skew can cause race conditions

6

Overview

Sequential system timing requirements

Impact of clock skew on timing

Impact of clock jitter on timing

Clock distribution

Clock Skew

Bad design

7

Clock Skew

Clock Skew

R1

D QCombinational

Logic

In

CLK tCLK1

R2

D Q

tCLK2

tc - qtc - q, cdtsu, thold

tlogictlogic, cd

Assume the following timing parameters are available:

Contamination or minimum delay (tc-q,cd) and maximum

propagation delay (tc-q) of the register

Setup (tsu) and Hold (thold) times for registers

Contamination delay (tlogic,cd) and maximum delay (tlogic) of the

combinational logic

The positions of the rising edges of clocks CLK1 and CLK2 (tCLK1

and tCLK2) relative to a global reference. Ideally tCLK1 = tCLK2.

8

Positive Clock Skew

Launching edge arrives before the

receiving edge

Minimum clock cycle:

T+ tc-q + tlogic + tsu

R1

D QCombinational

Logic

In

CLK tCLK1

R2

D Q

tCLK2

tc - qtc - q, cdtsu, thold

tlogictlogic, cd

Negative Clock Skew

Receiving edge arrives before the

launching edge

Minimum clock cycle:

T+ tc-q + tlogic + tsu

R1

D Q Combinational

Logic

In

CLK

t CLK1

R2

D Q

t CLK2

t c - q t c - q, cd t su, t hold

t logic t logic, cd

9

Positive and Negative Clock Skew

Impact of Clock Skew on Timing:

Cycle Time (Long Path)

10

Impact of Clock Skew on Timing:

Race Margin (Short Path)

Overview

Sequential system timing requirements

Impact of clock skew on timing

Impact of clock jitter on timing

Clock distribution

11

Clock Jitter

CLK

-tji tter

TC LK

t j itter

CLK

InCombinational

Logic

tc-q , tc-q, cd

t log ict log ic, cd

tsu, thold

REGS

tjitter

TCLK - 2tjitter tc-q + tlogic + tsu

2tjitter+ thold < tc-q,cd + tlogic,cd

Impact of Clock Jitter on Timing:

Cycle Time (Late-Early Problem)

12

Impact of Clock Jitter on Timing

Impact of Clock Skew and Jitter:

Cycle Time (Late-Early Problem)

13

Impact of Clock Skew and Jitter:

Race Margin (Early-Late Problem)

Combined Impact of Clock Skew and Jitter

Minimum clock cycle (cycle time)

• TCLK > tc-q + tlogic + tsu - + 2tjitter

Positive skew improves performance

Negative skew reduces performance

Jitter reduces performance

Minimum logic delay (race)

• tlogic,cd + tc-q,cd > thold + + 2tjitter

Skew reduces race margin

Jitter reduces acceptable skew

Notes:

Absolute delay through a clock distribution path is not important

What matters is the relative arrival time at the register points at

the end of each path

14

Overview

Sequential system timing requirements

Impact of clock skew on timing

Impact of clock jitter on timing

Clock distribution

Dealing with Clock Skew and Jitter

Balance clock paths (tree distribution)

Don’t use gated clocks

Use negative skew to eliminate race conditions (at the cost of performance): • Add up the components that result in the time

budget - the period must be greater than this value

TCLK > tc-q + tlogic + tsu - ( <0)

15

Clock Distribution

Clock Distribution

Distribute clock in a tree fashion

H-Tree

CLK

16

More Realistic H-Trees

Example: EV6 (Alpha 21264) Clocking

600 MHz – 0.35 micron CMOS

17

Spartan-6 FPGA

Spartan-6 FPGA Global Clock Network

18

Spartan-6 FPGA I/O Clock Network

Spartan-6 FPGA Clock Management Tile (CMT)

19

Digital Clock Manager (DCM)

Eliminating Clock Skew

20

Eliminating Clock Skew

Quadrant Phase Shifting

21

Fine Phase Shifting

Summary

Clock skew and clock jitter – increasingly

important issues with technology downscaling

CAD tools (e.g., ISE WebPack) take care of

many issues automatically

22

References and Credits

Chapter 10 of:

• Jan M. Rabaey, Anantha Chandrakasan, Borivoje

Nikolic, Digital Integrated Circuits, 2nd Edition,

Prentice Hall, 2003.

Spartan-6 FPGA Clocking Resources:

• http://www.xilinx.com/support/documentation/user

_guides/ug382.pdf

Appendix A: Asynchronous Inputs

23

Asynchronous Inputs: Multiple

Synchronizers