EFFICIENT ANALYSIS OF LARGE SCALE DIGITAL CIRCUITS AND PARASITIC INFORMATIONS

Dimitris Akridas, Electronics Lab, University of Thessaly

Key points of the analysis

● Parsing with Flex and Bison utilities.○ Very fast parsing, a necessary feature for large scale

designs.○ Lexical and syntax analysis of the Verilog and SPEF

language.● Graphical representation of the circuit.● Graphical representation of parasitics for each net in the circuit.● Exporting graphs to dot files.

○ The graphs can be visualised using a graph viewer like xdot.● Support of hierarchical designs in both verilog and spef

languages.

Parsing flow analysis

A hierarchical design

Exported graph from verilog files (visualised with xdot)

Look closer to a net

Interconnect modeling - RC parasitics

Exported net graph from spef file (visualised with xdot)

Performance on a real processor● Leon processor

○ Verilog file■ 164 MB■ 3,234,764 lines of verilog code■ 1,616,368 cells

○ Spef file■ 1,4 GB (spef files are much bigger than verilog)■ 48,807,933 lines of spef code

● Performance on i5-4590 CPU @ 3.30GHz○ Parsing verilog file

■ Process time 58.8203 seconds■ Memory usage 4.5386e+06 bytes

○ Parsing spef file■ Process time 210.058 seconds■ Memory usage 5.51672e+06 bytes

Developing Challenges - Memory Management

Old version of code with leon as input…

And killed!

35% of transition diagram for verilog lexical analyzer!

SPECIAL THANKS TOElectronics Lab - PHD candidates● Dimitris Garyfallou● Panagiotis Giannakou

Master student● Nikos Sketopoulos

Undergraduate Students● Giorgos Gkountouras● Dimitris Paraschas● Giorgos Varvarelis● Dimitris Evangelopoulos

Professors● Christos Sotiriou● Giorgos Dimitriou● Giorgos Stamoulis

Source code on github

github.com/dakridas/VerilogAPIgithub.com/dakridas/SpefAPI

THANKS!Any questions?

github.com/dakridasd.akridas@gmail.com