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Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
SRAM & DRAM
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
Read-Write Memories (RAM)
• STATIC (SRAM)
• DYNAMIC (DRAM)
Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferential
Periodic refresh requiredSmall (1-3 transistors/cell)SlowerSingle Ended
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
6-transistor CMOS SRAM Cell
VDD
Q
Q
M1 M3
M4M2
M5
BL
WL
BL
M6
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
CMOS SRAM Analysis (Write)
VDD
Q = 1Q = 0
M1
M4
M5
BL = 1
WL
BL = 0
M6
VDD
kn M6 VDD VTn– VDD
2----------- VDD
2
8-----------–
kp M4 VDD VTp– VDD
2----------- VDD
2
8-----------–
=
kn M5
2--------------
VDD
2----------- VTn
VDD
2-----------
–
2
kn M1 VDD VTn– VDD
2-----------
VDD2
8-----------–
= (W/L)n,M510 (W/L)n,M1
(W/L)n,M60.33 (W/L)p,M4
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
CMOS SRAM Analysis (Read)
VDD
Q = 1Q = 0
M1
M4
M5
BL
WL
BL
M6
VDDVDD
VDD
CbitCbit
kn M5
2---------------
VDD
2------------ VTn
VDD
2------------
–
2kn M1 VDD VTn–
VDD
2------------
VDD2
8------------–
=
(W/L)n,M510 (W/L)n,M1 (supercedes read constraint)
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
1-Transistor DRAM Cell
CSM1
BL
WL
CBL
WL
X
BL
VDD VT
VDD/2
VDD
GND
Write "1" Read "1"
sensingVDD/2
V VBL VPRE– VBIT VPRE– CS
CS CBL+------------------------= =
Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance
Voltage swing is small; typically around 250 mV.
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
DRAM Cell Observations
1T DRAM requires a sense amplifier for each bit line, due to
charge redistribution read-out.
DRAM memory cells are single ended in contrast to SRAM cells.
The read-out of the 1T DRAM cell is destructive; read and
refresh operations are necessary for correct operation.
Unlike 3T cell, 1T cell requires presence of an extra capacitance
that must be explicitly included in the design.
When writing a “1” into a DRAM cell, a threshold voltage is lost.
This charge loss can be circumvented by bootstrapping the
word lines to a higher value than VDD.
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
1-T DRAM Cell
(a) Cross-section
(b) Layout
Diffusedbit line
Polysiliconplate
M1 wordline
Capacitor
Polysilicongate
Metal word line
SiO2
n+ Field Oxide
Inversion layerinduced by plate bias
n+
poly
poly
Used Polysilicon-Diffusion Capacitance
Expensive in Area
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
Advanced 1T DRAM Cells
Cell Plate Si
Capacitor Insulator
Storage Node Poly
2nd Field Oxide
Refilling Poly
Si Substrate
Trench Cell Stacked-capacitor Cell
Capacitor dielectric layerCell plateWord line
Insulating Layer
IsolationTransfer gate
Storage electrode
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
Periphery
• Decoders
• Sense Amplifiers
• Input/Output Buffers
• Control / Timing Circuitry
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
Row DecodersCollection of 2M complex logic gatesOrganized in regular and dense fashion
(N)AND Decoder
NOR Decoder
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
Dynamic Decoders
WL3
GND GNDPrecharge devices
WL2
WL1
WL0
VDD A0 A0 A1 A1 A0 A0 A1 A1
VDD
VDD
VDD
VDD
WL3
WL2
WL1
WL0
Dynamic 2-to-4 NOR decoder 2-to-4 MOS dynamic NAND Decoder
Propagation delay is primary concern
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
4 input pass-transistor based column decoder
BL0 BL1 BL2 BL3
D
A0
A1
S0
S1
S2
S3 2 i
np
ut N
OR
dec
oder
Advantage: speed (tpd does not add to overall memory access time)
Disadvantage: large transistor countonly 1 extra transistor in signal path
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
4-to-1 tree based column decoder
BL0 BL1 BL2 BL3
D
A0
A0
A1
A1
Number of devices drastically reducedDelay increases quadratically with # of sections; prohibitive for large decoders
buffersprogressive sizingcombination of tree and pass transistor approaches
Solutions:
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
Sense Amplifiers
tpC V
Iav----------------=
make V as smallas possible
smalllarge
Idea: Use Sense Amplifer
outputinput
s.a.smalltransition
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
Differential Sensing - SRAM
Diff.SenseAmp
BLBL
SRAM cell i
x x
y yD D
VDDVDD
WLi
PC
EQ
VDD
x x
y
SE
VDD
xx
y
SE
VDD
x x
y
SE
(b) Doubled-ended Current Mirror Amplifier
y
(a) SRAM sensing scheme.(c) Cross-Coupled Amplifier
M1 M2
M4M3
M5
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
Latch-Based Sense Amplifier
VDD
BL
SE
SE
BLEQ
Initialized in its meta-stable point with EQOnce adequate voltage gap created, sense amp enabled with SEPositive feedback quickly forces output to a stable operating point.
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
Open bitline architecture
VDD
SE
SE
CS CS CS
L
...CSCS
...CS
R
BLL BLR
L0L1 R0 R1
dummycell
dummycell
EQ
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
DRAM Read Process with Dummy Cell
0 1 2 3 4 5t (nsec)
0.0
2.0
4.0
6.0
V (
Vo
lt)
0 1 2 3 4 5t (nsec)
0.0
2.0
4.0
6.0
V (
Vo
lt)
0 1 2 3 4 50.0
1.0
2.0
3.0
4.0
5.0
V (
Vo
lt)
EQ
WLSE
BL
BL
BL
BL
(a) reading a zero
(b) reading a one
(c) control signals
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
Open Bit-line Architecture —Cross Coupling
Sense
AmplifierC C CCCC
WL1 WL0 WLD WLD WL0 WL1
EQ
CWBLCWBL
CBL
BL
CBL
BL
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
Alpha-particles
WL
BL
VDD
n+SiO2
-particle
1 particle ~ 1 million carriers
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
Yield
Yield curves at different stages of process maturity(from [Veendrick92])
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
Redundancy
Memory
Array
Redundant
columns
Redundant
rows
Column Decoder
Row
Dec
oder
Row
Address
Column
Address
Fuse
Bank:
Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003
SRAM & DRAM
Redundancy and Error Correction