Post on 17-Dec-2015
transcript
EXECUTION UNIT
BUSINTERFACE UNIT
SYSTEM BUS
INSTRUCTIONPIPELINE
GENERALREGISTERS
SEGMENTREGISTERS
INSTRUCTIONQUEUE
ADDRESSGENERATION &BUS CONTROL
OPERANDS
FLAGS
INSTRUCTIONPOINTER
ALU
BUS INTERFACE UNIT(BIU)EXECUTION UNIT(EU)
MULTIPLEXED BUS
INTERNAL ARCHITECTURE OF 8088/8086 MICRPPROCESSOR
FETCH FIRST INST
EXECUTEFIRST INST
FETCH SECOND
INST
EXECUTESECOND
INST
EXECUTETHIRD INST
WRITERESULT
FETCH FOURTH
INST
FETCH THIRD INST
READ OPERAND
EU
BIU
PIPELINED ARCHITECTURE
SOFTWARE MODEL OF 8088/8086 MPU
8088/8086 MPU
IP
CS
DSSS
ES
AH AL
BH BL
CH CL
DH DL
SPBPSIDI
SR
INPUT/OUTPUTADDRESS SPACE
FFFFH
0000H
FFFFFH
OOOOOH EXTERNAL MEMORYADDRESS SPACE
EXRA SEGMENT(64 K BYTES)
CODE SEGMENT(64 K BYTES)
DATA SEGMENT(64K BYTES)
STACK SEGMENT(64 K BYTES)
BYTE 8
BYTE 7
BYTE 5
BYTE 6
BYTE 4
BYTE 1
BYTE 0
BYTE 3
BYTE 2
PHYSICALMEMORY
ADDRESS ALIGNEDWORDS
MISALIGNEDWORDS
00000H
00001H
0002H
00003H
00004H
00005H
00006H
00007H
00008H
WORD 6
WORD 4
WORD 2
WORD 0
WORD 1
WORD 5
BYTE 8
BYTE 7
BYTE 5
BYTE 6
BYTE 4
BYTE 1
BYTE 0
BYTE 3
BYTE 2
PHYSICALMEMORY
ADDRESS ALIGNEDDOUBLEWORDS
MISALIGNEDDOUBLE WORDS
00000H
00001H
0002H
00003H
00004H
00005H
00006H
00007H
00008H
DOUBLE WORD 4
DOUBLE WORD 2
DOUBLE WORD 0
DOUBLE WORD 1
DOUBLE WORD 5
DOUBLE WORD 3
BX
AX
DX
CX
ACCUMULATOR
BASE
COUNT
DATA
AH AL
DH DL
CH CL
BH BL
H L015 78
Register Operations
AX WORLD MULTIPLY, WORD DIVIDE, WORD I/O
AL BYTE MULTIPLY, BYTE DIVIDE, I/O TRANSLATE,DECIMAL ARITHMETIC
AH BYTE MULTIPLY, BYTE DIVIDE
BX TRANSLATE
CX STRING OPERATIONS, LOOPS
CL VARIABLE SHIFT AND ROTATE
DX WORLD MULTIPLY, WORD DIVIDE, INDIRECT I/O
SP
SI
BP
DI
015
STACK POINTER
BASE POINTER
SOURCE INDEX
DESTINATION INDEX
TYPE OF REFERENCE DEFAULT ALTERNATE OFFSET SEGMENT SEGMENT
INSTRUCTION FETCH CS NONE IP
STACK OPERATION SS NONE SP
DATA DS CS, ES OR SS VARIOUS
STRING SOURCE DS CS, ES OR SS SI
STRING DESTINATION ES NONE DI
BP USED AS ABASE REGISTER SS CS, ES OR SS VARIOUS
DEFAUT & ALTERNATE ADDRESS SOURCES
DFTF IF OF AFZFSF CFPF
CARRY
PARITY
STATUS OR FLAG REGISTER
AUXIIARY FLAG
ZERO
SIGN
OVERFLOW
INTERRUPT ENABLE
DIRECTION
TRAP
FLAG MEANING SET RESET
OF OVERFLOW OV (OVERFLOW) NV (NO OVERFLOW)
DF DIRECTION DN (DOWN) UP (UP)
IF INTERUPT EI (ENABLE INT) DI (DISABLE INT)
SF SIGN NG (NEGATIVE) PL (PLUS)
ZF ZERO ZR (ZERO) NZ (NOT ZERO)
AF AUXILIARY FLAG AC (AUX FLAG) NA (NO AUX FLAG)
PF PARITY PE (EVEN PARITY) PO (ODD PARITY)
CF CARRY CY (CARRY) NC (NO CARRY)
TF TRAP SINGLE-STEP MODE
SEGMENT REGISTER 0 0 0 0
20 BIT PHYSICAL MEMORY ADDRESS
OFFSET VALUE
ADDER
SEGMENT ADDRESS
OFFSET
GENERATING A PHYSICAL ADDRESS
015
015
019
XXXX
ABCD
0100
0000
8088 MPU
CS
DS
SS
ES
AX
BX
CX
DX
SP
BP
SI
DI
IP
INSTRUCTIONADDRESS
MEMORY CONTENTS
01000
01001
8B
C3
01002 XX
MOV AX,BX
NEXT INSTRUCTION
FIG. 1.1 (a)REGISTER ADDRESSINGMODE INSTRUCTION BEFORE FETCH AND EXECUTION
ABCD
ABCD
0100
0002
8088 MPU
CS
DS
SS
ES
AX
BX
CX
DX
SP
BP
SI
DI
IP
INSTRUCTIONADDRESS
MEMORY CONTENTS
01000
01001
8B
C3
01002 XX
MOV AX,BX
NEXT INSTRUCTION
FIG. 1.1 (b)REGISTER ADDRESSING MODE INSTRUCTION AFTER EXECUTION
XX
0100
0000
8088 MPU
CS
DS
SS
ES
AX
BX
CX
DX
SP
BP
SI
DI
IP
INSTRUCTIONADDRESS
MEMORY CONTENTS
01000
01001
B0
15
01002 XX
MOV AL,15H
NEXT INSTRUCTION
FIG. 1.2 (a)IMMEDIATE ADDRESSINGMODE INSTRUCTION BEFORE FETCH AND EXECUTION
01003 XX
15
0100
0002
8088 MPU
CS
DS
SS
ES
AX
BX
CX
DX
SP
BP
SI
DI
IP
INSTRUCTIONADDRESS
MEMORY CONTENTS
01000
01001
B0
15
01002 XX
MOV AL,15H
NEXT INSTRUCTION
FIG. 1.2 (b)IMMEDIATE ADDRESSINGMODE INSTRUCTIONAFTER EXECUTION
01003 XX
xxxx
0100
0200
0000
8088 MPU
CS
DS
SS
ES
AX
BX
CX
DX
SP
BP
SI
DI
IP
INSTRUCTIONADDRESS
MEMORY CONTENTS
01000
01001
8B
0E
01002 34
MOV CX, [1234H]
NEXT INSTRUCTION
FIG. 1.4 (a)DIRECT ADDRESSINGMODE INSTRUCTION BEFORE FETCH AND EXECUTION
01003
01004
12
XX
02000
02001
XX
XX
03234
03225
ED
BE
.
.
.
SOURCE OPERAND
BEED
0100
0200
0004
8088 MPU
CS
DS
SS
ES
AX
BX
CX
DX
SP
BP
SI
DI
IP
INSTRUCTIONADDRESS
MEMORY CONTENTS
01000
01001
8B
0E
01002 34
MOV CX, [1234H]
NEXT INSTRUCTION
FIG. 1.4 (b)DIRECT ADDRESSINGMODE INSTRUCTION AFTER EXECUTION
01003
01004
12
XX
02000
02001
XX
XX
03234
03225
ED
BE
.
.
.
SOURCE OPERAND
1234
0100
0200
0000
8088 MPU
CS
DS
SS
ES
AX
BX
CX
DX
SP
BP
SI
DI
IP
INSTRUCTIONADDRESS
MEMORY CONTENTS
01000
01001
8B
04
01002
MOV AX, [SI]
NEXT INSTRUCTION
FIG. 1.5 (a)REGISTER INDIRECTADDRESSING MODE INSTRUCTION BEFOREFETCH & EXECUTION
XX
02000
02001
XX
XX
03234
03235
ED
BE
.
.
.
SOURCE OPERAND
XXXX
1234
0100
0200
0002
8088 MPU
CS
DS
SS
ES
AX
BX
CX
DX
SP
BP
SI
DI
IP
INSTRUCTIONADDRESS
MEMORY CONTENTS
01000
01001
8B
04
01002
MOV AX, [SI]
NEXT INSTRUCTION
FIG. 1.5 (b)REGISTER INDIRECTADDRESSING MODE INSTRUCTION AFTEREXECUTION
XX
02000
02001
XX
XX
03234
03235
ED
BE
.
.
.BEED
0100
0200
0000
8088 MPU
CS
DS
SS
ES
AX
BX
CX
DX
SP
BP
SI
DI
IP
INSTRUCTIONADDRESS
MEMORY CONTENTS
01000
01001
88
87
01002
MOV [BX]+1234H,AL
NEXT INSTRUCTION
INSTRUCTION USING DIRECT BASE POINTER ADDRESSING MODE BEFORE FETCH ANDEXECUTION
XX
02000
02001
XX
XX
04234
04235
XX
XX
.
.
.BE ED
01003
34
12
01004
1000
0100
0200
0000
8088 MPU
CS
DS
SS
ES
AX
BX
CX
DX
SP
BP
SI
DI
IP
INSTRUCTIONADDRESS
MEMORY CONTENTS
01000
01001
88
87
01002
MOV [BX]+1234H,AL
NEXT INSTRUCTION
INSTRUCTION USING DIRECT BASE POINTER ADDRESSING MODE AFTER EXECUTION
XX
02000
02001
XX
XX
04234
04235
ED
XX
.
.
.BE ED
01003
34
12
01004
1000
D W
MOD REG R/MOPCODE
BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6
LOW DISP/DATA
HIGH DISP/DATA
LOW DATA
HIGH DATA
DIRECTION BITD=1 FOR DESTINATION OPERANDD=0 FOR SOURCE OPERAND
DATA SIZE BITW=1 WORD OPERATIONW=0 BYTE OPERATION
REG
000001010011100101110111
W=0
ALCLDLBLAHCHDHBH
W=1
AXCXDXBXSPBPSIDI
REGISTER (REG) FIELD CODING
MODE=11 EFFECTIVE ADDRESS CALCULATION
R/M
000001010011100101110111
REGISTER/MEMORY (R/M) FIELD ENCODING
W=0
AL CL DL BL AH CH DH BH
W=1
AX CX DX BX SP BP SI DI
R/M
000001010011100101110111
MOD=00
(BX)+(SI)(BX)+(DI)(BP)+(SI)(BP)+(DI)(SI)(DI)DIRECT ADDRESS(BX)
MOD=01
(BX)+(SI)+D8(BX)+(DI)+D8(BP)+(SI)+D8(BP)+(DI)+D8(SI) )+D8(DI) )+D8(BP)+D8(BX)+D8
MOD=10
(BX)+(SI)+D16(BX)+(DI)+D16(BP)+(SI)+D16(BP)+(DI)+D16(SI)+D16(DI)+D16(BP)+D16(BX)+D16
CODE
00
01
10
11
EXPLANATION
MEMORY MODE, NO DISPLACEMENT
MEMORY MODE, 8-BITDISPLACEMENT FOLLOWS
MEMORY MODE, 16-BITDISPLACEMENT FOLLOWS
REGISTER MODE. (NODISPLACEMENT)
MODE (MOD) FIELD ENCODING
REGISTER
ES
CS
SS
DS
SR
00
01
10
11
SEGMENT REGISTER CODES
FIELD
S
V
Z
VALUE
01
01
01
FUNCTION
NO SIGN EXTENSIONSIGN EXTEND 8-BIT IMMEDIATE DATA TO 16-BITS IF W=1
SHIFT/ ROTATE COUNT IS ONESHIFT/ ROTATE COUNT IS SPECIFIED IN CL REGISTER
REPEAT/LOOP WHILE ZERO FLAG IS CLEARREPEAT/LOOP WHILE ZERO FLAG IS SET
ADDITIONAL 1-BIT FIELDS & THEIR FUNCTIONS
Symbol Register
AX Accumulator Register BX Base Register CX Count Register DX Data Register SI Source Index Register DI Destination Index Register SP Stack Pointer Register BP Base Pointer Register CS Code Segment Register DS Data Segment Register SS Stack Segment Register ES Extra Segment Register F Flag SRegister IP Instruction Pointer
Register mnemonics for the R command
Addition ADD Add byte or wordADC Add byte or word with carryINC Increment byte or word by 1AAA ASCII adjust for additionDAA Decimal adjust for addition
SubtractionSUB Subtract byte or wordSBB Subtract byte or word with borrowDEC Decrement byte or word by 1NEG Negate byte or wordAAS ASCII adjust for subtractionDAS Decimal adjust for subtraction
MultiplicationMUL Multiply byte or word unsignedIMUL Integer multiply byte or wordAAM ASCII adjust for multiply
Division DIV Divide byte or word unsignedIDIV Integer divide byte or word unsignedAAD ASCII adjust for divisionCBW Convert byte to wordCWD Convert word to double word
Arithmetic Instructions
Mnemonics Meaning Format Operation Flags affected
MOV Move MOV D,S (S) (D) None
MOV data transfer instruction
Destination Source
Memory Accumulator Accumulator Memory Register Register Register Memory Memory Register Register Immediate Memory Immediate Seg-reg Reg16 Seg-reg Mem16 Reg16 Seg-reg Memory Seg-reg
Allowed Operands
Mnemonics Meaning Format Operation Flags affected
Xlate Translate XLAT ((AL)+(BX)+(DS)0 (AL) None
Xlate data transfer instruction
Mnemonics Meaning Format Operation Flags affected
XCHG Exchange XCHG D,S (D) (S) None
Exchange data transfer instruction
Destination Source
Accumulator Reg16 Memory Register Register Register Register Memory
Allowed Operands
1 1 0 0 0 1 1 W MOD 0 0 0 R/M DISP-LO DISP-HI DATA DATA IF W=1IMMEDIATE TOREGISTER/MEMORY
DISP-HI
DISP-HI
1 0 1 1 W REG DATA DATA IF W=1IMMEDIATE TOREGISTER
1 0 1 0 0 0 W ADDR-LO ADDR-HIMEMORY TOACCUMULATOR
1 0 0 0 1 1 1 0 MOD 0 SR R/M DISP-LO
1 0 0 0 1 1 0 0 MOD 0 SR R/M DISP-LO
REGISTER/MEMORY TOSEGMENT REG
SEGMENT REGTO REGISTER/MEMORY
MOVE COMMANDS
Memory(EBCDIC)
00..F0F1F2F3F4F5F6F7F8F97A 4C7E6E6F7CC1C2C3C4C5
ADDRESS
03100
03110
0313F
03141
0123456789:;<=?@ABCDE
NULL
CHARACTER
0300
0100
XX3F
XX6F
DS
BX
AX
AX
BEFOREEXECUTION
AFTEREXECUTION
ASCII to EBCDICConversion operation(Translate Instruction)
Mnemonic Meaning Format Operation Flags affected
LEA Load effective address LEA Reg16,EA EA (Reg16) None
LDS Load register and DS LDS Reg16,Mem32 (Mem32 ) (Reg16) None (Mem32+2) (DS)
LES Load register and ES LES Reg16,Mem32 (Mem32) (Reg16) None (Mem32+2) (ES)
LEA, LDS & LES Instructions
XXXX
1100
1200
0100
8088 MPU
CS
DS
SS
ES
AX
BX
CX
DX
SP
BP
SI
DI
IP
INSTRUCTIONADDRESS
MEMORY CONTENTS
11100
11101
C5
36
11102 00
LDS SI , [200H]
NEXT INSTRUCTION
FIG. LDS INSTRUCTION BEFORE FETCH AND EXECUTION
11103
11104
02
XX
12000
12001
XX
XX
12200
12201
20
00
.
.
.
12202
12203
00
13
0020
1100
1300
0104
8088 MPU
CS
DS
SS
ES
AX
BX
CX
DX
SP
BP
SI
DI
IP
INSTRUCTIONADDRESS
MEMORY CONTENTS
11100
11101
C5
36
11102 00
LDS SI , [200H]
NEXT INSTRUCTION
FIG. LDS INSTRUCTION AFTER EXECUTION
11103
11104
02
XX
12000
12001
XX
XX
12200
12201
20
00
.
.
.
12202
12203
00
13.
13000 XX13001 XX
0 0 0 0 0 0 D W MOD REG R/M DISP-LO DISP-LOREG/MEM WITH REGTO EITHER
1 0 0 0 0 0 D W MOD REG R/M DISP-LO DISP-LO DATA DATA IF W=1IMMEDIATE TOREG/MEM
0 0 0 0 0 1 0 W DATA DATA IF W=1IMMEDIATE TO ACCUMULATOR
ADD INSTRUCTIONS
Mnemonic Meaning Format Operation Flags affected
CMP Compare CMP D, S (D) (S) is used OF, SF, ZF, AF, PF, CF in setting or resetting
the flags
Compare Instruction
Destination Source
Register RegisterRegister MemoryMemory RegisterRegister ImmediateMemory ImmediateAccumulator Immediate Allowed Operand
Mnemonic Meaning Format Operation Flags affected
jMP Unconditional JMP Operand Jump is initiated None jump to the address specified by the operand
Unconditional jump Instruction
Operands
Short – LabelNear – LabelFar – LabelMemptr 16Regptr 16Memptr 32 Allowed Operand
Mnemonic Meaning Format Operation Flags affected
jcc Conditional Jcc Operand If the specified condition cc None jump is true the jump to the address specified by the operand is initiated; otherwise the next instruction is executed
Conditional jump Instruction
Mnemonic Meaning Format Operation Flags affected
CALL Subroutine call CALL Operand Execution continues from None address of the subroutine specified by the operand. Information required to return back to the main program such as IP and CS are saved on the stack
Subroutine call Instruction
Allowed Operand
Operand
Near-procFar-procMemptr16Regptr16Memptr32
Mnemonic Meaning Condition
JA Above CF=0 and ZF=0JAE Above or equal CF=0JB below CF=1JBE Below or equal CF=1 or ZF=1JC Carry CF=1JCXZ CX reg is zero (CF or ZF)=0JE Equal ZF=1JG greater ZF=0 & SF=OFJGE Greater or equal SF=OFJL Less (SF xor OF)=1JLE Less or equal ((S Fxor OF)orZF=1JNA not above CF=1 or ZF=1 JNAE not above nor equal CF=1 JNB not below CF=0 JNBE not above nor equal CF=0 & ZF=0JNC not carry CF=0JNE not equal ZF=0JNG not greater ((SF xor OF)orZF=1JNG not greater or equal (SF xor OF)=1JNL not less SF=OF JNLE not less or equal ZF=0 & SF=OFJNO not overflow OF=0JNP not parity PF=0JNS not sign SF=0JNZ not zero ZF=0JO overflow OF=1JP parity PF=1JPE parity even PF=1JPO parity odd PF=0JS Sign SF=1JZ zero ZF=1
Conditional Jump Instructions
Main Program
Call Subroutine A
Next instruction
.
.
.
.
.
.
.
.
Call Subroutine A
Next Instruction....
Subroutine A
First instruction
Return
Subroutine concept
Mnemonic Meaning Format Operation Flags affected
ADD Addition ADD D, S (S)+(D) (D) OF, SF, ZF, AF, PF, CF Carry (CF) ADC Add with carry ADC D, S (S)+(D) + (CF) (D) OF, SF, ZF, AF, PF, CF Carry (CF)
INC Increment by 1 INC D (D) + 1 (D) OF, SF, ZF, AF, PF,
AAA ASCII adjust AAA AF, CF for addition OF, SF, ZF, PF undefined
DAA Decimal adjust DAA SF, ZF, AF, PF, CF for addition OF, Undefined
Addition Instructions
Destination Source
Register RegisterRegister MemoryMemory RegisterRegister ImmediateMemory ImmediateAccumulator Immediate
Allowed OperandFor Addition
Destination
Reg16Reg8Memory
Allowed Operand For Increment
Mnemonic Meaning Format Operation Flags affected
SUB Subtract SUB D, S (D)-(S) (D) OF, SF, ZF, AF, PF, CF Borrow (CF) SBB Subtract with ADC D, S (D) - (S) - (CF) (D) OF, SF, ZF, AF, PF, CF Borrow DEC Decrement by 1 INC D (D) - 1 (D) OF, SF, ZF, AF, PF, NEG Negate NEG D 0-(D) (D) OF SF, ZF, AF, PF, CF 1 (CF)DAS Decimal adjust DAS SF, ZF, AF, PF, CF for subtraction OF, Undefined AAS ASCII adjust AAS AF, CF for subtraction OF, SF, ZF, PF undefined
Subtraction Instructions
Destination Source
Register RegisterRegister MemoryMemory RegisterRegister ImmediateMemory ImmediateAccumulator Immediate
Allowed OperandFor Subtraction Instruction
Destination
Reg16Reg8Memory
Allowed Operand For DecrementInstruction
Destination
RegisterMemory
Allowed Operand forNEG instruction
Mnemonic Meaning Format Operation Flags affected
MUL Multiply MUL S (AL) . (S8) (AX) OF, CF (unsigned) (AX . (S16) (DX),(AX) SF, ZF, AF, PF undefined DIV Division DIV S (1) Q((AX)/(S8) (AL) OF, SF, ZF, AF, PF, CF (unsigned) R((AX)/(S8) (AH) undefined (2) Q((DX,AX)/(S16) (AX) R((DX,AX)/(S16) (DX If Q is FFH in case (1) or FFFFH in case (2), then type 0 interrupt occurs IMUL Integer Multiply IMUL S (AL) . (S8) (AX) OF, SF, ZF, AF, PF,CF (signed) (AX) . (S16) (DX),(AX) undefined
IDIV Integer divide IDIV S (1) Q((AX)/(S8) (AL) (signed) R((AX)/(S8) (AH) (2) Q((DX,AX)/(S16) (AX) R((DX,AX)/(S16) (DX If Q is positive and exceeds 7FFFH or if Q is negative and becomes less than 8001H then type 0 interrupt occursAAM Adjust AL for AAM Q((AL)/10) (AH) SF, ZF, , PF, multiplication R((AL)/10) (AL) OF, AF, CF Undefined AAD Adjust AX for AAD (AH).10+(AL) (AL) SF, ZF, PF division OF, AF, CF undefinedCBW Convert byte CBW (MSB of AL) (All bits of AH) None to wordCWD Convert word to CWD (MSB of AX) (All bits of DX) None double word
Multiplication & Division Instructions
MOV AX,2000H ; LOAD AX REGISTER
MOV DS,AX ; LOAD DATA SEGMENT ADDRESS
MOV SI,100H ; LOAD SOURCE BLOCK POINTER
MOV DI,120H ; LOAD DESTINATION BLOCK POINTER
MOV CX,10H ; LOAD REPEAT COUNTER
MOV AH,[SI] ; MOVE SOURCE BLOCK ELEMENT TO AH
MOV [DI],AH ; MOVE AH TO DESTINATION BLOCK
INC SI ; INCREMENT SOURCE BLOCK POINTER
INC DI ; INCREMENT DESTINATION BLOCK POINTER
DEC CX ; DECREMENT REPEAT COUNTER
JNZ NXTPT ; JUMP TO NXTPT IF CX NOT EQUAL TO ZERO
NOP ; NO OPERATION
NXTPT:
Part 1
JMP AA
Part II
UnconditionalJump Instruction
Locations skipped dueto jump
AA
Part III
Next Instructionexecuted
Unconditional jumpProgram sequence
Part 1
Jcc AAConditionalJump Instruction
Locations skipped dueif jumptaken
XXXXXX
Part II
Conditionmet
No
AA
XXXXXX
XXXXXX
Next instruction executed if condition not met
Yes
Next instructionExecuted ifCondition met
Conditional jump Program sequence
Mnemonic Meaning Operation Flags affected
LAHF Load AH from Flags (AH) (Flags) None SAHF Store AH into flags (Flags) (AH) SF, ZF, AF, PF, CF CLC Clear carry flag (CF) 0 CF
STC Set carry flag (CF) 1 CF
CMC Compliment carry flag (CF) (CF) CF
CLI Clear Interrupt flag (IF) 0 IF
STI Set Interrupt flag (IF) 1 IF
Flag Control Instructions
SF = Sign flagZF = Zero flagAF = Auxiliary flagPF = Parity flagCF = Carry flag
Mnemonic Meaning Format Operation Flags affected
AND Logical AND AND D, S (S)+(D) (D) OF, SF, ZF, PF, CF AF undefined OR Logical ADC D, S (S)+(D) (D) OF, SF, ZF, AF, PF, CF Inclusive-OR AF undefined
XOR Logical XOR D, S (S)+(D) (D) OF, SF, ZF, CF, PF Exclusive-OR AF undefined
NOT Logical NOT NOT D (D)’ (D) None
Logic Instructions
Destination Source
Register RegisterRegister MemoryMemory RegisterRegister ImmediateMemory ImmediateAccumulator Immediate
Allowed Operands for AND,OR, XOR Instruction
Destination
Register
Memory
Allowed Operand For NOT Instruction
Mnemonic Meaning Format Operation Flags affected
SAL/SHL Shift SAL/SHL D, Count Shift the (D) left by the number of OF, SF, ZF, PF, CF arithmetic bit positions equal to the count and left/shift fill the vacated bits positions OF undefined if count logical left on the right with zereos not equal to 1 SHR Shift SHR D, Count Shift the (D) right by the number of OF, SF, ZF, AF, PF, CF logical bit positions equal to count and AF undefined right fill the vacated bits positions OF undefined if count on the left with zereos not equal to1 SAR Shift SAR D, Count Shift the (D) right by the number of OF, SF, ZF, CF, PF arithmetic bit positions equal to count and AF undefined right fill the vacated bits positions on the left with the original most significant bit.
Shift Instructions
Destination Count
Register 1Register CLMemory 1 Memory CL
Target
Target
Target
Target
C
C
C
C
SHL
SAL
SHR
SAR
The four Shift operation available in 8088/8086 instruction set
0Logical left
0Arithmetic left
0
S
Logical right
Arithmetic right
SHL AX,1
0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
0
Bit 15 Bit 0
Bit 15 Bit 0
0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0
AXBefore
AX After
CF
SHR AX, CL Assume CL = 02
0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
00 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1
CF
AX
After
AX After
AX Before
Bit 15 Bit 0
Bit 15
0
0
SAR AX, CL Assume CL = 02H & AX=091AH
0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0
10 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0
CF
AX
After
AX After
AX Before
Bit 15 Bit 0
Bit 15 Bit 0
Mnemonic Meaning Format Operation Flags affected
ROL Rotate left ROL D, Count Rotate the (D) left by the number of CF bit positions equal to the count. Each bit shifted out from the leftmost OF undefined if count goes back into the rightmost bit posn, not equal to 1 ROR Rotate right ROR D, Count Rotate the (D) right by the number of CF logical bit positions equal to count. Each bit right shifted out from the rightmost bit goes OF undefined if count into the leftmost bit position not equal to1 RCL Rotate left RCL D, Count Same as ROL except carry is attached CF through carry (D) for rotation. OF undefined if count not equal to1RCR Rotate right RCR D, Count Same as ROL except carry is attached CF through carry (D) for rotation.
Rotate Instructions
Destination Count
Register 1Register CLMemory 1 Memory CL
Allowed Operands
Target
Target
Target
Target
C
C
C
C
ROL
RCL
ROR
RCR
The four rotate operation available in 8088/8086 instruction set
ROL AX,1
00 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
0
Bit 15 Bit 0
Bit 15 Bit 0
0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0
AXBefore
AX After
CF
CF
ROR AX, CL Assume CL = 04
0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 1
0
CF
CF
AX
After
AX After
AX Before
Bit 15 Bit 0
Bit 15
200H201H202H203H204H205H206H207H208H209H20AH20BH20CH20DH20EH20FH210H211H212H213H214H215H216H217H
MEM ADDR CONTENTS
B8H00H20H8EHD8HBEH00H01HBFH20H01HB9H10H00H8AH24H88H25H46H47H49H75HF7H90H
INSTRUCTION
MOVE AX,2000H
MOV DS,AX
MOV SI,100H
MOV DI,120H
MOV CX,10H
MOV AH,[SI]
MOV [DI],AH
INC SIINC DIDEC CXJNZ $-9
NOP
STORING THE MACHINE CODE IN MEMORY
GND-- 1 40 -- VccA14 -- 2 39 – A15A13 -- 3 38 – A16/S3A12 -- 4 37 -- A17/S4A11 -- 5 36 -- A18/S5A10 -- 6 35 -- A19/S6 A9 -- 7 34 -- SSO’ (HIGH) A8 -- 8 8088 33 -- MN/MX’ AD7– 9 CPU 32 --RD’ AD6– 10 31 --HOLD (RQ’/GT0’) AD5– 11 30 --HLDA (RQ’/GT1’) AD4– 12 29 --WR’ (LOCK’) AD3– 13 28 --IO/M’ (S2’) AD2– 14 27 --DT/R’ (S1’) AD1– 15 26 --DEN’ (S0’) AD0– 16 25 --ALE (QS0)NMI – 17 24 --INTA’ (QS1)INTR--18 23 --TEST’ Clk – 19 22 --READYGND– 20 21 --RESET
GND-- 1 40 – VccAD14 -- 2 39 – A15
AD13 -- 3 38 – A16/S3 AD12 -- 4 37 -- A17/S4 AD11 -- 5 36 -- A18/S5
AD10 -- 6 35 -- A19/S6 AD9 -- 7 34 -- BHE’/S7
AD8 -- 8 8086 33 -- MN/MX’AD7– 9 CPU 32 --RD’
AD6– 10 31 --HOLD (RQ’/GT0’) AD5– 11 30 --HLDA (RQ’/GT1’)
AD4– 12 29 --WR’ (LOCK’) AD3– 13 28 --M/IO’ (S2’)
AD2– 14 27 --DT/R’ (S1’) AD1– 15 26 --DEN’ (S0’)
AD0– 16 25 --ALE (QS0) NMI – 17 24 --INTA’ (QS1)
INTR--18 23 --TEST’ Clk – 19 22 --READY GND– 20 21 --RESET
Pin layout of 8088/8086 Microprocessor
Common Signals
Name Function Type
AD7-AD0 Address/Data bus Bidirectional 3-stateA15-A8 Address bus Output 3-stateA19/S6- Address/status OutputA16/S3 3-state
MN/MX’ Minimum/Maximum Input Mode controlRD’ Read Control Output 3-stateTEST’ Wait on test control Input
READY Wait state control Input
RESET System reset Input
NMI Nonmaskable Input Interrupt requestINTR Interrupt request Input
CLK System clock InputVcc +5 V Input
Minimum Mode signals (MN/MX’=Vcc )
Name Function Type
HOLD Hold request InputHLDA Hold acknowledge OutputWR’ Write Control Output 3-stateIO/M’ IO/memory control Output 3-stateDT/R’ Data tranmit/receive Output 3-stateDEN’ Data enable Output 3-stateSSO’ Status line Output 3-stateALE Address latch enable OutputINTA’ Interrupt acknowledge Output
Maximum mode signals (MN/MX’ =GND )Name Function Type
RQ’/GT1’,0’ Request/grant bus access control Bidirectional
LOCK’ Bus priority lock control Output(3-state)
S2’-S0’ Bus cycle status Output(3-state)
QS1,QS2 Instruction queue status Output
8088MPU
Vcc GND
Power supply
INTR
INTRA’
Address/data bus
AD0-AD7, A8-A15
A16/S3-A19/S8
ALE
Interrupt interface
TEST’
NMI
RESET
HOLD
HLDA
Vcc
DMAinterface
CLKClock
MN/MX’Modeselect
SSO’
IO/M’
DT/R’
RD’
WR’
DEN’
READY
Block diagram of minimum-mode 8088 MPU
Memory/IOcontrols
S4 S3 Address Status
0 0 Alternate (relative to the ES seg )
0 1 Stack (relative to the SS segment )
1 0 Code/None (relative to the ES seg or a default of zero)
1 1 Data (relative to the DS segment )
QS1 QS0 Queue Status
0(low) 0 No Operation. During the last clock cycle nothing was taken from the queue.0 1 First byte. The byte taken from the queue was the first byte of the instruction.1(high) 0 Queue empty. The queue has been reinitialized as a result of the execution of a transfer instruction.1 1 Subsequent Byte. The byte taken from was a subsequent byte of the instruction
Status Inputs
S2’ S1’ S0’ CPU Cycle 8288 Command
0 0 0 Interrupt acknowledge INTA’ 0 0 1 Read I/O Port IORC’ 0 1 0 Write I/O Port IOWC’, AIOWC’ 0 1 1 Halt None 1 0 0 Instruction Fetch MRDC’ 1 0 1 Read Memory MRDC’ 1 1 0 Write Memory MWTC’, MWTC’ 1 1 1 Passive None
Bus Status codes
Queue Status CodesBus Address Status
8086MPU
Vcc GND
Power supply
INTR
INTRA’
Address/data bus
AD0-AD7, A8-A15
A16/S3-A19/S8
ALE
Interrupt interface
TEST’
NMI
RESET
HOLD
HLDA
Vcc
DMAinterface
CLKClock
MN/MX’Modeselect
BHE’/S7
M/IO’
DT/R’
RD’
WR’
DEN’
READY
Block diagram of minimum-mode 8086 MPU
Memory/IOcontrols
8088MPU
MN/MX’
8088 Maximum- Mode Block Diagram
Vcc GNDCLK
Interruptinterface
INTR
TEST’
NMI
TEST’
CLK
MRDC’
MWTC’
AMWC
IORC’
IOWC
AIOWC’
INTA’
AEN’
CLK
S0’
S1’
S2’
S0’
S1’
S2’
MCE/PDEN’
ALE
DT/R’
DEN
QS1, QS0
Ready
RD’
LOCK’
8288 Buscontroller
AD0-AD7, A8-A15, A16/S3-A19/S6
AEN’
DEN
DT/RALE
RQ’/ RQ’/GT1’ GT0’
8088 Memory Interface/Control Signals ( Minimum-Mode)
8088
8088
8088 Memory Interface/Control Signals ( Maximum-Mode)
ALE
A8-A19
AD0-AD7
RD’
WR’
+5VMN/MX’
IO/M’
MemorySubsystemAnd busInterfacecircuitry
DT/R’
DEN’
SSO’
Bus Controller
8288 MemorySubsystemAnd busInterfacecircuitry
MN/MX’GND
CLK
S0’-S2’
MRDC’
MWTC’
ALE
DT/R’
DEN’
A8-A19
AD0-AD7
8088 System I/O Interface Signals ( Minimum-Mode)
8088
8088
8088 System I/O Interface Signals ( Maximum-Mode)
ALE
A8-A19
AD0-AD7
RD’
WR’
+5VMN/MX’
IO/M’
I/OInterfacecircuitry
DT/R’
DEN’
SSO’
Bus Controller
8288I/O
Interfacecircuitry
MN/MX’GND
CLK
S0’-S2’
IORC’
IOWC’
ALE
DT/R’
DEN’
A8-A19
AD0-AD7
I/O device 0
I/O device 1
I/O device N
.
.
.
.
.
Memory
Subsystem
And
I/O device 0
I/O device 0
I/O device 0
.
.
.
.
.
Mnemonic Meaning Format Operation
IN Input direct IN Acc, Port (Acc) (Port) Acc=AL or AX
Input indirect IN Acc, DX (Acc) ((DX)) (variable)
OUT Output direct OUT Port, Acc (Port) (Acc)
Output indirect OUT DX, Acc ((DX)) (Acc) (variable)
Input/Output Instructions
8088MPU
74373(2)
AddressLatch
74245Data bus
transceiver
74138I/O
Addressdecode
74374Port 0
CLK
OE’
VCC
MN/MX’
AD0-AD7
A0L – A15L
WR’
DT/R’
DEN’G’
DIR
IO/M’G2A’
G1
CBA
G2B’P0
P7
VCC
R1
LED
O7
O0
O1....
OE’
CLKA1L-A3L
A0L
A15L
AD0-AD7,A8-A15
ALE
Driving an LED connected to an output port.
74374Port 7
O1
.
.
.
.
.
.
.
.
.
.
CLK O56
O57
O63
P1.....
8088MPU
74373(2)
AddressLatch
74245Data bus
transceiver
74138I/O
Addressdecode
74244Port 0
CLK
OE’
VCC
MN/MX’
AD0-AD7
A0L – A15L
RD’’
DT/R’
DEN’G’
DIR
IO/M’G2A’
G1
CBA
G2B’P0
P7
VCC
R1
I7
I0
I1....
G’A1L-A3L
A0L
A15L
AD0-AD7,A8-A15
ALE
Reading the setting of a switch connected to an input port.
D0-D7
ON OFF
SWITCH