Post on 11-Feb-2016
description
transcript
FaridehShiran
Department of ElectronicsCarleton University, Ottawa, ON, Canada
fshiran@doe.carleton.ca
SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application
Processors
OutlineIntroductionFirst Generation 90 nm Second Generation 65 nm Third Generation 45 nm Design Methodology and Automation Low Power Standard: IEEE-1801Conclusion
OutlineIntroductionFirst Generation 90 nmSecond Generation 65 nm Third Generation 45 nm Design Methodology and Automation Low Power Standard: IEEE-1801Conclusion
IntroductionDemand for increasing features of
handheld devicesProcessors speeds reaching 1 GHz and
aboveBottleneck: battery technologyTrade-off: battery life versus higher speeds
Technology ScalingAdvantagesDisadvantagrs
Demand for Increased Mobile Product Features and Performance
Leakage Power in different technologies
Extend battery lifeCo-optimization: Process and circuitTexas Instruments (TI) for 90 nm, 65 nm,
45 nmSmartReflex
OutlineIntroductionFirst Generation 90 nm Second Generation 65 nm Third Generation 45 nm Design Methodology and Automation Low Power Standard: IEEE-1801Conclusion
90 nm Leakage Power Management
Exponential increase in leakage : Power gating
uses high Vt sleep transistors which cut off VDD from a circuit block
SRAM retentionLosing data stored in SRAM, retention needed
Multiple channel lengthReducing leakage power both in active and idle
modesOMAP2 Mobile Application Process
Integrate above techniques in a 90 nm technology
Power gating
Global/local power grid methodology
OutlineIntroductionFirst Generation 90 nm Second Generation 65 nm Third Generation 45 nm Design Methodology and Automation Low Power Standard: IEEE-1801Conclusion
65nm Power and PerformanceLarger increase in device leakageImproving SmartReflex power management
toolbox:Leakage power managementaggressive dynamic voltage frequency
scaling Process and temperature adaptive voltage
scaling
65 nm technology OMAP3430 application processor
OutlineIntroductionFirst Generation 90 nm Second Generation 65 nm Third Generation 45 nm Design Methodology and Automation Low Power Standard: IEEE-1801Conclusion
45 nm Power and Performance
Further reduction of active leakage power and performance increase Adaptive body bias (ABB):
FBBRBB
Retention Til Access (RTA)Full power stateLow power state
Single Chip 3.5 Baseband and Applications ProcessorIntegrate above techniques in a 45 nm technology
OutlineIntroductionFirst Generation 90 nm Second Generation 65 nm Third Generation 45 nm Design Methodology and Automation Low Power Standard: IEEE-1801Conclusion
Design methodology and automation
SmartReflex-PriMer (SmartPriMer): Chip-level leakage management design methodology
Power Managed (PM) modules
Power-Aware VerificationPM integrity checkPower-aware simulations at RTL and gate levels
Not power-awarePower-aware
OutlineIntroductionFirst Generation 90 nmSecond Generation 65 nm Third Generation 45 nm Design Methodology and Automation Low Power Standard: IEEE-1801Conclusion and Future Work
Low Power Standard: IEEE-1801
Unified Power Format (UPF): Why UPF?
PM intent informationUPF1.0: power design intent in verification and
implementationPower states Power domain specificationsRetention, Isolation and level shifting
UPF2.0-IEEE1801Command layeringSupply set handles
ConclusionsFor higher performance (power
management)
Three generation technologies 90nm, 65nm, 40nm
design methodology SmartReflex-PriMerPower-Aware Verification
StandardUPF 1.0UPF 2.0
Thank You