Figure 1.1 The Altera UP 3 FPGA Development board

Figure 1.2 The Altera UP 2 FPGA development board.

Figure 1.3 Design process for schematic or HDL entry.

Figure 1.4 Connections between the pushbuttons, the LEDs, and the Altera FPGA.

AlteraFlex

Device

+5V +5V+5V

PB1

PB2

LED

Figure 1.5a and 1.5b. Equivalent circuits for ORing active low inputs and outputs.

(a) (b)

Figure 1.6 Creating a new Quartus II Project.

Figure 1.7 Setting the FPGA Device Type.

Figure 1.8 Creating the top-level project schematic design file.

Figure 1.9 Selecting a new symbol with the Symbol Tool.

Figure 1.10 Active low OR-gate schematic example with I/O pins connected.

Table 1.1 Hardwired connections on the FPGA chips for the design.

I/O Device

UP 3 Pin Number Connections

UP 1 & UP 2 Pin Number Connections

PB1 62 (SW7) 28 (FLEX PB1)

PB2 48 (SW4) 29 (FLEX PB2)

LED 56 (D3) 14 (7Seg LED DEC. PT.)

Figure 1.11 Assigning Pins with the Assignment Editor.

Figure 1.12 Active low OR-gate timing simulation with time delays.

Figure 1.13 ALTERA UP 3 board showing

Pushbutton and LED locations used in design

Parallel PortVGAPort

B B B

Santa Cruz Expansion Long Connector

Santa Cruz Expansion Long Connector

Santa Cruz Expansion Long Connector

JP6

On/OffSwitch

PowerConnector

MountingHole

HeatSink

HeatSink

+5 VoltSupplyLED

+3.3 VoltSupplyLED

HeatSink B B

Flash

BReset

GlobalReset

4 User Definable DIP Switches (JP3)

4 Push Buttons

SRAM4 User

DefinableLEDs

Input ClockSetting Headers

Oscillator Chip

Cyclone FPGAEP1C6Q240C8

I2C PROMChip .....

Headersfor I2C

Bus SignalsUSB PHYChip

PS-2Port

USBPort

Invalid Volt. LED

JTAG & ASDownload

Connectors

“B”- Buffer Chips

Liquid Crystal Display

Real Time Clock

J5

J7

JP19

JP4LED

SerialChip

J3

J2 J4

J1

JP19

JP5

JP7JP3

SW7

SW6

SW5

SW4

D3

D4

D5

D6

LEDPushbuttons

Figure 1.14 ALTERA UP 2 board with jumper

settings and PB1, PB2, and LED locations

Chip Select Jumpers Decimal Point LED

FLEX Pushbuttons

FLEX_EXPAN_C

FLEX_10K

EPF10K20RC240-4 DAA239837

R

R

Mouse

25.175 MHzCLOCK

FLEX_EXPAN_AFLEX_PB1 FLEX_PB2

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

DC_IN FLEX_DIGIT

U1

JTAG_OUT

POWER TCK

MAX_SW1 MAX_SW2

EMP7128SLC84-7 BFD329837

R

R

VGAAdapter

P1

P2

P3P4

P9 P10P6P5

P7 P8

EPC

MAX FLEX

Table 1.2 Jumper settings for downloading to the UP2 MAX and FLEX devices.

Figure 1.15 UP 2’s FLEX FPGA pin connection to seven-segment display decimal point.

Pin 14

Figure 1.16 VHDL Entity declaration text.

Figure 1.17 VHDL OR-gate model (with syntax error).

Figure 1.18 VHDL compilation with a syntax error.

Figure 1.19 Verilog module declaration text.

Figure 1.20 Verilog active low OR-gate model (with syntax error).

Figure 1.21 Verilog compilation with a syntax error.

Figure 1.22 Timing analyzer showing input to output timing delays.

Figure 1.23 Floorplan view showing internal

FPGA placement of OR-gate in LE and I/O pins

Figure 1.24 ORgate design symbol.

orgate

inst

PB1PB1

PB2PB2

LEDLED

Figure 1.14 The Altera DE2 FPGA Development board

Figure 1.15 The Altera DE2 FPGA Development board

9V DC PowerSupply

Connector

27Mhz Oscillator24-bit Audio CODEC

TV Decoder(NTSC/PAL)

PowerON/OFFSwitch USB

Host/SlaveController

Altera USB BlasterController Chipset

Altera EPCS 16Configuration Device

RUN/PROGSwitch forJTAG/AS

Modes

LCD 16x2 Module

7-SEG Display Module

18 Red LEDs

18 Toggle Switches

1MB FlashMemory

(upgradable to4MB)

XSGA10-bit DAC

Ethernet 10/100MController

SD Card Connector

IrDATransceiver8 Green LEDs

SMAExtClk

4 Push-button Switches

90nmCyclone IIFPGA with35K LEs

RS-232Port

Ethernet10/100M Port

XSGAVideo Port

VideoIn

USBHost

LineIn

MicOut

MicInUSB

Device

USBBlaster

Port

50Mhz Oscillator

8MB SDRAM

512KB SRAM

88888888