FPGA Run-time Reconfigurable Placement

transcript

FPGA Run-time Reconfigurable

PlacementPresentation by Brian Leonard

Clemson University

2003 SURE REU Program

Advisor: Ron Sass

Outline

Background Placement Package Online Placement Offline Placement Conclusion

Outline

Background - FPGAs

Field Programmable Gate Array Reconfigurable RTR Architectures

Background - Definitions

Modules Configuration Affinity

Background – Example

Up now

Background – Example

Outline

Placement Package - Representation List of modules

currently on chip List of empty

rectangles

Placement Package - Representation

Placement Package - Algorithms Class PlacementAlgorithm Algorithms

First Fit Best Fit Worst Fit Location Aspect Ratio

Outline

Online Placement - Problem

Java RTR-JVM Multiple Classes and Methods Online Placement

Speed No affinity considerations

Online Placement - Solution

Test Placement Algorithms Chip Utilization Fragmentation Program Speed

Consensus

Outline

Offline Placement - Problem

Large, Fully-Implemented Program More Computation Time Considerations

Affinity Reconfiguration time

Offline Placement - Lattice

Offline Placement - LatticeChip Size = 5

A = 4 B = 1

C = 2 D = 1

Offline Placement - Solution

Place Frontier Configurations Transition Table How to Place

For Reconfiguration For Affinity (run-time speed) Compromise

Outline

Conclusion

Summary Placement Package Online Placement Offline Placement

Future Work Conclusion

Thank you.

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FPGA Run-time Reconfigurable Placement

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