Post on 09-Apr-2016
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IMPLEMENTATION OF CAR PARKING LOT USING FSM MODELLING ON FPGA
ByN.SAI MANI BHARATH
M.Tech 1st YEAREMBEDDED SYSTEMS
ABSTRACT
Car parking system is implemented using Finite State Machine Modelling. The system has two main modules i.e1)Identification module and 2) slot checking module. Identification module identifies the visitor. Slot checking module checks the slot status. These modules are Modelled in HDL and implemented on FPGA. A prototype of parking system is designed with various interfaces like sensor interfacing, stepper motor and LCD.
FSM: State machines or FSM are the heart of any digital design Controller of any processor is about a group of state machines.
There are two types of state machines as classified by the types of outputs generated from each MELAY FSM MOORE FSMMELAY FSM: Mealy State Machine where one or more of the outputs are a function of the present state and
one or more of the inputs. More sensitive to the changes in the inputs Reqiures less no states compared to Moore state machine.MOORE FSM: Moore State Machine where the outputs are only a function of the present state Less sensitivity to changes in inputs Requires more no states.
INTRODUCTION
FSM using Verilog
FSM code should have three sections: Encoding Style . Combinational Part (Next State Logic and output Logic). Sequential Part (State Registers).
FSM Using Verilog Encoding Style:
Binary Encoding: parameter [1:0] S0 = 2’b00; parameter [1:0] S1 = 2’b01; parameter [1:0] S2 = 2’b10; parameter [1:0] S3 = 2’b11;One hot Encoding: parameter [3:0] S0 = 4’b0001; parameter [3:0] S1 = 4’b0010; parameter [3:0] S2 = 4’b0100; parameter [3:0] S3 = 4’b1000;Gray Encoding (Only 1-bit should change from
previous value): parameter [2:0] S0 = 3’b000; parameter [2:0] S1 = 3’b001; parameter [2:0] S2 = 3’b011; parameter [2:0] S3 = 3’b010;
REQUIREMENTS: Xilinx ISE FPGA BOARD LCD DISPLAY MOTOR IR SENSOR MODULES POWER SUPPLY
FPGA
LCD
ULN 2003 STEPPER MOTOR
BLOCK DIAGRAM
POWER SUPPLY
IR SENSOR MODULE
AIR
SENSOR MODULE
B
Xilinx ISE contains all the aspects required for Devolopment flow
Various tools provided by Xilinx are Xilinx Project Navigator Xilinx synthesis tool-XST Xilinx Simulation Tool Impact ModelSim
Xilinx ISE
Project Navigator is a graphical interface for users to access software tools and relevant files associated with a project.
It consists of four windows Source window Process window Transcript window Workplace window
Xilinx project Navigator
PROCESS INVOLVED DURING ENTRANCE
IR SENSOR
RX AIR SENSOR
TX A
IR SENSOR TX B
IR SENSOR RX B
A=0&B=0 A=1&B=0
\ A=1&B=1 A=0&B=1
IR SENSOR TX A
IR SENSOR TX B
IR SENSOR RX B
IR SENSOR RX A
IR SENSOR TX B
IR SENSOR TX A
IR SENSOR RX B
IR SENSOR RX A
IR SENSOR
TX BIR SENSOR
RX B
IR SENSOR TX A
IR SENSOR RX A
PROCESS INVOLVED DURING EXIT
IR SENSOR
RX AIR SENSOR
TX A
IR SENSOR TX B
IR SENSOR RX B
A=0&B=0 A=0&B=1
\ A=1&B=1 A=1&B=0
IR SENSOR TX A
IR SENSOR TX B
IR SENSOR RX B
IR SENSOR RX A
IR SENSOR TX B
IR SENSOR TX A
IR SENSOR RX B
IR SENSOR RX A
IR SENSOR
TX BIR SENSOR
RX B
IR SENSOR TX A
IR SENSOR RX A
S1A=1B=0
S5A=0 B=1
S2A=1B=1
S3A=0B=1
S6A=1B=1
S7A=1B=0
S4ENTER/
1
S8EXIT/1
S0A,B=0
STATE DIAGRAM
There are four major steps involved : Create the design project and HDL codes. Create a Testbench and perform RTL simulation. Add a constraint file and synthesize and implement the
code. Generate and download the configuration file to an
FPGA device.
Steps involved in devolopment of software Process
module car_detector_final( input [1:0] x, input clk,rst, output entry,exit, output [3:0] count ); parameter s0=4'b0000; parameter s1=4'b0001; parameter s2=4'b0010; parameter s3=4'b0011; parameter s4=4'b0100; parameter s5=4'b0101; parameter s6=4'b0110; parameter s7=4'b0111; parameter s8=4'b1000; reg [3:0] state , next_state; always @ (posedge clk)begin if(rst) begin state <=s0; end else state<=next_state; end end module
Verilog code
always @ * begin case(state) s0:next_state=((x==2'b10)?s1:((x==2'b01)?s5:s0)); s1:next_state=((x==2'b11)?s2:((x==2'b10)?s1:s0)); s2:next_state=((x==2'b01)?s3:((x==2'b11)?s2:s0)); s3:next_state=((x==2'b00)?s4:((x==2'b01)?s3:s2)); s4:next_state=((x==2'b10)?s1:s0); s5:next_state=((x==2'b11)?s6:((x==2'b01)?s5:s0)); s6:next_state=((x==2'b10)?s7:((x==2'b11)?s6:s0)); s7:next_state=((x==2'b00)?s8:((x==2'b10)?s7:s6)); s8:next_state=((x==2'b01)?s5:s0); default: next_state=state; endcase end assign entry=(state==s4); assign exit=(state==s8); bin_count b1(.clk(clk),.enclk(entry),.exclk(exit),.rst(rst),.y(count)); endmodule module bin_count(input clk,enclk,exclk,rst, output reg [3:0] y); always @ (posedge clk) begin if(rst) y=4'b0000; else if(enclk==1) y=y+1'b1; else if(exclk==1) y=y-1'b1; end
RTL SCHEMATIC
RTL SCHEMATIC USING Xilinx
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