Global Routing

ENTITY test isport a: in bit;

end ENTITY test;

DRCLVS

ERC

Circuit Design

Functional Designand Logic Design

Physical Design

Physical Verificationand Signoff

Fabrication

SystemSpecification

ArchitecturalDesign

Chip

Packaging and Testing

Chip Planning

Placement

Signal Routing

Partitioning

Timing Closure

Clock Tree Synthesis

2

3

Problem Definition• Input:

Netlist Locations of blocks and locations of pins Technology information Timing budget for, typically, critical nets

• Output: Geometric layouts of all nets

• Objectives: Minimize the total wire length # of vias or just completing all connections without increasing the chip area

• Constraints: Design rules Routing resource capacities Timing budget of each net

Types of Routing Problems

• Fixed-die routing: Chip outline and routing resources are fixed.

• Variable-die routing: New routing tracks can be added as needed.

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5

General Routing Problem

Two phases:

Global Routing Detailed Routing

6

Timing-Driven Routing

GlobalRouting

DetailedRouting

Large Single- Net Routing

Coarse-grain assignment of routes to routing regions

Fine-grain assignment of routes to routing tracks

considering critical nets

Power & Ground routing

Routing

Geometric Techniques

clock routing

Introduction

Multi-Stage Routing of Signal Nets

8

Routing is Hard

• Minimum Steiner Tree Problem: Given a net, find the steiner tree with minimum

length.

• Challenges:NP-Complete! May need to route millions of nets simultaneously

without overlapping Obstacles may exist in the routing region.

Formal Problem Definition

• For delay consideration:Minimize diameter of net

9

10

10

10

5 510

5 5

D= 30

L= 30

D = 20

L= 30

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Formal Problem Definition

D = 6

L = 7

D= 6

L = 6

2

2

11

1

2

2

1

1

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Global Routing

Global routing is divided into 3 phases:

1. Region definition

2. Region assignment

3. Pin assignment to routing regions

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Region Definition

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Region Assignment (Global Routing)

Cell

Cell

Cell

Cell

1

1

1

2

2

14

Cell

Cell

Cell

Cell

1

1

1

2

2

Pin Assignment

Assign pins on routing region boundaries for each net. - Prepare for the detailed routing of each routing

region.

15

Detailed Routing

The actual wires are routed in the channel

• Goal: Produce the shortest wires and consume the least

amount of space

Cell

Cell

Cell

Cell

1

1

1

2

2

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Region Definition

Divide the routing area into routing regions of simple shape (rectangular):

• Channel: Pins on 2 opposite sides.• 2-D Switchbox: Pins on 4 sides.• 3-D Switchbox: Pins on all 6 sides.

Switchbox

Channel

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Detailed Routing Types

• There are different detailed routers for different regions

Switchbox router where therectangle has pins on all foursides.

Channel Router

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2D and 3D Switchboxes

Metal5

Bottom pin connectionon 3D switchbox

3D switchbox

2D switchbox

Pin on channel boundary

Top pin connection on cell

Horizontalchannel

Metal4

Metal3

Metal2

Metal1

Vertical channel

Routing Regions

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Routing Regions inDifferent Design Styles

Gate-Array Standard-Cell Full-Custom

Feedthrough Cell

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Standard cell layout (Two-layer routing)

Channel in Standard Cell Style

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Gcells (Tiles) with macro cell layout

Metal1

Metal2

Metal3

Metal4 etc.

Routing Regions

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Metal1(Standard cells)

Metal3

Metal4 etc.

Routing Regions

Gcells (Tiles) with standard cells

Metal2(Cell ports)

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Metal1(Back-to-back-standard cells)

Metal2(Cell ports)

Metal3

Metal4 etc.

Routing Regions

Gcells (Tiles) with standard cells (back-to-back)

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Routing in Different Design StylesFull-custom design

B

FA

C

D

E

H

V

H

A B

F

D H

V

C E

1

2

3

4

55

B

FA

C

D

E1 23

4

(2 )Channel ordering

B

FA

C

D

E

(1 )Types of channels

Layout is dominated by macro cells and routing regions are non-uniform

5

4

321

25

Routing in Different Design StylesStandard-cell design

A

A

A

A

A

Feedthroughcells

If number of metal layers is limited, feedthrough cells must be used to route across multiple cell rows

Variable-die,standard cell design:

Total height = ΣCell row heights + All channel heights

26

Routing in Different Design Styles

Standard-cell design

Steiner tree solution with minimal wirelength

Steiner tree solution withfewest feedthrough cells

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28

29

Switchbox Routed

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Routing in Different Design Styles

Gate-array design

Availabletracks

Unrouted net

Cell sizes and sizes of routing regions between cells are fixed

Key Task:

- Find a routable solution

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Graph Modeling ofRouting Regions

• Routing context is captured using a graph, where Nodes:

− Routing regions Edges:

− Adjoining regions

Capacities:

− can be associated with both edges and nodes

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1 2 3 4 5

6 7 8 9 10

11 12 13 14 15

16 17 18 19 20

21 22 23 24 25

1 2 3 4 5

6 7 8 9 10

11 12 13 14 15

16 17 18 19 20

21 22 23 24 25

Grid graph model

ggrid = (V,E), where the nodes v V represent the routing grid cells (gcells) and the edges represent connections of grid cell pairs (vi,vj)

Representations of Routing Regions

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1 2 3

4

5

6

7

8

9 1 2 3

4

5

6

7

8

9

Channel connectivity graph

G = (V,E), where the nodes v V represent channels, and the edges E represent adjacencies of the channels

Representations of Routing Regions

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1

2

3

4

5

6

7

8

9

10

11

12

13

14

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Switchbox connectivity (channel intersection) graph

G = (V, E), where the nodes v V represent switchboxes and an edge exists between two nodes if the corresponding switchboxes are on opposite sides of the same channel

Representations of Routing Regions

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Formal Problem Definition

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• Two-layer routing:

• Multilayer routing:

Layerslayer pitch layerd

hLayersσ

)()(

A A

B B

B

B B

BC

C

DC

CD

dpitchh

Horizontal Routing Channel

Channel Capacity• Capacity:

• Number of available routing tracks or columns

)()(

layerd

hlayer

pitch

dpitch = s + w

ws

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Channel Capacity

pitchd

hl l: number of layers in a direction

dpitch: size of largest pitch

1433

422

Capacity

42

• In practice:• Grid lines are the same for all layers

Example:

two horizontal layers

minimum wire width = 3

minimum wire spacing = 3

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Pitch Size Models

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Routing in Different Design Styles

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Global Router

• Typical algorithm steps: Creating global router mesh Reading nets and pins Finding global and local

nets Routing nets

− Length of nets− Capacity of edges− (Noise of nets)

Introduction

ATLAS Basics

ATLAS Plug-in

ATLAS UIs

AtlasDB

ATLAS Engines