Post on 10-Aug-2020
transcript
Greatest Common Divisor Circuit DesignGreatest Common Divisor Circuit Design
ECE261 CMOS VLSI Design
Team Member
Chao Chen Jae Shik Lim
Lei Kong Lingzhao Xie
Agenda
Quick Review and Block DiagramQuick Review and Block Diagram
Module Schematics & Digital Simulation
System Simulation & Layout DRC, LVS Check
Critical path & Area estimation, Power Consumption
Brief Introduction
In mathematics, the greatest common divisor (gcd) is the largest positive integer that divides(gcd) is the largest positive integer that divides the numbers without a remainder.
In our design, a gcd(a,b) function is presented, which returns the greatest common divisor (gcd).
For example gcd(1 10) returns 1 whileFor example, gcd(1,10) returns 1, while gcd(12,9) returns 3.
P i i l f F t GCDPrinciple for Fast GCD
00 01 10 11
00 00 00 00 00
01 00 01 01 01
10 00 01 10 01
11 00 01 01 11
Computation Circuit
Comparatora[3,0]
a=ba>b
Comparator[ , ]
b[3,0]
a<b
MUXOutput
a[ , ]
MUXMUX a
a
SelectorMatrix
GCD
MUXb
Schematics for Comparatorp
Digital Simulation for ComparatorDigital Simulation for Comparatora=7a=7
b=7
a=10
b 7
a=b “1”b “0”
b=7
a=b “0”a>b “1” a>b “0”a>b 1
Schematics for Selector ArraySchematics for Selector Array
Schematic for Selector Arrayy
Digital Sim for Selector ArrayDigital Sim for Selector Array
10
5
5
16-bit selector schematic
Schematics for 2 digit MUXSchematics for 2-digit MUX
Digital Sim for 2-digit MUXDigital Sim for 2 digit MUXWhen SEL Signal is “0”, When SEL Signal is “1”, gselect IN0 select IN1
System SchematicSystem Schematic
Digital Sim of GCD SystemDigital Sim of GCD System
Digital Sim of GCD SystemDigital Sim of GCD System
16-bit selector DRC Result
16-bit selector LVS Result
Selector DRC Result
Selector LVS Result
Adder DRC Result
Adder LVS Result
Comparator DRC Resultp
Comparator LVS Resultp
Top-level DRC Resultp
Top-level LVS Resultp
Floor PlanFloor PlanTop level floor plan of layout design
C
SelectorArray
SelectorArray
Comparator
SelectorArray
SelectorArrayArray Array
Floor PlanFloor PlanTop level floor plan of layout design
d d i iUpdated area estimations
Number of estimated transistor ≈ 6422
Inverter = 1033(2/ea) XOR = 8(8/ea)Inverter = 1033(2/ea) XOR = 8(8/ea)
Transmission Gate = 2048(2/ea)
NAND2 = 36(4/ea) NAND3 = 4(6/ea)
NAND4 1(8/ea)NAND4 = 1(8/ea)
Area per transistor: 40 λ*12 λ(λ is 0.4μm in 0.8 μm technology)
Total estimated Area = 6422 * 40 λ*12 λ * 130% =0.6412mm^2
Power estimationPower estimationDynamic Power Consumption
Assumption
system clock frequency f
activity factor α = 0.1y
no short circuit current (rising and fall time assumed equal)
22DDP C V fα= ⋅ ⋅ ⋅
[ ] 20 1 6422 (12 ) (0 8 / 2 ) (2 / ) 3fF fλ λ[ ] 20.1 6422 (12 ) (0.8 / 2 ) (2 / ) 30.0555 /
m fF m fmW MHz f
λ μ λ μ= ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
= × f
Power estimationPower estimationUsing the simulated latency maximum operational frequency Using the simulated latency, maximum operational frequency
can be estimated.
Maximum frequency = 1 / total latencyMaximum frequency = 1 / total latency
= 1/ 4.2ns = 240 MHz
2DDP C V fα= ⋅ ⋅ ⋅DD f
[ ] 20.1 6422 (12 ) (0.8 / 2 ) (2 / ) 30 0555 / 240
m fF m fW MH MH
λ μ λ μ= ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
0.0555 / 24013.32
mW MHz MHzmW
= ×=
Latency CalculationLatency CalculationFrom analog simulation, we measure latency in critical path
Comparator latency = 3.2nsp y
Selector matrix latency = 1.0 ns
The total latency = 3.2ns + 1.0nsThe total latency 3.2ns 1.0ns
= 4.2ns
Latency Calculationy
Latency Calculationy
Thank you