HDL Bencher

transcript

HDL Bencher

FPGA Design Workshop

For Academic Use OnlyPresentation Name 2

Objectives

After completing this module, you will be able to:

Describe the process to create a testbench for HDL designsReduce testing time by integrating HDL Bencher into Digital

Design Labs

Outline

OverviewCreate a New SourceCreate WaveformsExport TestbenchSummary

HDL Bencher

Creates timing constrained VHDL and Verilog self-checking testbenches

No knowledge of HDL or scripting required

Overview

HDL Bencher helps validate design function and performance

HDL Bencher generates – VHDL or Verilog testbenches– Design specific waveforms– Documentation

Testbenches can be simulated with various simulators– Model Technology– Synopsys

Advantages

No HDL or scripting knowledge required (or even needed!)

No need to manually modify testbenches for each design revision

How It Works

Step 1: Create New Source

Step 2: Draw stimulus and response waveforms

Step 3: Export testbench

Outline

• Overview• Create a New Source• Create Waveforms• Export Testbench• Summary

Create a New Source

HDL Bencher

• Unit under test is analyzed, when selected– Port problems– Syntax violations– Inconsistencies

• Design timing selected– Specify clock timing– Single, multiple, or internal

clocks

HDL Bencher

HDL Bencher Windows

Title bar

Process bar

Port direction

Line numbers

Waveform window

Waveforms

HDL source editor

Outline

• Overview• Create a New Source• Create Waveforms• Export Testbench• Summary

Create Waveforms

Data values– 1, 0 ,X ,Z, U

Assignments– Double-click bit signal to toggle value– Pattern wizard assigns a range of cell values– WaveTable assign signals like a spreadsheet– By default, decimal values are shown in the WaveTable

Waveform values are checked as they are entered– Validation check for non-binary inputs only (for example, hex, or

decimal)

Toggling

Toggling bit values is the easiest way to assign bit signalsSimply click directly on the signal’s waveform at the time where

changes should take place

Click directly on these boxes, at the time where signals should toggle

WaveTable Intended for fast behavioral verificationWaveforms represented as cellsData entered in spreadsheet formatDouble-click a signal at the time it should be changed, to access value

cell editorEnter value and press Return for the next time frameRange validation checked after each entry

Double-click in this area

Enter values in this area

Pattern Wizard

Aids complex waveform inputTo access, click a signal at the time it should be changed to

access value cell editor

Note: light blue background = input assignment, light yellow background = output assignment

Click in this area Click here for Pattern Wizard

Pattern Wizard

Available patterns

Pattern description– Changes depending

on the pattern selected

Count unit in clock cycles

Outline

TestbenchTranslates waveforms to testbenchesWrites out VHDL or Verilog testbenchColor-coded for easy reading and reference Includes

– Library extractions– Log file creation– Procedure check– Input assignments– Output validation– Defined test signals– Delay verification– UUT (Unit Under Test) instantiation

Configuration

• Options Configuration

• Ability to automatically terminate the testbench for export on the last assignment

• VHDL compliance

Testbench• Waveform file extensions are TBW

• Waveform file can be seen in the Sources in Project window of the Project Navigator

• To view testbench: – In Sources in Project Window, select

the TBW file– Then in the Processes for Current

Source window, click View Behavioral Testbench

Outline

Summary

HDL Bencher helps validate design function and performance

The three steps to create a testbench are– Create a new source– Develop waveforms– Export testbench

Writes out VHDL or Verilog testbench

Where Can I learn More?

• The HDL Bencher tool– Help Menu– support.xilinx.com software manuals Development

System Reference Guide HDL Bencher Help

HDL Bencher

Documents